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authorSujith <Sujith.Manoharan@atheros.com>2009-02-09 02:57:12 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:45:05 -0500
commitcbe61d8a41210600bc76b212edcd4dc0f55c014f (patch)
treed8bd8e43d3556c58d410f1bef0d2ca3bf7d75c92 /drivers/net/wireless/ath9k/hw.c
parentba52da58be0acf3b7775972b2b5234ce64388c79 (diff)
ath9k: Merge ath_hal and ath_hal_5416 structures
Finally, merge these structures and have a single HW specific data structure. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath9k/hw.c675
1 files changed, 315 insertions, 360 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 5d7287549c0b..ba908e9f1a8e 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -28,41 +28,45 @@ MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30 30
31static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode); 33 enum ath9k_ht_macmode macmode);
34static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData, 35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value); 36 u32 reg, u32 value);
37static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39 39
40/********************/ 40/********************/
41/* Helper Functions */ 41/* Helper Functions */
42/********************/ 42/********************/
43 43
44static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45{ 45{
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
47 if (!ah->ah_curchan) /* should really check for CCK instead */ 48 if (!ah->ah_curchan) /* should really check for CCK instead */
48 return clks / ATH9K_CLOCK_RATE_CCK; 49 return clks / ATH9K_CLOCK_RATE_CCK;
49 if (conf->channel->band == IEEE80211_BAND_2GHZ) 50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
50 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
51 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
52} 54}
53 55
54static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
55{ 57{
56 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
57 if (conf_is_ht40(conf)) 60 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2; 61 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else 62 else
60 return ath9k_hw_mac_usec(ah, clks); 63 return ath9k_hw_mac_usec(ah, clks);
61} 64}
62 65
63static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64{ 67{
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
66 if (!ah->ah_curchan) /* should really check for CCK instead */ 70 if (!ah->ah_curchan) /* should really check for CCK instead */
67 return usecs *ATH9K_CLOCK_RATE_CCK; 71 return usecs *ATH9K_CLOCK_RATE_CCK;
68 if (conf->channel->band == IEEE80211_BAND_2GHZ) 72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
@@ -70,16 +74,17 @@ static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
70 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
71} 75}
72 76
73static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
74{ 78{
75 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
76 if (conf_is_ht40(conf)) 81 if (conf_is_ht40(conf))
77 return ath9k_hw_mac_clks(ah, usecs) * 2; 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
78 else 83 else
79 return ath9k_hw_mac_clks(ah, usecs); 84 return ath9k_hw_mac_clks(ah, usecs);
80} 85}
81 86
82bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
83{ 88{
84 int i; 89 int i;
85 90
@@ -109,7 +114,7 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
109 return retval; 114 return retval;
110} 115}
111 116
112bool ath9k_get_channel_edges(struct ath_hal *ah, 117bool ath9k_get_channel_edges(struct ath_hw *ah,
113 u16 flags, u16 *low, 118 u16 flags, u16 *low,
114 u16 *high) 119 u16 *high)
115{ 120{
@@ -128,7 +133,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
128 return false; 133 return false;
129} 134}
130 135
131u16 ath9k_hw_computetxtime(struct ath_hal *ah, 136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
132 struct ath_rate_table *rates, 137 struct ath_rate_table *rates,
133 u32 frameLen, u16 rateix, 138 u32 frameLen, u16 rateix,
134 bool shortPreamble) 139 bool shortPreamble)
@@ -184,12 +189,11 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
184 return txTime; 189 return txTime;
185} 190}
186 191
187void ath9k_hw_get_channel_centers(struct ath_hal *ah, 192void ath9k_hw_get_channel_centers(struct ath_hw *ah,
188 struct ath9k_channel *chan, 193 struct ath9k_channel *chan,
189 struct chan_centers *centers) 194 struct chan_centers *centers)
190{ 195{
191 int8_t extoff; 196 int8_t extoff;
192 struct ath_hal_5416 *ahp = AH5416(ah);
193 197
194 if (!IS_CHAN_HT40(chan)) { 198 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center = 199 centers->ctl_center = centers->ext_center =
@@ -212,16 +216,15 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah,
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
213 centers->ext_center = 217 centers->ext_center =
214 centers->synth_center + (extoff * 218 centers->synth_center + (extoff *
215 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 219 ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
216 HT40_CHANNEL_CENTER_SHIFT : 15)); 220 HT40_CHANNEL_CENTER_SHIFT : 15));
217
218} 221}
219 222
220/******************/ 223/******************/
221/* Chip Revisions */ 224/* Chip Revisions */
222/******************/ 225/******************/
223 226
224static void ath9k_hw_read_revisions(struct ath_hal *ah) 227static void ath9k_hw_read_revisions(struct ath_hw *ah)
225{ 228{
226 u32 val; 229 u32 val;
227 230
@@ -244,7 +247,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
244 } 247 }
245} 248}
246 249
247static int ath9k_hw_get_radiorev(struct ath_hal *ah) 250static int ath9k_hw_get_radiorev(struct ath_hw *ah)
248{ 251{
249 u32 val; 252 u32 val;
250 int i; 253 int i;
@@ -263,7 +266,7 @@ static int ath9k_hw_get_radiorev(struct ath_hal *ah)
263/* HW Attach, Detach, Init Routines */ 266/* HW Attach, Detach, Init Routines */
264/************************************/ 267/************************************/
265 268
266static void ath9k_hw_disablepcie(struct ath_hal *ah) 269static void ath9k_hw_disablepcie(struct ath_hw *ah)
267{ 270{
268 if (AR_SREV_9100(ah)) 271 if (AR_SREV_9100(ah))
269 return; 272 return;
@@ -281,7 +284,7 @@ static void ath9k_hw_disablepcie(struct ath_hal *ah)
281 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 284 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
282} 285}
283 286
284static bool ath9k_hw_chip_test(struct ath_hal *ah) 287static bool ath9k_hw_chip_test(struct ath_hw *ah)
285{ 288{
286 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
287 u32 regHold[2]; 290 u32 regHold[2];
@@ -323,6 +326,7 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
323 REG_WRITE(ah, regAddr[i], regHold[i]); 326 REG_WRITE(ah, regAddr[i], regHold[i]);
324 } 327 }
325 udelay(100); 328 udelay(100);
329
326 return true; 330 return true;
327} 331}
328 332
@@ -347,7 +351,7 @@ static const char *ath9k_hw_devname(u16 devid)
347 return NULL; 351 return NULL;
348} 352}
349 353
350static void ath9k_hw_set_defaults(struct ath_hal *ah) 354static void ath9k_hw_set_defaults(struct ath_hw *ah)
351{ 355{
352 int i; 356 int i;
353 357
@@ -387,25 +391,20 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
387 ah->ah_config.intr_mitigation = 1; 391 ah->ah_config.intr_mitigation = 1;
388} 392}
389 393
390static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
391 struct ath_softc *sc, 395 int *status)
392 void __iomem *mem,
393 int *status)
394{ 396{
395 struct ath_hal_5416 *ahp; 397 struct ath_hw *ah;
396 struct ath_hal *ah;
397 398
398 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 399 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
399 if (ahp == NULL) { 400 if (ah == NULL) {
400 DPRINTF(sc, ATH_DBG_FATAL, 401 DPRINTF(sc, ATH_DBG_FATAL,
401 "Cannot allocate memory for state block\n"); 402 "Cannot allocate memory for state block\n");
402 *status = -ENOMEM; 403 *status = -ENOMEM;
403 return NULL; 404 return NULL;
404 } 405 }
405 406
406 ah = &ahp->ah;
407 ah->ah_sc = sc; 407 ah->ah_sc = sc;
408 ah->ah_sh = mem;
409 ah->hw_version.magic = AR5416_MAGIC; 408 ah->hw_version.magic = AR5416_MAGIC;
410 ah->regulatory.country_code = CTRY_DEFAULT; 409 ah->regulatory.country_code = CTRY_DEFAULT;
411 ah->hw_version.devid = devid; 410 ah->hw_version.devid = devid;
@@ -419,24 +418,24 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
419 418
420 ah->regulatory.power_limit = MAX_RATE_POWER; 419 ah->regulatory.power_limit = MAX_RATE_POWER;
421 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; 420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
422 ahp->ah_atimWindow = 0; 421 ah->ah_atimWindow = 0;
423 ahp->ah_diversityControl = ah->ah_config.diversity_control; 422 ah->ah_diversityControl = ah->ah_config.diversity_control;
424 ahp->ah_antennaSwitchSwap = 423 ah->ah_antennaSwitchSwap =
425 ah->ah_config.antenna_switch_swap; 424 ah->ah_config.antenna_switch_swap;
426 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 425 ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
427 ahp->ah_beaconInterval = 100; 426 ah->ah_beaconInterval = 100;
428 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 427 ah->ah_enable32kHzClock = DONT_USE_32KHZ;
429 ahp->ah_slottime = (u32) -1; 428 ah->ah_slottime = (u32) -1;
430 ahp->ah_acktimeout = (u32) -1; 429 ah->ah_acktimeout = (u32) -1;
431 ahp->ah_ctstimeout = (u32) -1; 430 ah->ah_ctstimeout = (u32) -1;
432 ahp->ah_globaltxtimeout = (u32) -1; 431 ah->ah_globaltxtimeout = (u32) -1;
433 432
434 ahp->ah_gBeaconRate = 0; 433 ah->ah_gBeaconRate = 0;
435 434
436 return ahp; 435 return ah;
437} 436}
438 437
439static int ath9k_hw_rfattach(struct ath_hal *ah) 438static int ath9k_hw_rfattach(struct ath_hw *ah)
440{ 439{
441 bool rfStatus = false; 440 bool rfStatus = false;
442 int ecode = 0; 441 int ecode = 0;
@@ -451,7 +450,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
451 return 0; 450 return 0;
452} 451}
453 452
454static int ath9k_hw_rf_claim(struct ath_hal *ah) 453static int ath9k_hw_rf_claim(struct ath_hw *ah)
455{ 454{
456 u32 val; 455 u32 val;
457 456
@@ -480,7 +479,7 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
480 return 0; 479 return 0;
481} 480}
482 481
483static int ath9k_hw_init_macaddr(struct ath_hal *ah) 482static int ath9k_hw_init_macaddr(struct ath_hw *ah)
484{ 483{
485 u32 sum; 484 u32 sum;
486 int i; 485 int i;
@@ -503,55 +502,55 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah)
503 return 0; 502 return 0;
504} 503}
505 504
506static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah) 505static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
507{ 506{
508 u32 rxgain_type; 507 u32 rxgain_type;
509 struct ath_hal_5416 *ahp = AH5416(ah);
510 508
511 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 509 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
512 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); 510 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
513 511
514 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
515 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 513 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
516 ar9280Modes_backoff_13db_rxgain_9280_2, 514 ar9280Modes_backoff_13db_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
518 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
519 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 517 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
520 ar9280Modes_backoff_23db_rxgain_9280_2, 518 ar9280Modes_backoff_23db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
522 else 520 else
523 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 521 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
524 ar9280Modes_original_rxgain_9280_2, 522 ar9280Modes_original_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
526 } else 524 } else {
527 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 525 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2, 526 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 }
530} 529}
531 530
532static void ath9k_hw_init_txgain_ini(struct ath_hal *ah) 531static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
533{ 532{
534 u32 txgain_type; 533 u32 txgain_type;
535 struct ath_hal_5416 *ahp = AH5416(ah);
536 534
537 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 535 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
538 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); 536 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
539 537
540 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
541 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 539 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
542 ar9280Modes_high_power_tx_gain_9280_2, 540 ar9280Modes_high_power_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
544 else 542 else
545 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 543 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
546 ar9280Modes_original_tx_gain_9280_2, 544 ar9280Modes_original_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
548 } else 546 } else {
549 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 547 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2, 548 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 }
552} 551}
553 552
554static int ath9k_hw_post_attach(struct ath_hal *ah) 553static int ath9k_hw_post_attach(struct ath_hw *ah)
555{ 554{
556 int ecode; 555 int ecode;
557 556
@@ -580,33 +579,30 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
580 return 0; 579 return 0;
581} 580}
582 581
583static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 582static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
584 void __iomem *mem, int *status) 583 int *status)
585{ 584{
586 struct ath_hal_5416 *ahp; 585 struct ath_hw *ah;
587 struct ath_hal *ah;
588 int ecode; 586 int ecode;
589 u32 i, j; 587 u32 i, j;
590 588
591 ahp = ath9k_hw_newstate(devid, sc, mem, status); 589 ah = ath9k_hw_newstate(devid, sc, status);
592 if (ahp == NULL) 590 if (ah == NULL)
593 return NULL; 591 return NULL;
594 592
595 ah = &ahp->ah;
596
597 ath9k_hw_set_defaults(ah); 593 ath9k_hw_set_defaults(ah);
598 594
599 if (ah->ah_config.intr_mitigation != 0) 595 if (ah->ah_config.intr_mitigation != 0)
600 ahp->ah_intrMitigation = true; 596 ah->ah_intrMitigation = true;
601 597
602 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
603 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
604 ecode = -EIO; 600 ecode = -EIO;
605 goto bad; 601 goto bad;
606 } 602 }
607 603
608 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
609 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); 605 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
610 ecode = -EIO; 606 ecode = -EIO;
611 goto bad; 607 goto bad;
612 } 608 }
@@ -621,15 +617,14 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
621 } 617 }
622 } 618 }
623 619
624 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
625 "serialize_regmode is %d\n",
626 ah->ah_config.serialize_regmode); 621 ah->ah_config.serialize_regmode);
627 622
628 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && 623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
629 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
630 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && 625 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
631 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 626 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
632 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 627 DPRINTF(sc, ATH_DBG_RESET,
633 "Mac Chip Rev 0x%02x.%x is not supported by " 628 "Mac Chip Rev 0x%02x.%x is not supported by "
634 "this driver\n", ah->hw_version.macVersion, 629 "this driver\n", ah->hw_version.macVersion,
635 ah->hw_version.macRev); 630 ah->hw_version.macRev);
@@ -638,176 +633,176 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
638 } 633 }
639 634
640 if (AR_SREV_9100(ah)) { 635 if (AR_SREV_9100(ah)) {
641 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 636 ah->ah_iqCalData.calData = &iq_cal_multi_sample;
642 ahp->ah_suppCals = IQ_MISMATCH_CAL; 637 ah->ah_suppCals = IQ_MISMATCH_CAL;
643 ah->ah_isPciExpress = false; 638 ah->ah_isPciExpress = false;
644 } 639 }
645 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
646 641
647 if (AR_SREV_9160_10_OR_LATER(ah)) { 642 if (AR_SREV_9160_10_OR_LATER(ah)) {
648 if (AR_SREV_9280_10_OR_LATER(ah)) { 643 if (AR_SREV_9280_10_OR_LATER(ah)) {
649 ahp->ah_iqCalData.calData = &iq_cal_single_sample; 644 ah->ah_iqCalData.calData = &iq_cal_single_sample;
650 ahp->ah_adcGainCalData.calData = 645 ah->ah_adcGainCalData.calData =
651 &adc_gain_cal_single_sample; 646 &adc_gain_cal_single_sample;
652 ahp->ah_adcDcCalData.calData = 647 ah->ah_adcDcCalData.calData =
653 &adc_dc_cal_single_sample; 648 &adc_dc_cal_single_sample;
654 ahp->ah_adcDcCalInitData.calData = 649 ah->ah_adcDcCalInitData.calData =
655 &adc_init_dc_cal; 650 &adc_init_dc_cal;
656 } else { 651 } else {
657 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 652 ah->ah_iqCalData.calData = &iq_cal_multi_sample;
658 ahp->ah_adcGainCalData.calData = 653 ah->ah_adcGainCalData.calData =
659 &adc_gain_cal_multi_sample; 654 &adc_gain_cal_multi_sample;
660 ahp->ah_adcDcCalData.calData = 655 ah->ah_adcDcCalData.calData =
661 &adc_dc_cal_multi_sample; 656 &adc_dc_cal_multi_sample;
662 ahp->ah_adcDcCalInitData.calData = 657 ah->ah_adcDcCalInitData.calData =
663 &adc_init_dc_cal; 658 &adc_init_dc_cal;
664 } 659 }
665 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 660 ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
666 } 661 }
667 662
668 if (AR_SREV_9160(ah)) { 663 if (AR_SREV_9160(ah)) {
669 ah->ah_config.enable_ani = 1; 664 ah->ah_config.enable_ani = 1;
670 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 665 ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
671 ATH9K_ANI_FIRSTEP_LEVEL); 666 ATH9K_ANI_FIRSTEP_LEVEL);
672 } else { 667 } else {
673 ahp->ah_ani_function = ATH9K_ANI_ALL; 668 ah->ah_ani_function = ATH9K_ANI_ALL;
674 if (AR_SREV_9280_10_OR_LATER(ah)) { 669 if (AR_SREV_9280_10_OR_LATER(ah)) {
675 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 670 ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
676 } 671 }
677 } 672 }
678 673
679 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 674 DPRINTF(sc, ATH_DBG_RESET,
680 "This Mac Chip Rev 0x%02x.%x is \n", 675 "This Mac Chip Rev 0x%02x.%x is \n",
681 ah->hw_version.macVersion, ah->hw_version.macRev); 676 ah->hw_version.macVersion, ah->hw_version.macRev);
682 677
683 if (AR_SREV_9285_12_OR_LATER(ah)) { 678 if (AR_SREV_9285_12_OR_LATER(ah)) {
684 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, 679 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2,
685 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
686 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, 681 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2,
687 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
688 683
689 if (ah->ah_config.pcie_clock_req) { 684 if (ah->ah_config.pcie_clock_req) {
690 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 685 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
691 ar9285PciePhy_clkreq_off_L1_9285_1_2, 686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
692 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
693 } else { 688 } else {
694 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 689 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
695 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
696 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
697 2); 692 2);
698 } 693 }
699 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
700 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, 695 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285,
701 ARRAY_SIZE(ar9285Modes_9285), 6); 696 ARRAY_SIZE(ar9285Modes_9285), 6);
702 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, 697 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285,
703 ARRAY_SIZE(ar9285Common_9285), 2); 698 ARRAY_SIZE(ar9285Common_9285), 2);
704 699
705 if (ah->ah_config.pcie_clock_req) { 700 if (ah->ah_config.pcie_clock_req) {
706 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 701 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
707 ar9285PciePhy_clkreq_off_L1_9285, 702 ar9285PciePhy_clkreq_off_L1_9285,
708 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
709 } else { 704 } else {
710 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 705 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
711 ar9285PciePhy_clkreq_always_on_L1_9285, 706 ar9285PciePhy_clkreq_always_on_L1_9285,
712 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
713 } 708 }
714 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
715 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 710 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2,
716 ARRAY_SIZE(ar9280Modes_9280_2), 6); 711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
717 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 712 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2,
718 ARRAY_SIZE(ar9280Common_9280_2), 2); 713 ARRAY_SIZE(ar9280Common_9280_2), 2);
719 714
720 if (ah->ah_config.pcie_clock_req) { 715 if (ah->ah_config.pcie_clock_req) {
721 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 716 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
722 ar9280PciePhy_clkreq_off_L1_9280, 717 ar9280PciePhy_clkreq_off_L1_9280,
723 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
724 } else { 719 } else {
725 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 720 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
726 ar9280PciePhy_clkreq_always_on_L1_9280, 721 ar9280PciePhy_clkreq_always_on_L1_9280,
727 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
728 } 723 }
729 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 724 INIT_INI_ARRAY(&ah->ah_iniModesAdditional,
730 ar9280Modes_fast_clock_9280_2, 725 ar9280Modes_fast_clock_9280_2,
731 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
732 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 728 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280,
734 ARRAY_SIZE(ar9280Modes_9280), 6); 729 ARRAY_SIZE(ar9280Modes_9280), 6);
735 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, 730 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280,
736 ARRAY_SIZE(ar9280Common_9280), 2); 731 ARRAY_SIZE(ar9280Common_9280), 2);
737 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
738 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, 733 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160,
739 ARRAY_SIZE(ar5416Modes_9160), 6); 734 ARRAY_SIZE(ar5416Modes_9160), 6);
740 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, 735 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160,
741 ARRAY_SIZE(ar5416Common_9160), 2); 736 ARRAY_SIZE(ar5416Common_9160), 2);
742 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, 737 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160,
743 ARRAY_SIZE(ar5416Bank0_9160), 2); 738 ARRAY_SIZE(ar5416Bank0_9160), 2);
744 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, 739 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
745 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
746 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, 741 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160,
747 ARRAY_SIZE(ar5416Bank1_9160), 2); 742 ARRAY_SIZE(ar5416Bank1_9160), 2);
748 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, 743 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160,
749 ARRAY_SIZE(ar5416Bank2_9160), 2); 744 ARRAY_SIZE(ar5416Bank2_9160), 2);
750 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, 745 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160,
751 ARRAY_SIZE(ar5416Bank3_9160), 3); 746 ARRAY_SIZE(ar5416Bank3_9160), 3);
752 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, 747 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160,
753 ARRAY_SIZE(ar5416Bank6_9160), 3); 748 ARRAY_SIZE(ar5416Bank6_9160), 3);
754 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, 749 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160,
755 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
756 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, 751 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160,
757 ARRAY_SIZE(ar5416Bank7_9160), 2); 752 ARRAY_SIZE(ar5416Bank7_9160), 2);
758 if (AR_SREV_9160_11(ah)) { 753 if (AR_SREV_9160_11(ah)) {
759 INIT_INI_ARRAY(&ahp->ah_iniAddac, 754 INIT_INI_ARRAY(&ah->ah_iniAddac,
760 ar5416Addac_91601_1, 755 ar5416Addac_91601_1,
761 ARRAY_SIZE(ar5416Addac_91601_1), 2); 756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
762 } else { 757 } else {
763 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, 758 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160,
764 ARRAY_SIZE(ar5416Addac_9160), 2); 759 ARRAY_SIZE(ar5416Addac_9160), 2);
765 } 760 }
766 } else if (AR_SREV_9100_OR_LATER(ah)) { 761 } else if (AR_SREV_9100_OR_LATER(ah)) {
767 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, 762 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100,
768 ARRAY_SIZE(ar5416Modes_9100), 6); 763 ARRAY_SIZE(ar5416Modes_9100), 6);
769 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, 764 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100,
770 ARRAY_SIZE(ar5416Common_9100), 2); 765 ARRAY_SIZE(ar5416Common_9100), 2);
771 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, 766 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100,
772 ARRAY_SIZE(ar5416Bank0_9100), 2); 767 ARRAY_SIZE(ar5416Bank0_9100), 2);
773 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, 768 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
774 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
775 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, 770 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100,
776 ARRAY_SIZE(ar5416Bank1_9100), 2); 771 ARRAY_SIZE(ar5416Bank1_9100), 2);
777 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, 772 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100,
778 ARRAY_SIZE(ar5416Bank2_9100), 2); 773 ARRAY_SIZE(ar5416Bank2_9100), 2);
779 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, 774 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100,
780 ARRAY_SIZE(ar5416Bank3_9100), 3); 775 ARRAY_SIZE(ar5416Bank3_9100), 3);
781 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, 776 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100,
782 ARRAY_SIZE(ar5416Bank6_9100), 3); 777 ARRAY_SIZE(ar5416Bank6_9100), 3);
783 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, 778 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100,
784 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, 780 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100,
786 ARRAY_SIZE(ar5416Bank7_9100), 2); 781 ARRAY_SIZE(ar5416Bank7_9100), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, 782 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100,
788 ARRAY_SIZE(ar5416Addac_9100), 2); 783 ARRAY_SIZE(ar5416Addac_9100), 2);
789 } else { 784 } else {
790 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, 785 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes,
791 ARRAY_SIZE(ar5416Modes), 6); 786 ARRAY_SIZE(ar5416Modes), 6);
792 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, 787 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common,
793 ARRAY_SIZE(ar5416Common), 2); 788 ARRAY_SIZE(ar5416Common), 2);
794 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, 789 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0,
795 ARRAY_SIZE(ar5416Bank0), 2); 790 ARRAY_SIZE(ar5416Bank0), 2);
796 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, 791 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain,
797 ARRAY_SIZE(ar5416BB_RfGain), 3); 792 ARRAY_SIZE(ar5416BB_RfGain), 3);
798 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, 793 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1,
799 ARRAY_SIZE(ar5416Bank1), 2); 794 ARRAY_SIZE(ar5416Bank1), 2);
800 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, 795 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2,
801 ARRAY_SIZE(ar5416Bank2), 2); 796 ARRAY_SIZE(ar5416Bank2), 2);
802 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, 797 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3,
803 ARRAY_SIZE(ar5416Bank3), 3); 798 ARRAY_SIZE(ar5416Bank3), 3);
804 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, 799 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6,
805 ARRAY_SIZE(ar5416Bank6), 3); 800 ARRAY_SIZE(ar5416Bank6), 3);
806 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, 801 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC,
807 ARRAY_SIZE(ar5416Bank6TPC), 3); 802 ARRAY_SIZE(ar5416Bank6TPC), 3);
808 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, 803 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7,
809 ARRAY_SIZE(ar5416Bank7), 2); 804 ARRAY_SIZE(ar5416Bank7), 2);
810 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, 805 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac,
811 ARRAY_SIZE(ar5416Addac), 2); 806 ARRAY_SIZE(ar5416Addac), 2);
812 } 807 }
813 808
@@ -829,22 +824,22 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
829 ath9k_hw_init_txgain_ini(ah); 824 ath9k_hw_init_txgain_ini(ah);
830 825
831 if (ah->hw_version.devid == AR9280_DEVID_PCI) { 826 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
832 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 827 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
833 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 828 u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
834 829
835 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { 830 for (j = 1; j < ah->ah_iniModes.ia_columns; j++) {
836 u32 val = INI_RA(&ahp->ah_iniModes, i, j); 831 u32 val = INI_RA(&ah->ah_iniModes, i, j);
837 832
838 INI_RA(&ahp->ah_iniModes, i, j) = 833 INI_RA(&ah->ah_iniModes, i, j) =
839 ath9k_hw_ini_fixup(ah, 834 ath9k_hw_ini_fixup(ah,
840 &ahp->ah_eeprom.def, 835 &ah->ah_eeprom.def,
841 reg, val); 836 reg, val);
842 } 837 }
843 } 838 }
844 } 839 }
845 840
846 if (!ath9k_hw_fill_cap_info(ah)) { 841 if (!ath9k_hw_fill_cap_info(ah)) {
847 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 842 DPRINTF(sc, ATH_DBG_RESET,
848 "failed ath9k_hw_fill_cap_info\n"); 843 "failed ath9k_hw_fill_cap_info\n");
849 ecode = -EINVAL; 844 ecode = -EINVAL;
850 goto bad; 845 goto bad;
@@ -852,7 +847,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
852 847
853 ecode = ath9k_hw_init_macaddr(ah); 848 ecode = ath9k_hw_init_macaddr(ah);
854 if (ecode != 0) { 849 if (ecode != 0) {
855 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 850 DPRINTF(sc, ATH_DBG_RESET,
856 "failed initializing mac address\n"); 851 "failed initializing mac address\n");
857 goto bad; 852 goto bad;
858 } 853 }
@@ -866,15 +861,15 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
866 861
867 return ah; 862 return ah;
868bad: 863bad:
869 if (ahp) 864 if (ah)
870 ath9k_hw_detach((struct ath_hal *) ahp); 865 ath9k_hw_detach(ah);
871 if (status) 866 if (status)
872 *status = ecode; 867 *status = ecode;
873 868
874 return NULL; 869 return NULL;
875} 870}
876 871
877static void ath9k_hw_init_bb(struct ath_hal *ah, 872static void ath9k_hw_init_bb(struct ath_hw *ah,
878 struct ath9k_channel *chan) 873 struct ath9k_channel *chan)
879{ 874{
880 u32 synthDelay; 875 u32 synthDelay;
@@ -890,7 +885,7 @@ static void ath9k_hw_init_bb(struct ath_hal *ah,
890 udelay(synthDelay + BASE_ACTIVATE_DELAY); 885 udelay(synthDelay + BASE_ACTIVATE_DELAY);
891} 886}
892 887
893static void ath9k_hw_init_qos(struct ath_hal *ah) 888static void ath9k_hw_init_qos(struct ath_hw *ah)
894{ 889{
895 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 890 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
896 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 891 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
@@ -907,7 +902,7 @@ static void ath9k_hw_init_qos(struct ath_hal *ah)
907 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 902 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
908} 903}
909 904
910static void ath9k_hw_init_pll(struct ath_hal *ah, 905static void ath9k_hw_init_pll(struct ath_hw *ah,
911 struct ath9k_channel *chan) 906 struct ath9k_channel *chan)
912{ 907{
913 u32 pll; 908 u32 pll;
@@ -975,13 +970,12 @@ static void ath9k_hw_init_pll(struct ath_hal *ah,
975 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 970 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
976} 971}
977 972
978static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 973static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
979{ 974{
980 struct ath_hal_5416 *ahp = AH5416(ah);
981 int rx_chainmask, tx_chainmask; 975 int rx_chainmask, tx_chainmask;
982 976
983 rx_chainmask = ahp->ah_rxchainmask; 977 rx_chainmask = ah->ah_rxchainmask;
984 tx_chainmask = ahp->ah_txchainmask; 978 tx_chainmask = ah->ah_txchainmask;
985 979
986 switch (rx_chainmask) { 980 switch (rx_chainmask) {
987 case 0x5: 981 case 0x5:
@@ -1013,28 +1007,26 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1013 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1007 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1014} 1008}
1015 1009
1016static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, 1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1017 enum nl80211_iftype opmode) 1011 enum nl80211_iftype opmode)
1018{ 1012{
1019 struct ath_hal_5416 *ahp = AH5416(ah); 1013 ah->ah_maskReg = AR_IMR_TXERR |
1020
1021 ahp->ah_maskReg = AR_IMR_TXERR |
1022 AR_IMR_TXURN | 1014 AR_IMR_TXURN |
1023 AR_IMR_RXERR | 1015 AR_IMR_RXERR |
1024 AR_IMR_RXORN | 1016 AR_IMR_RXORN |
1025 AR_IMR_BCNMISC; 1017 AR_IMR_BCNMISC;
1026 1018
1027 if (ahp->ah_intrMitigation) 1019 if (ah->ah_intrMitigation)
1028 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1020 ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1029 else 1021 else
1030 ahp->ah_maskReg |= AR_IMR_RXOK; 1022 ah->ah_maskReg |= AR_IMR_RXOK;
1031 1023
1032 ahp->ah_maskReg |= AR_IMR_TXOK; 1024 ah->ah_maskReg |= AR_IMR_TXOK;
1033 1025
1034 if (opmode == NL80211_IFTYPE_AP) 1026 if (opmode == NL80211_IFTYPE_AP)
1035 ahp->ah_maskReg |= AR_IMR_MIB; 1027 ah->ah_maskReg |= AR_IMR_MIB;
1036 1028
1037 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 1029 REG_WRITE(ah, AR_IMR, ah->ah_maskReg);
1038 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1039 1031
1040 if (!AR_SREV_9100(ah)) { 1032 if (!AR_SREV_9100(ah)) {
@@ -1044,72 +1036,64 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1044 } 1036 }
1045} 1037}
1046 1038
1047static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) 1039static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1048{ 1040{
1049 struct ath_hal_5416 *ahp = AH5416(ah);
1050
1051 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1052 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1053 ahp->ah_acktimeout = (u32) -1; 1043 ah->ah_acktimeout = (u32) -1;
1054 return false; 1044 return false;
1055 } else { 1045 } else {
1056 REG_RMW_FIELD(ah, AR_TIME_OUT, 1046 REG_RMW_FIELD(ah, AR_TIME_OUT,
1057 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1058 ahp->ah_acktimeout = us; 1048 ah->ah_acktimeout = us;
1059 return true; 1049 return true;
1060 } 1050 }
1061} 1051}
1062 1052
1063static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) 1053static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1064{ 1054{
1065 struct ath_hal_5416 *ahp = AH5416(ah);
1066
1067 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1068 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1069 ahp->ah_ctstimeout = (u32) -1; 1057 ah->ah_ctstimeout = (u32) -1;
1070 return false; 1058 return false;
1071 } else { 1059 } else {
1072 REG_RMW_FIELD(ah, AR_TIME_OUT, 1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1073 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1074 ahp->ah_ctstimeout = us; 1062 ah->ah_ctstimeout = us;
1075 return true; 1063 return true;
1076 } 1064 }
1077} 1065}
1078 1066
1079static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) 1067static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1080{ 1068{
1081 struct ath_hal_5416 *ahp = AH5416(ah);
1082
1083 if (tu > 0xFFFF) { 1069 if (tu > 0xFFFF) {
1084 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1085 "bad global tx timeout %u\n", tu); 1071 "bad global tx timeout %u\n", tu);
1086 ahp->ah_globaltxtimeout = (u32) -1; 1072 ah->ah_globaltxtimeout = (u32) -1;
1087 return false; 1073 return false;
1088 } else { 1074 } else {
1089 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1090 ahp->ah_globaltxtimeout = tu; 1076 ah->ah_globaltxtimeout = tu;
1091 return true; 1077 return true;
1092 } 1078 }
1093} 1079}
1094 1080
1095static void ath9k_hw_init_user_settings(struct ath_hal *ah) 1081static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1096{ 1082{
1097 struct ath_hal_5416 *ahp = AH5416(ah); 1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n",
1084 ah->ah_miscMode);
1098 1085
1099 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n", 1086 if (ah->ah_miscMode != 0)
1100 ahp->ah_miscMode);
1101
1102 if (ahp->ah_miscMode != 0)
1103 REG_WRITE(ah, AR_PCU_MISC, 1087 REG_WRITE(ah, AR_PCU_MISC,
1104 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); 1088 REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode);
1105 if (ahp->ah_slottime != (u32) -1) 1089 if (ah->ah_slottime != (u32) -1)
1106 ath9k_hw_setslottime(ah, ahp->ah_slottime); 1090 ath9k_hw_setslottime(ah, ah->ah_slottime);
1107 if (ahp->ah_acktimeout != (u32) -1) 1091 if (ah->ah_acktimeout != (u32) -1)
1108 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); 1092 ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout);
1109 if (ahp->ah_ctstimeout != (u32) -1) 1093 if (ah->ah_ctstimeout != (u32) -1)
1110 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); 1094 ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout);
1111 if (ahp->ah_globaltxtimeout != (u32) -1) 1095 if (ah->ah_globaltxtimeout != (u32) -1)
1112 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); 1096 ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout);
1113} 1097}
1114 1098
1115const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1099const char *ath9k_hw_probe(u16 vendorid, u16 devid)
@@ -1118,7 +1102,7 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1118 ath9k_hw_devname(devid) : NULL; 1102 ath9k_hw_devname(devid) : NULL;
1119} 1103}
1120 1104
1121void ath9k_hw_detach(struct ath_hal *ah) 1105void ath9k_hw_detach(struct ath_hw *ah)
1122{ 1106{
1123 if (!AR_SREV_9100(ah)) 1107 if (!AR_SREV_9100(ah))
1124 ath9k_hw_ani_detach(ah); 1108 ath9k_hw_ani_detach(ah);
@@ -1128,10 +1112,9 @@ void ath9k_hw_detach(struct ath_hal *ah)
1128 kfree(ah); 1112 kfree(ah);
1129} 1113}
1130 1114
1131struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, 1115struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1132 void __iomem *mem, int *error)
1133{ 1116{
1134 struct ath_hal *ah = NULL; 1117 struct ath_hw *ah = NULL;
1135 1118
1136 switch (devid) { 1119 switch (devid) {
1137 case AR5416_DEVID_PCI: 1120 case AR5416_DEVID_PCI:
@@ -1141,7 +1124,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1141 case AR9280_DEVID_PCI: 1124 case AR9280_DEVID_PCI:
1142 case AR9280_DEVID_PCIE: 1125 case AR9280_DEVID_PCIE:
1143 case AR9285_DEVID_PCIE: 1126 case AR9285_DEVID_PCIE:
1144 ah = ath9k_hw_do_attach(devid, sc, mem, error); 1127 ah = ath9k_hw_do_attach(devid, sc, error);
1145 break; 1128 break;
1146 default: 1129 default:
1147 *error = -ENXIO; 1130 *error = -ENXIO;
@@ -1155,7 +1138,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1155/* INI */ 1138/* INI */
1156/*******/ 1139/*******/
1157 1140
1158static void ath9k_hw_override_ini(struct ath_hal *ah, 1141static void ath9k_hw_override_ini(struct ath_hw *ah,
1159 struct ath9k_channel *chan) 1142 struct ath9k_channel *chan)
1160{ 1143{
1161 /* 1144 /*
@@ -1173,7 +1156,7 @@ static void ath9k_hw_override_ini(struct ath_hal *ah,
1173 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1156 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1174} 1157}
1175 1158
1176static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, 1159static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1177 struct ar5416_eeprom_def *pEepData, 1160 struct ar5416_eeprom_def *pEepData,
1178 u32 reg, u32 value) 1161 u32 reg, u32 value)
1179{ 1162{
@@ -1207,24 +1190,21 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1207 return value; 1190 return value;
1208} 1191}
1209 1192
1210static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 1193static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1211 struct ar5416_eeprom_def *pEepData, 1194 struct ar5416_eeprom_def *pEepData,
1212 u32 reg, u32 value) 1195 u32 reg, u32 value)
1213{ 1196{
1214 struct ath_hal_5416 *ahp = AH5416(ah); 1197 if (ah->ah_eep_map == EEP_MAP_4KBITS)
1215
1216 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1217 return value; 1198 return value;
1218 else 1199 else
1219 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1220} 1201}
1221 1202
1222static int ath9k_hw_process_ini(struct ath_hal *ah, 1203static int ath9k_hw_process_ini(struct ath_hw *ah,
1223 struct ath9k_channel *chan, 1204 struct ath9k_channel *chan,
1224 enum ath9k_ht_macmode macmode) 1205 enum ath9k_ht_macmode macmode)
1225{ 1206{
1226 int i, regWrites = 0; 1207 int i, regWrites = 0;
1227 struct ath_hal_5416 *ahp = AH5416(ah);
1228 struct ieee80211_channel *channel = chan->chan; 1208 struct ieee80211_channel *channel = chan->chan;
1229 u32 modesIndex, freqIndex; 1209 u32 modesIndex, freqIndex;
1230 int status; 1210 int status;
@@ -1257,35 +1237,33 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1257 } 1237 }
1258 1238
1259 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1239 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1260
1261 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1240 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1262
1263 ath9k_hw_set_addac(ah, chan); 1241 ath9k_hw_set_addac(ah, chan);
1264 1242
1265 if (AR_SREV_5416_V22_OR_LATER(ah)) { 1243 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1266 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); 1244 REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites);
1267 } else { 1245 } else {
1268 struct ar5416IniArray temp; 1246 struct ar5416IniArray temp;
1269 u32 addacSize = 1247 u32 addacSize =
1270 sizeof(u32) * ahp->ah_iniAddac.ia_rows * 1248 sizeof(u32) * ah->ah_iniAddac.ia_rows *
1271 ahp->ah_iniAddac.ia_columns; 1249 ah->ah_iniAddac.ia_columns;
1272 1250
1273 memcpy(ahp->ah_addac5416_21, 1251 memcpy(ah->ah_addac5416_21,
1274 ahp->ah_iniAddac.ia_array, addacSize); 1252 ah->ah_iniAddac.ia_array, addacSize);
1275 1253
1276 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; 1254 (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0;
1277 1255
1278 temp.ia_array = ahp->ah_addac5416_21; 1256 temp.ia_array = ah->ah_addac5416_21;
1279 temp.ia_columns = ahp->ah_iniAddac.ia_columns; 1257 temp.ia_columns = ah->ah_iniAddac.ia_columns;
1280 temp.ia_rows = ahp->ah_iniAddac.ia_rows; 1258 temp.ia_rows = ah->ah_iniAddac.ia_rows;
1281 REG_WRITE_ARRAY(&temp, 1, regWrites); 1259 REG_WRITE_ARRAY(&temp, 1, regWrites);
1282 } 1260 }
1283 1261
1284 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1285 1263
1286 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 1264 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
1287 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 1265 u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
1288 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); 1266 u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex);
1289 1267
1290 REG_WRITE(ah, reg, val); 1268 REG_WRITE(ah, reg, val);
1291 1269
@@ -1298,14 +1276,14 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1298 } 1276 }
1299 1277
1300 if (AR_SREV_9280(ah)) 1278 if (AR_SREV_9280(ah))
1301 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); 1279 REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites);
1302 1280
1303 if (AR_SREV_9280(ah)) 1281 if (AR_SREV_9280(ah))
1304 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); 1282 REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites);
1305 1283
1306 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { 1284 for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) {
1307 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); 1285 u32 reg = INI_RA(&ah->ah_iniCommon, i, 0);
1308 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); 1286 u32 val = INI_RA(&ah->ah_iniCommon, i, 1);
1309 1287
1310 REG_WRITE(ah, reg, val); 1288 REG_WRITE(ah, reg, val);
1311 1289
@@ -1320,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1320 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1321 1299
1322 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1323 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, 1301 REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex,
1324 regWrites); 1302 regWrites);
1325 } 1303 }
1326 1304
@@ -1353,7 +1331,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1353/* Reset and Channel Switching Routines */ 1331/* Reset and Channel Switching Routines */
1354/****************************************/ 1332/****************************************/
1355 1333
1356static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) 1334static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1357{ 1335{
1358 u32 rfMode = 0; 1336 u32 rfMode = 0;
1359 1337
@@ -1373,12 +1351,12 @@ static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1373 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1351 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1374} 1352}
1375 1353
1376static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) 1354static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1377{ 1355{
1378 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1356 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1379} 1357}
1380 1358
1381static inline void ath9k_hw_set_dma(struct ath_hal *ah) 1359static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1382{ 1360{
1383 u32 regval; 1361 u32 regval;
1384 1362
@@ -1404,7 +1382,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1404 } 1382 }
1405} 1383}
1406 1384
1407static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) 1385static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1408{ 1386{
1409 u32 val; 1387 u32 val;
1410 1388
@@ -1428,7 +1406,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1428 } 1406 }
1429} 1407}
1430 1408
1431static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1409static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1432 u32 coef_scaled, 1410 u32 coef_scaled,
1433 u32 *coef_mantissa, 1411 u32 *coef_mantissa,
1434 u32 *coef_exponent) 1412 u32 *coef_exponent)
@@ -1447,7 +1425,7 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1447 *coef_exponent = coef_exp - 16; 1425 *coef_exponent = coef_exp - 16;
1448} 1426}
1449 1427
1450static void ath9k_hw_set_delta_slope(struct ath_hal *ah, 1428static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1451 struct ath9k_channel *chan) 1429 struct ath9k_channel *chan)
1452{ 1430{
1453 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1431 u32 coef_scaled, ds_coef_exp, ds_coef_man;
@@ -1481,7 +1459,7 @@ static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1481 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1459 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1482} 1460}
1483 1461
1484static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) 1462static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1485{ 1463{
1486 u32 rst_flags; 1464 u32 rst_flags;
1487 u32 tmpReg; 1465 u32 tmpReg;
@@ -1529,7 +1507,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1529 return true; 1507 return true;
1530} 1508}
1531 1509
1532static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) 1510static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1533{ 1511{
1534 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1535 AR_RTC_FORCE_WAKE_ON_INT); 1513 AR_RTC_FORCE_WAKE_ON_INT);
@@ -1550,7 +1528,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1550 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1528 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1551} 1529}
1552 1530
1553static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) 1531static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1554{ 1532{
1555 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1533 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1556 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1534 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
@@ -1568,12 +1546,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1568 } 1546 }
1569} 1547}
1570 1548
1571static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 1549static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1572 enum ath9k_ht_macmode macmode) 1550 enum ath9k_ht_macmode macmode)
1573{ 1551{
1574 u32 phymode; 1552 u32 phymode;
1575 u32 enableDacFifo = 0; 1553 u32 enableDacFifo = 0;
1576 struct ath_hal_5416 *ahp = AH5416(ah);
1577 1554
1578 if (AR_SREV_9285_10_OR_LATER(ah)) 1555 if (AR_SREV_9285_10_OR_LATER(ah))
1579 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1556 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
@@ -1589,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1589 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1566 (chan->chanmode == CHANNEL_G_HT40PLUS))
1590 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1591 1568
1592 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1569 if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1593 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1594 } 1571 }
1595 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1572 REG_WRITE(ah, AR_PHY_TURBO, phymode);
@@ -1600,27 +1577,23 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1600 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1577 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1601} 1578}
1602 1579
1603static bool ath9k_hw_chip_reset(struct ath_hal *ah, 1580static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1604 struct ath9k_channel *chan) 1581 struct ath9k_channel *chan)
1605{ 1582{
1606 struct ath_hal_5416 *ahp = AH5416(ah);
1607
1608 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1583 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1609 return false; 1584 return false;
1610 1585
1611 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1612 return false; 1587 return false;
1613 1588
1614 ahp->ah_chipFullSleep = false; 1589 ah->ah_chipFullSleep = false;
1615
1616 ath9k_hw_init_pll(ah, chan); 1590 ath9k_hw_init_pll(ah, chan);
1617
1618 ath9k_hw_set_rfmode(ah, chan); 1591 ath9k_hw_set_rfmode(ah, chan);
1619 1592
1620 return true; 1593 return true;
1621} 1594}
1622 1595
1623static bool ath9k_hw_channel_change(struct ath_hal *ah, 1596static bool ath9k_hw_channel_change(struct ath_hw *ah,
1624 struct ath9k_channel *chan, 1597 struct ath9k_channel *chan,
1625 enum ath9k_ht_macmode macmode) 1598 enum ath9k_ht_macmode macmode)
1626{ 1599{
@@ -1694,7 +1667,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1694 return true; 1667 return true;
1695} 1668}
1696 1669
1697static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1670static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1698{ 1671{
1699 int bb_spur = AR_NO_SPUR; 1672 int bb_spur = AR_NO_SPUR;
1700 int freq; 1673 int freq;
@@ -1944,7 +1917,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel
1944 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 1917 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1945} 1918}
1946 1919
1947static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1920static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1948{ 1921{
1949 int bb_spur = AR_NO_SPUR; 1922 int bb_spur = AR_NO_SPUR;
1950 int bin, cur_bin; 1923 int bin, cur_bin;
@@ -2145,27 +2118,26 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2145 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2118 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2146} 2119}
2147 2120
2148int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 2121int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2149 bool bChannelChange) 2122 bool bChannelChange)
2150{ 2123{
2151 u32 saveLedState; 2124 u32 saveLedState;
2152 struct ath_softc *sc = ah->ah_sc; 2125 struct ath_softc *sc = ah->ah_sc;
2153 struct ath_hal_5416 *ahp = AH5416(ah);
2154 struct ath9k_channel *curchan = ah->ah_curchan; 2126 struct ath9k_channel *curchan = ah->ah_curchan;
2155 u32 saveDefAntenna; 2127 u32 saveDefAntenna;
2156 u32 macStaId1; 2128 u32 macStaId1;
2157 int i, rx_chainmask, r; 2129 int i, rx_chainmask, r;
2158 2130
2159 ahp->ah_extprotspacing = sc->ht_extprotspacing; 2131 ah->ah_extprotspacing = sc->ht_extprotspacing;
2160 ahp->ah_txchainmask = sc->tx_chainmask; 2132 ah->ah_txchainmask = sc->tx_chainmask;
2161 ahp->ah_rxchainmask = sc->rx_chainmask; 2133 ah->ah_rxchainmask = sc->rx_chainmask;
2162 2134
2163 if (AR_SREV_9285(ah)) { 2135 if (AR_SREV_9285(ah)) {
2164 ahp->ah_txchainmask &= 0x1; 2136 ah->ah_txchainmask &= 0x1;
2165 ahp->ah_rxchainmask &= 0x1; 2137 ah->ah_rxchainmask &= 0x1;
2166 } else if (AR_SREV_9280(ah)) { 2138 } else if (AR_SREV_9280(ah)) {
2167 ahp->ah_txchainmask &= 0x3; 2139 ah->ah_txchainmask &= 0x3;
2168 ahp->ah_rxchainmask &= 0x3; 2140 ah->ah_rxchainmask &= 0x3;
2169 } 2141 }
2170 2142
2171 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
@@ -2175,7 +2147,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2175 ath9k_hw_getnf(ah, curchan); 2147 ath9k_hw_getnf(ah, curchan);
2176 2148
2177 if (bChannelChange && 2149 if (bChannelChange &&
2178 (ahp->ah_chipFullSleep != true) && 2150 (ah->ah_chipFullSleep != true) &&
2179 (ah->ah_curchan != NULL) && 2151 (ah->ah_curchan != NULL) &&
2180 (chan->channel != ah->ah_curchan->channel) && 2152 (chan->channel != ah->ah_curchan->channel) &&
2181 ((chan->channelFlags & CHANNEL_ALL) == 2153 ((chan->channelFlags & CHANNEL_ALL) ==
@@ -2253,7 +2225,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2253 | AR_STA_ID1_RTS_USE_DEF 2225 | AR_STA_ID1_RTS_USE_DEF
2254 | (ah->ah_config. 2226 | (ah->ah_config.
2255 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2256 | ahp->ah_staId1Defaults); 2228 | ah->ah_staId1Defaults);
2257 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2229 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2258 2230
2259 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
@@ -2280,7 +2252,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2280 for (i = 0; i < AR_NUM_DCU; i++) 2252 for (i = 0; i < AR_NUM_DCU; i++)
2281 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2282 2254
2283 ahp->ah_intrTxqs = 0; 2255 ah->ah_intrTxqs = 0;
2284 for (i = 0; i < ah->ah_caps.total_queues; i++) 2256 for (i = 0; i < ah->ah_caps.total_queues; i++)
2285 ath9k_hw_resettxqueue(ah, i); 2257 ath9k_hw_resettxqueue(ah, i);
2286 2258
@@ -2300,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2300 2272
2301 REG_WRITE(ah, AR_OBS, 8); 2273 REG_WRITE(ah, AR_OBS, 8);
2302 2274
2303 if (ahp->ah_intrMitigation) { 2275 if (ah->ah_intrMitigation) {
2304 2276
2305 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2306 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
@@ -2311,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2311 if (!ath9k_hw_init_cal(ah, chan)) 2283 if (!ath9k_hw_init_cal(ah, chan))
2312 return -EIO;; 2284 return -EIO;;
2313 2285
2314 rx_chainmask = ahp->ah_rxchainmask; 2286 rx_chainmask = ah->ah_rxchainmask;
2315 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2316 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2317 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -2345,7 +2317,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2345/* Key Cache Management */ 2317/* Key Cache Management */
2346/************************/ 2318/************************/
2347 2319
2348bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) 2320bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2349{ 2321{
2350 u32 keyType; 2322 u32 keyType;
2351 2323
@@ -2382,7 +2354,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2382 return true; 2354 return true;
2383} 2355}
2384 2356
2385bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) 2357bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2386{ 2358{
2387 u32 macHi, macLo; 2359 u32 macHi, macLo;
2388 2360
@@ -2410,7 +2382,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2410 return true; 2382 return true;
2411} 2383}
2412 2384
2413bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 2385bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2414 const struct ath9k_keyval *k, 2386 const struct ath9k_keyval *k,
2415 const u8 *mac, int xorKey) 2387 const u8 *mac, int xorKey)
2416{ 2388{
@@ -2420,7 +2392,6 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2420 u32 xorMask = xorKey ? 2392 u32 xorMask = xorKey ?
2421 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 2393 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2422 | ATH9K_KEY_XOR) : 0; 2394 | ATH9K_KEY_XOR) : 0;
2423 struct ath_hal_5416 *ahp = AH5416(ah);
2424 2395
2425 if (entry >= pCap->keycache_size) { 2396 if (entry >= pCap->keycache_size) {
2426 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2397 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
@@ -2491,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2491 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2492 (void) ath9k_hw_keysetmac(ah, entry, mac); 2463 (void) ath9k_hw_keysetmac(ah, entry, mac);
2493 2464
2494 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 2465 if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2495 u32 mic0, mic1, mic2, mic3, mic4; 2466 u32 mic0, mic1, mic2, mic3, mic4;
2496 2467
2497 mic0 = get_unaligned_le32(k->kv_mic + 0); 2468 mic0 = get_unaligned_le32(k->kv_mic + 0);
@@ -2541,7 +2512,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2541 return true; 2512 return true;
2542} 2513}
2543 2514
2544bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2545{ 2516{
2546 if (entry < ah->ah_caps.keycache_size) { 2517 if (entry < ah->ah_caps.keycache_size) {
2547 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
@@ -2555,7 +2526,7 @@ bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2555/* Power Management (Chipset) */ 2526/* Power Management (Chipset) */
2556/******************************/ 2527/******************************/
2557 2528
2558static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) 2529static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2559{ 2530{
2560 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2531 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2561 if (setChip) { 2532 if (setChip) {
@@ -2569,7 +2540,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2569 } 2540 }
2570} 2541}
2571 2542
2572static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) 2543static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2573{ 2544{
2574 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2575 if (setChip) { 2546 if (setChip) {
@@ -2585,8 +2556,7 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2585 } 2556 }
2586} 2557}
2587 2558
2588static bool ath9k_hw_set_power_awake(struct ath_hal *ah, 2559static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2589 int setChip)
2590{ 2560{
2591 u32 val; 2561 u32 val;
2592 int i; 2562 int i;
@@ -2627,17 +2597,15 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2627 return true; 2597 return true;
2628} 2598}
2629 2599
2630bool ath9k_hw_setpower(struct ath_hal *ah, 2600bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2631 enum ath9k_power_mode mode)
2632{ 2601{
2633 struct ath_hal_5416 *ahp = AH5416(ah); 2602 int status = true, setChip = true;
2634 static const char *modes[] = { 2603 static const char *modes[] = {
2635 "AWAKE", 2604 "AWAKE",
2636 "FULL-SLEEP", 2605 "FULL-SLEEP",
2637 "NETWORK SLEEP", 2606 "NETWORK SLEEP",
2638 "UNDEFINED" 2607 "UNDEFINED"
2639 }; 2608 };
2640 int status = true, setChip = true;
2641 2609
2642 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2643 modes[ah->ah_power_mode], modes[mode], 2611 modes[ah->ah_power_mode], modes[mode],
@@ -2649,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2649 break; 2617 break;
2650 case ATH9K_PM_FULL_SLEEP: 2618 case ATH9K_PM_FULL_SLEEP:
2651 ath9k_set_power_sleep(ah, setChip); 2619 ath9k_set_power_sleep(ah, setChip);
2652 ahp->ah_chipFullSleep = true; 2620 ah->ah_chipFullSleep = true;
2653 break; 2621 break;
2654 case ATH9K_PM_NETWORK_SLEEP: 2622 case ATH9K_PM_NETWORK_SLEEP:
2655 ath9k_set_power_network_sleep(ah, setChip); 2623 ath9k_set_power_network_sleep(ah, setChip);
@@ -2664,9 +2632,8 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2664 return status; 2632 return status;
2665} 2633}
2666 2634
2667void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 2635void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2668{ 2636{
2669 struct ath_hal_5416 *ahp = AH5416(ah);
2670 u8 i; 2637 u8 i;
2671 2638
2672 if (ah->ah_isPciExpress != true) 2639 if (ah->ah_isPciExpress != true)
@@ -2679,9 +2646,9 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2679 return; 2646 return;
2680 2647
2681 if (AR_SREV_9280_20_OR_LATER(ah)) { 2648 if (AR_SREV_9280_20_OR_LATER(ah)) {
2682 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { 2649 for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) {
2683 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), 2650 REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0),
2684 INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); 2651 INI_RA(&ah->ah_iniPcieSerdes, i, 1));
2685 } 2652 }
2686 udelay(1000); 2653 udelay(1000);
2687 } else if (AR_SREV_9280(ah) && 2654 } else if (AR_SREV_9280(ah) &&
@@ -2730,14 +2697,13 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2730 else 2697 else
2731 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 2698 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2732 } 2699 }
2733
2734} 2700}
2735 2701
2736/**********************/ 2702/**********************/
2737/* Interrupt Handling */ 2703/* Interrupt Handling */
2738/**********************/ 2704/**********************/
2739 2705
2740bool ath9k_hw_intrpend(struct ath_hal *ah) 2706bool ath9k_hw_intrpend(struct ath_hw *ah)
2741{ 2707{
2742 u32 host_isr; 2708 u32 host_isr;
2743 2709
@@ -2756,14 +2722,13 @@ bool ath9k_hw_intrpend(struct ath_hal *ah)
2756 return false; 2722 return false;
2757} 2723}
2758 2724
2759bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) 2725bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2760{ 2726{
2761 u32 isr = 0; 2727 u32 isr = 0;
2762 u32 mask2 = 0; 2728 u32 mask2 = 0;
2763 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2729 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2764 u32 sync_cause = 0; 2730 u32 sync_cause = 0;
2765 bool fatal_int = false; 2731 bool fatal_int = false;
2766 struct ath_hal_5416 *ahp = AH5416(ah);
2767 2732
2768 if (!AR_SREV_9100(ah)) { 2733 if (!AR_SREV_9100(ah)) {
2769 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2734 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -2811,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2811 2776
2812 *masked = isr & ATH9K_INT_COMMON; 2777 *masked = isr & ATH9K_INT_COMMON;
2813 2778
2814 if (ahp->ah_intrMitigation) { 2779 if (ah->ah_intrMitigation) {
2815 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2780 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2816 *masked |= ATH9K_INT_RX; 2781 *masked |= ATH9K_INT_RX;
2817 } 2782 }
@@ -2826,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2826 *masked |= ATH9K_INT_TX; 2791 *masked |= ATH9K_INT_TX;
2827 2792
2828 s0_s = REG_READ(ah, AR_ISR_S0_S); 2793 s0_s = REG_READ(ah, AR_ISR_S0_S);
2829 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2794 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2830 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2795 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2831 2796
2832 s1_s = REG_READ(ah, AR_ISR_S1_S); 2797 s1_s = REG_READ(ah, AR_ISR_S1_S);
2833 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2798 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2834 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2799 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2835 } 2800 }
2836 2801
2837 if (isr & AR_ISR_RXORN) { 2802 if (isr & AR_ISR_RXORN) {
@@ -2888,15 +2853,14 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2888 return true; 2853 return true;
2889} 2854}
2890 2855
2891enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) 2856enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2892{ 2857{
2893 return AH5416(ah)->ah_maskReg; 2858 return ah->ah_maskReg;
2894} 2859}
2895 2860
2896enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) 2861enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2897{ 2862{
2898 struct ath_hal_5416 *ahp = AH5416(ah); 2863 u32 omask = ah->ah_maskReg;
2899 u32 omask = ahp->ah_maskReg;
2900 u32 mask, mask2; 2864 u32 mask, mask2;
2901 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2865 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2902 2866
@@ -2919,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2919 mask2 = 0; 2883 mask2 = 0;
2920 2884
2921 if (ints & ATH9K_INT_TX) { 2885 if (ints & ATH9K_INT_TX) {
2922 if (ahp->ah_txOkInterruptMask) 2886 if (ah->ah_txOkInterruptMask)
2923 mask |= AR_IMR_TXOK; 2887 mask |= AR_IMR_TXOK;
2924 if (ahp->ah_txDescInterruptMask) 2888 if (ah->ah_txDescInterruptMask)
2925 mask |= AR_IMR_TXDESC; 2889 mask |= AR_IMR_TXDESC;
2926 if (ahp->ah_txErrInterruptMask) 2890 if (ah->ah_txErrInterruptMask)
2927 mask |= AR_IMR_TXERR; 2891 mask |= AR_IMR_TXERR;
2928 if (ahp->ah_txEolInterruptMask) 2892 if (ah->ah_txEolInterruptMask)
2929 mask |= AR_IMR_TXEOL; 2893 mask |= AR_IMR_TXEOL;
2930 } 2894 }
2931 if (ints & ATH9K_INT_RX) { 2895 if (ints & ATH9K_INT_RX) {
2932 mask |= AR_IMR_RXERR; 2896 mask |= AR_IMR_RXERR;
2933 if (ahp->ah_intrMitigation) 2897 if (ah->ah_intrMitigation)
2934 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2935 else 2899 else
2936 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2900 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -2968,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2968 AR_IMR_S2_TSFOOR | 2932 AR_IMR_S2_TSFOOR |
2969 AR_IMR_S2_GTT | AR_IMR_S2_CST); 2933 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2970 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 2934 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2971 ahp->ah_maskReg = ints; 2935 ah->ah_maskReg = ints;
2972 2936
2973 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2937 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2974 if (ints & ATH9K_INT_TIM_TIMER) 2938 if (ints & ATH9K_INT_TIM_TIMER)
@@ -3002,12 +2966,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3002/* Beacon Handling */ 2966/* Beacon Handling */
3003/*******************/ 2967/*******************/
3004 2968
3005void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) 2969void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3006{ 2970{
3007 struct ath_hal_5416 *ahp = AH5416(ah);
3008 int flags = 0; 2971 int flags = 0;
3009 2972
3010 ahp->ah_beaconInterval = beacon_period; 2973 ah->ah_beaconInterval = beacon_period;
3011 2974
3012 switch (ah->ah_opmode) { 2975 switch (ah->ah_opmode) {
3013 case NL80211_IFTYPE_STATION: 2976 case NL80211_IFTYPE_STATION:
@@ -3022,7 +2985,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3022 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2985 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3023 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 2986 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3024 TU_TO_USEC(next_beacon + 2987 TU_TO_USEC(next_beacon +
3025 (ahp->ah_atimWindow ? ahp-> 2988 (ah->ah_atimWindow ? ah->
3026 ah_atimWindow : 1))); 2989 ah_atimWindow : 1)));
3027 flags |= AR_NDP_TIMER_EN; 2990 flags |= AR_NDP_TIMER_EN;
3028 case NL80211_IFTYPE_AP: 2991 case NL80211_IFTYPE_AP:
@@ -3060,7 +3023,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3060 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3023 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3061} 3024}
3062 3025
3063void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3026void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3064 const struct ath9k_beacon_state *bs) 3027 const struct ath9k_beacon_state *bs)
3065{ 3028{
3066 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
@@ -3124,9 +3087,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3124/* HW Capabilities */ 3087/* HW Capabilities */
3125/*******************/ 3088/*******************/
3126 3089
3127bool ath9k_hw_fill_cap_info(struct ath_hal *ah) 3090bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3128{ 3091{
3129 struct ath_hal_5416 *ahp = AH5416(ah);
3130 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3092 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3131 u16 capField = 0, eeval; 3093 u16 capField = 0, eeval;
3132 3094
@@ -3195,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3195 } 3157 }
3196 3158
3197 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3159 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3198 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3160 ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3199 3161
3200 pCap->low_2ghz_chan = 2312; 3162 pCap->low_2ghz_chan = 2312;
3201 pCap->high_2ghz_chan = 2732; 3163 pCap->high_2ghz_chan = 2732;
@@ -3317,10 +3279,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3317 return true; 3279 return true;
3318} 3280}
3319 3281
3320bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3282bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3321 u32 capability, u32 *result) 3283 u32 capability, u32 *result)
3322{ 3284{
3323 struct ath_hal_5416 *ahp = AH5416(ah);
3324 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3285 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3325 3286
3326 switch (type) { 3287 switch (type) {
@@ -3341,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3341 case 0: 3302 case 0:
3342 return true; 3303 return true;
3343 case 1: 3304 case 1:
3344 return (ahp->ah_staId1Defaults & 3305 return (ah->ah_staId1Defaults &
3345 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3306 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3346 false; 3307 false;
3347 } 3308 }
3348 case ATH9K_CAP_TKIP_SPLIT: 3309 case ATH9K_CAP_TKIP_SPLIT:
3349 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 3310 return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3350 false : true; 3311 false : true;
3351 case ATH9K_CAP_WME_TKIPMIC: 3312 case ATH9K_CAP_WME_TKIPMIC:
3352 return 0; 3313 return 0;
3353 case ATH9K_CAP_PHYCOUNTERS: 3314 case ATH9K_CAP_PHYCOUNTERS:
3354 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; 3315 return ah->ah_hasHwPhyCounters ? 0 : -ENXIO;
3355 case ATH9K_CAP_DIVERSITY: 3316 case ATH9K_CAP_DIVERSITY:
3356 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3317 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3357 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3318 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
@@ -3366,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3366 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3327 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3367 return false; 3328 return false;
3368 } else { 3329 } else {
3369 return (ahp->ah_staId1Defaults & 3330 return (ah->ah_staId1Defaults &
3370 AR_STA_ID1_MCAST_KSRCH) ? true : 3331 AR_STA_ID1_MCAST_KSRCH) ? true :
3371 false; 3332 false;
3372 } 3333 }
3373 } 3334 }
3374 return false; 3335 return false;
3375 case ATH9K_CAP_TSF_ADJUST: 3336 case ATH9K_CAP_TSF_ADJUST:
3376 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 3337 return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3377 true : false; 3338 true : false;
3378 case ATH9K_CAP_RFSILENT: 3339 case ATH9K_CAP_RFSILENT:
3379 if (capability == 3) 3340 if (capability == 3)
@@ -3404,19 +3365,18 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3404 } 3365 }
3405} 3366}
3406 3367
3407bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3368bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3408 u32 capability, u32 setting, int *status) 3369 u32 capability, u32 setting, int *status)
3409{ 3370{
3410 struct ath_hal_5416 *ahp = AH5416(ah);
3411 u32 v; 3371 u32 v;
3412 3372
3413 switch (type) { 3373 switch (type) {
3414 case ATH9K_CAP_TKIP_MIC: 3374 case ATH9K_CAP_TKIP_MIC:
3415 if (setting) 3375 if (setting)
3416 ahp->ah_staId1Defaults |= 3376 ah->ah_staId1Defaults |=
3417 AR_STA_ID1_CRPT_MIC_ENABLE; 3377 AR_STA_ID1_CRPT_MIC_ENABLE;
3418 else 3378 else
3419 ahp->ah_staId1Defaults &= 3379 ah->ah_staId1Defaults &=
3420 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3380 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3421 return true; 3381 return true;
3422 case ATH9K_CAP_DIVERSITY: 3382 case ATH9K_CAP_DIVERSITY:
@@ -3429,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3429 return true; 3389 return true;
3430 case ATH9K_CAP_MCAST_KEYSRCH: 3390 case ATH9K_CAP_MCAST_KEYSRCH:
3431 if (setting) 3391 if (setting)
3432 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 3392 ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3433 else 3393 else
3434 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3394 ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3435 return true; 3395 return true;
3436 case ATH9K_CAP_TSF_ADJUST: 3396 case ATH9K_CAP_TSF_ADJUST:
3437 if (setting) 3397 if (setting)
3438 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3398 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3439 else 3399 else
3440 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3400 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3441 return true; 3401 return true;
3442 default: 3402 default:
3443 return false; 3403 return false;
@@ -3448,7 +3408,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3448/* GPIO / RFKILL / Antennae */ 3408/* GPIO / RFKILL / Antennae */
3449/****************************/ 3409/****************************/
3450 3410
3451static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, 3411static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3452 u32 gpio, u32 type) 3412 u32 gpio, u32 type)
3453{ 3413{
3454 int addr; 3414 int addr;
@@ -3476,7 +3436,7 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3476 } 3436 }
3477} 3437}
3478 3438
3479void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) 3439void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3480{ 3440{
3481 u32 gpio_shift; 3441 u32 gpio_shift;
3482 3442
@@ -3490,7 +3450,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3490 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3450 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3491} 3451}
3492 3452
3493u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) 3453u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3494{ 3454{
3495#define MS_REG_READ(x, y) \ 3455#define MS_REG_READ(x, y) \
3496 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3456 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
@@ -3506,7 +3466,7 @@ u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3506 return MS_REG_READ(AR, gpio) != 0; 3466 return MS_REG_READ(AR, gpio) != 0;
3507} 3467}
3508 3468
3509void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 3469void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3510 u32 ah_signal_type) 3470 u32 ah_signal_type)
3511{ 3471{
3512 u32 gpio_shift; 3472 u32 gpio_shift;
@@ -3521,14 +3481,14 @@ void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3521 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3481 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3522} 3482}
3523 3483
3524void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) 3484void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3525{ 3485{
3526 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3486 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3527 AR_GPIO_BIT(gpio)); 3487 AR_GPIO_BIT(gpio));
3528} 3488}
3529 3489
3530#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3490#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3531void ath9k_enable_rfkill(struct ath_hal *ah) 3491void ath9k_enable_rfkill(struct ath_hw *ah)
3532{ 3492{
3533 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3493 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3534 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 3494 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
@@ -3541,24 +3501,23 @@ void ath9k_enable_rfkill(struct ath_hal *ah)
3541} 3501}
3542#endif 3502#endif
3543 3503
3544u32 ath9k_hw_getdefantenna(struct ath_hal *ah) 3504u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3545{ 3505{
3546 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3506 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3547} 3507}
3548 3508
3549void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) 3509void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3550{ 3510{
3551 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3511 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3552} 3512}
3553 3513
3554bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 3514bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3555 enum ath9k_ant_setting settings, 3515 enum ath9k_ant_setting settings,
3556 struct ath9k_channel *chan, 3516 struct ath9k_channel *chan,
3557 u8 *tx_chainmask, 3517 u8 *tx_chainmask,
3558 u8 *rx_chainmask, 3518 u8 *rx_chainmask,
3559 u8 *antenna_cfgd) 3519 u8 *antenna_cfgd)
3560{ 3520{
3561 struct ath_hal_5416 *ahp = AH5416(ah);
3562 static u8 tx_chainmask_cfg, rx_chainmask_cfg; 3521 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3563 3522
3564 if (AR_SREV_9280(ah)) { 3523 if (AR_SREV_9280(ah)) {
@@ -3591,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3591 break; 3550 break;
3592 } 3551 }
3593 } else { 3552 } else {
3594 ahp->ah_diversityControl = settings; 3553 ah->ah_diversityControl = settings;
3595 } 3554 }
3596 3555
3597 return true; 3556 return true;
@@ -3601,7 +3560,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3601/* General Operation */ 3560/* General Operation */
3602/*********************/ 3561/*********************/
3603 3562
3604u32 ath9k_hw_getrxfilter(struct ath_hal *ah) 3563u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3605{ 3564{
3606 u32 bits = REG_READ(ah, AR_RX_FILTER); 3565 u32 bits = REG_READ(ah, AR_RX_FILTER);
3607 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3566 u32 phybits = REG_READ(ah, AR_PHY_ERR);
@@ -3614,7 +3573,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3614 return bits; 3573 return bits;
3615} 3574}
3616 3575
3617void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) 3576void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3618{ 3577{
3619 u32 phybits; 3578 u32 phybits;
3620 3579
@@ -3634,12 +3593,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3634 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3593 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3635} 3594}
3636 3595
3637bool ath9k_hw_phy_disable(struct ath_hal *ah) 3596bool ath9k_hw_phy_disable(struct ath_hw *ah)
3638{ 3597{
3639 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3598 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3640} 3599}
3641 3600
3642bool ath9k_hw_disable(struct ath_hal *ah) 3601bool ath9k_hw_disable(struct ath_hw *ah)
3643{ 3602{
3644 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3603 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3645 return false; 3604 return false;
@@ -3647,7 +3606,7 @@ bool ath9k_hw_disable(struct ath_hal *ah)
3647 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3606 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3648} 3607}
3649 3608
3650bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) 3609bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3651{ 3610{
3652 struct ath9k_channel *chan = ah->ah_curchan; 3611 struct ath9k_channel *chan = ah->ah_curchan;
3653 struct ieee80211_channel *channel = chan->chan; 3612 struct ieee80211_channel *channel = chan->chan;
@@ -3665,17 +3624,17 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3665 return true; 3624 return true;
3666} 3625}
3667 3626
3668void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) 3627void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3669{ 3628{
3670 memcpy(ah->macaddr, mac, ETH_ALEN); 3629 memcpy(ah->macaddr, mac, ETH_ALEN);
3671} 3630}
3672 3631
3673void ath9k_hw_setopmode(struct ath_hal *ah) 3632void ath9k_hw_setopmode(struct ath_hw *ah)
3674{ 3633{
3675 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 3634 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3676} 3635}
3677 3636
3678void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) 3637void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3679{ 3638{
3680 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3639 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3681 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3640 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
@@ -3694,7 +3653,7 @@ void ath9k_hw_write_associd(struct ath_softc *sc)
3694 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3653 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3695} 3654}
3696 3655
3697u64 ath9k_hw_gettsf64(struct ath_hal *ah) 3656u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3698{ 3657{
3699 u64 tsf; 3658 u64 tsf;
3700 3659
@@ -3704,14 +3663,14 @@ u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3704 return tsf; 3663 return tsf;
3705} 3664}
3706 3665
3707void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64) 3666void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3708{ 3667{
3709 REG_WRITE(ah, AR_TSF_L32, 0x00000000); 3668 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3710 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3669 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3711 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3670 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3712} 3671}
3713 3672
3714void ath9k_hw_reset_tsf(struct ath_hal *ah) 3673void ath9k_hw_reset_tsf(struct ath_hw *ah)
3715{ 3674{
3716 int count; 3675 int count;
3717 3676
@@ -3728,34 +3687,30 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
3728 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3687 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3729} 3688}
3730 3689
3731bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) 3690bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3732{ 3691{
3733 struct ath_hal_5416 *ahp = AH5416(ah);
3734
3735 if (setting) 3692 if (setting)
3736 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3693 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3737 else 3694 else
3738 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3695 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3739 3696
3740 return true; 3697 return true;
3741} 3698}
3742 3699
3743bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) 3700bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3744{ 3701{
3745 struct ath_hal_5416 *ahp = AH5416(ah);
3746
3747 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3702 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3748 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3703 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3749 ahp->ah_slottime = (u32) -1; 3704 ah->ah_slottime = (u32) -1;
3750 return false; 3705 return false;
3751 } else { 3706 } else {
3752 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3707 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3753 ahp->ah_slottime = us; 3708 ah->ah_slottime = us;
3754 return true; 3709 return true;
3755 } 3710 }
3756} 3711}
3757 3712
3758void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) 3713void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3759{ 3714{
3760 u32 macmode; 3715 u32 macmode;
3761 3716
@@ -3772,7 +3727,7 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3772/* Bluetooth Coexistence */ 3727/* Bluetooth Coexistence */
3773/***************************/ 3728/***************************/
3774 3729
3775void ath9k_hw_btcoex_enable(struct ath_hal *ah) 3730void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3776{ 3731{
3777 /* connect bt_active to baseband */ 3732 /* connect bt_active to baseband */
3778 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3733 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 15:46:29 -0500