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authorSujith <Sujith.Manoharan@atheros.com>2008-11-17 22:37:53 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-11-26 09:47:30 -0500
commite63835b0f4d8545942fd41b3ca32bbf71bd73e4b (patch)
tree38eab8819cf8d3cc7aa98ee2cfb4e7df7e8eca3b /drivers/net/wireless/ath9k/hw.c
parenta8efee4f4740c61fccaf73608df282c4ee24ae86 (diff)
ath9k: Remove ath9k_rate_table
Maintaining two sets of rate tables is redundant, remove one and use struct ath_rate_table exclusively. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath9k/hw.c190
1 files changed, 3 insertions, 187 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 82c2a4259ce4..a26867c56a82 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -142,14 +142,14 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
142} 142}
143 143
144u16 ath9k_hw_computetxtime(struct ath_hal *ah, 144u16 ath9k_hw_computetxtime(struct ath_hal *ah,
145 const struct ath9k_rate_table *rates, 145 struct ath_rate_table *rates,
146 u32 frameLen, u16 rateix, 146 u32 frameLen, u16 rateix,
147 bool shortPreamble) 147 bool shortPreamble)
148{ 148{
149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
150 u32 kbps; 150 u32 kbps;
151 151
152 kbps = rates->info[rateix].rateKbps; 152 kbps = rates->info[rateix].ratekbps;
153 153
154 if (kbps == 0) 154 if (kbps == 0)
155 return 0; 155 return 0;
@@ -157,7 +157,7 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
157 switch (rates->info[rateix].phy) { 157 switch (rates->info[rateix].phy) {
158 case PHY_CCK: 158 case PHY_CCK:
159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
160 if (shortPreamble && rates->info[rateix].shortPreamble) 160 if (shortPreamble && rates->info[rateix].short_preamble)
161 phyTime >>= 1; 161 phyTime >>= 1;
162 numBits = frameLen << 3; 162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
@@ -3190,190 +3190,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3190 3190
3191} 3191}
3192 3192
3193/***************/
3194/* Rate tables */
3195/***************/
3196
3197static struct ath9k_rate_table ar5416_11a_table = {
3198 8,
3199 {0},
3200 {
3201 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3202 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3203 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3204 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3205 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3206 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3207 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3208 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
3209 },
3210};
3211
3212static struct ath9k_rate_table ar5416_11b_table = {
3213 4,
3214 {0},
3215 {
3216 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3217 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3218 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
3219 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
3220 },
3221};
3222
3223static struct ath9k_rate_table ar5416_11g_table = {
3224 12,
3225 {0},
3226 {
3227 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3228 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3229 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
3230 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
3231
3232 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
3233 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3234 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3235 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3236 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3237 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3238 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3239 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
3240 },
3241};
3242
3243static struct ath9k_rate_table ar5416_11ng_table = {
3244 28,
3245 {0},
3246 {
3247 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3248 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3249 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
3250 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
3251
3252 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
3253 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3254 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3255 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3256 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3257 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3258 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3259 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
3260 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
3261 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
3262 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
3263 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
3264 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
3265 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
3266 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
3267 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
3268 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
3269 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
3270 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
3271 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
3272 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
3273 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
3274 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
3275 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
3276 },
3277};
3278
3279static struct ath9k_rate_table ar5416_11na_table = {
3280 24,
3281 {0},
3282 {
3283 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3284 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3285 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3286 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3287 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3288 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3289 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3290 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
3291 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
3292 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
3293 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
3294 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
3295 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
3296 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
3297 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
3298 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
3299 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
3300 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
3301 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
3302 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
3303 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
3304 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
3305 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
3306 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
3307 },
3308};
3309
3310static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
3311 struct ath9k_rate_table *rt)
3312{
3313 int i;
3314
3315 if (rt->rateCodeToIndex[0] != 0)
3316 return;
3317
3318 for (i = 0; i < 256; i++)
3319 rt->rateCodeToIndex[i] = (u8) -1;
3320
3321 for (i = 0; i < rt->rateCount; i++) {
3322 u8 code = rt->info[i].rateCode;
3323 u8 cix = rt->info[i].controlRate;
3324
3325 rt->rateCodeToIndex[code] = i;
3326 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
3327
3328 rt->info[i].lpAckDuration =
3329 ath9k_hw_computetxtime(ah, rt,
3330 WLAN_CTRL_FRAME_SIZE,
3331 cix,
3332 false);
3333 rt->info[i].spAckDuration =
3334 ath9k_hw_computetxtime(ah, rt,
3335 WLAN_CTRL_FRAME_SIZE,
3336 cix,
3337 true);
3338 }
3339}
3340
3341const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
3342 u32 mode)
3343{
3344 struct ath9k_rate_table *rt;
3345
3346 switch (mode) {
3347 case ATH9K_MODE_11A:
3348 rt = &ar5416_11a_table;
3349 break;
3350 case ATH9K_MODE_11B:
3351 rt = &ar5416_11b_table;
3352 break;
3353 case ATH9K_MODE_11G:
3354 rt = &ar5416_11g_table;
3355 break;
3356 case ATH9K_MODE_11NG_HT20:
3357 case ATH9K_MODE_11NG_HT40PLUS:
3358 case ATH9K_MODE_11NG_HT40MINUS:
3359 rt = &ar5416_11ng_table;
3360 break;
3361 case ATH9K_MODE_11NA_HT20:
3362 case ATH9K_MODE_11NA_HT40PLUS:
3363 case ATH9K_MODE_11NA_HT40MINUS:
3364 rt = &ar5416_11na_table;
3365 break;
3366 default:
3367 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
3368 __func__, mode);
3369 return NULL;
3370 }
3371
3372 ath9k_hw_setup_rate_table(ah, rt);
3373
3374 return rt;
3375}
3376
3377/*******************/ 3193/*******************/
3378/* HW Capabilities */ 3194/* HW Capabilities */
3379/*******************/ 3195/*******************/
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 23:25:38 -0500