diff options
author | Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2008-09-10 09:20:17 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-09-15 16:48:19 -0400 |
commit | 500c064d3a5f9c8aa604ef63a1346ab70eed443a (patch) | |
tree | d7345fa9f894bcbc21e80e886cc3f32589469bad /drivers/net/wireless/ath9k/hw.c | |
parent | 8feceb67929bd23bfca58d5f49df93d7fc315bb1 (diff) |
ath9k: Add RF kill support
RF kill support is enabled when CONFIG_RFKILL
is set.
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.c')
-rw-r--r-- | drivers/net/wireless/ath9k/hw.c | 70 |
1 files changed, 40 insertions, 30 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 4ccbbc07cf1e..0251e59f2f84 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c | |||
@@ -2821,7 +2821,38 @@ void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) | |||
2821 | AR_GPIO_BIT(gpio)); | 2821 | AR_GPIO_BIT(gpio)); |
2822 | } | 2822 | } |
2823 | 2823 | ||
2824 | static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) | 2824 | /* |
2825 | * Configure GPIO Input lines | ||
2826 | */ | ||
2827 | void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) | ||
2828 | { | ||
2829 | u32 gpio_shift; | ||
2830 | |||
2831 | ASSERT(gpio < ah->ah_caps.num_gpio_pins); | ||
2832 | |||
2833 | gpio_shift = gpio << 1; | ||
2834 | |||
2835 | REG_RMW(ah, | ||
2836 | AR_GPIO_OE_OUT, | ||
2837 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | ||
2838 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | ||
2839 | } | ||
2840 | |||
2841 | #ifdef CONFIG_RFKILL | ||
2842 | static void ath9k_enable_rfkill(struct ath_hal *ah) | ||
2843 | { | ||
2844 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
2845 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | ||
2846 | |||
2847 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, | ||
2848 | AR_GPIO_INPUT_MUX2_RFSILENT); | ||
2849 | |||
2850 | ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); | ||
2851 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | ||
2852 | } | ||
2853 | #endif | ||
2854 | |||
2855 | u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) | ||
2825 | { | 2856 | { |
2826 | if (gpio >= ah->ah_caps.num_gpio_pins) | 2857 | if (gpio >= ah->ah_caps.num_gpio_pins) |
2827 | return 0xffffffff; | 2858 | return 0xffffffff; |
@@ -3034,17 +3065,17 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah) | |||
3034 | 3065 | ||
3035 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; | 3066 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
3036 | 3067 | ||
3068 | #ifdef CONFIG_RFKILL | ||
3037 | ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT); | 3069 | ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT); |
3038 | if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { | 3070 | if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { |
3039 | ahp->ah_gpioSelect = | 3071 | ah->ah_rfkill_gpio = |
3040 | MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); | 3072 | MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); |
3041 | ahp->ah_polarity = | 3073 | ah->ah_rfkill_polarity = |
3042 | MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); | 3074 | MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); |
3043 | 3075 | ||
3044 | ath9k_hw_setcapability(ah, ATH9K_CAP_RFSILENT, 1, true, | ||
3045 | NULL); | ||
3046 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | 3076 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
3047 | } | 3077 | } |
3078 | #endif | ||
3048 | 3079 | ||
3049 | if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || | 3080 | if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || |
3050 | (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || | 3081 | (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || |
@@ -5961,6 +5992,10 @@ bool ath9k_hw_reset(struct ath_hal *ah, | |||
5961 | ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); | 5992 | ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); |
5962 | ath9k_hw_init_qos(ah); | 5993 | ath9k_hw_init_qos(ah); |
5963 | 5994 | ||
5995 | #ifdef CONFIG_RFKILL | ||
5996 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | ||
5997 | ath9k_enable_rfkill(ah); | ||
5998 | #endif | ||
5964 | ath9k_hw_init_user_settings(ah); | 5999 | ath9k_hw_init_user_settings(ah); |
5965 | 6000 | ||
5966 | REG_WRITE(ah, AR_STA_ID1, | 6001 | REG_WRITE(ah, AR_STA_ID1, |
@@ -6490,31 +6525,6 @@ ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) | |||
6490 | return true; | 6525 | return true; |
6491 | } | 6526 | } |
6492 | 6527 | ||
6493 | #ifdef CONFIG_ATH9K_RFKILL | ||
6494 | static void ath9k_enable_rfkill(struct ath_hal *ah) | ||
6495 | { | ||
6496 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
6497 | |||
6498 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
6499 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | ||
6500 | |||
6501 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, | ||
6502 | AR_GPIO_INPUT_MUX2_RFSILENT); | ||
6503 | |||
6504 | ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect); | ||
6505 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | ||
6506 | |||
6507 | if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) { | ||
6508 | |||
6509 | ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect, | ||
6510 | !ahp->ah_gpioBit); | ||
6511 | } else { | ||
6512 | ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect, | ||
6513 | ahp->ah_gpioBit); | ||
6514 | } | ||
6515 | } | ||
6516 | #endif | ||
6517 | |||
6518 | void | 6528 | void |
6519 | ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, | 6529 | ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, |
6520 | u16 assocId) | 6530 | u16 assocId) |