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authorSujith <Sujith.Manoharan@atheros.com>2009-03-30 05:58:25 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-04-22 16:54:30 -0400
commitd8baa9392666d1c50ef42e9f6fbbb0cf536327b9 (patch)
treea70f7ef031e128defc2bc46dedb3ce1f15432d2a /drivers/net/wireless/ath9k/hw.c
parent6ed6a05e5c8061cdcd69a418c90c5f11979ce650 (diff)
ath9k: Cleanup debug messages
Clean debug messages to use appropriate levels, remove useless messages, and trim the number of debug levels. Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath9k/hw.c101
1 files changed, 44 insertions, 57 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 22ef93f3d47c..169d8efa69dc 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -97,7 +97,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
97 udelay(AH_TIME_QUANTUM); 97 udelay(AH_TIME_QUANTUM);
98 } 98 }
99 99
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 100 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val); 102 timeout, reg, REG_READ(ah, reg), mask, val);
103 103
@@ -181,7 +181,7 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
181 } 181 }
182 break; 182 break;
183 default: 183 default:
184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 184 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
185 "Unknown phy %u (rate ix %u)\n", 185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix); 186 rates->info[rateix].phy, rateix);
187 txTime = 0; 187 txTime = 0;
@@ -306,7 +306,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
306 REG_WRITE(ah, addr, wrData); 306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr); 307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) { 308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 309 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
310 "address test failed " 310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData); 312 addr, wrData, rdData);
@@ -318,7 +318,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
318 REG_WRITE(ah, addr, wrData); 318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr); 319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) { 320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 321 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
322 "address test failed " 322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData); 324 addr, wrData, rdData);
@@ -453,8 +453,8 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
453 453
454 rfStatus = ath9k_hw_init_rf(ah, &ecode); 454 rfStatus = ath9k_hw_init_rf(ah, &ecode);
455 if (!rfStatus) { 455 if (!rfStatus) {
456 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 456 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
457 "RF setup failed, status %u\n", ecode); 457 "RF setup failed, status: %u\n", ecode);
458 return ecode; 458 return ecode;
459 } 459 }
460 460
@@ -478,10 +478,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
478 case AR_RAD2122_SREV_MAJOR: 478 case AR_RAD2122_SREV_MAJOR:
479 break; 479 break;
480 default: 480 default:
481 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 481 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
482 "5G Radio Chip Rev 0x%02X is not " 482 "Radio Chip Rev 0x%02X not supported\n",
483 "supported by this driver\n", 483 val & AR_RADIO_SREV_MAJOR);
484 ah->hw_version.analog5GhzRev);
485 return -EOPNOTSUPP; 484 return -EOPNOTSUPP;
486 } 485 }
487 486
@@ -503,12 +502,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
503 ah->macaddr[2 * i] = eeval >> 8; 502 ah->macaddr[2 * i] = eeval >> 8;
504 ah->macaddr[2 * i + 1] = eeval & 0xff; 503 ah->macaddr[2 * i + 1] = eeval & 0xff;
505 } 504 }
506 if (sum == 0 || sum == 0xffff * 3) { 505 if (sum == 0 || sum == 0xffff * 3)
507 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
508 "mac address read failed: %pM\n",
509 ah->macaddr);
510 return -EADDRNOTAVAIL; 506 return -EADDRNOTAVAIL;
511 }
512 507
513 return 0; 508 return 0;
514} 509}
@@ -565,11 +560,8 @@ static int ath9k_hw_post_attach(struct ath_hw *ah)
565{ 560{
566 int ecode; 561 int ecode;
567 562
568 if (!ath9k_hw_chip_test(ah)) { 563 if (!ath9k_hw_chip_test(ah))
569 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
570 "hardware self-test failed\n");
571 return -ENODEV; 564 return -ENODEV;
572 }
573 565
574 ecode = ath9k_hw_rf_claim(ah); 566 ecode = ath9k_hw_rf_claim(ah);
575 if (ecode != 0) 567 if (ecode != 0)
@@ -611,13 +603,13 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
611 ah->intr_mitigation = true; 603 ah->intr_mitigation = true;
612 604
613 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
614 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 606 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
615 ecode = -EIO; 607 ecode = -EIO;
616 goto bad; 608 goto bad;
617 } 609 }
618 610
619 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 611 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
620 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); 612 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
621 ecode = -EIO; 613 ecode = -EIO;
622 goto bad; 614 goto bad;
623 } 615 }
@@ -640,7 +632,7 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
640 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 632 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
641 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && 633 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
642 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 634 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
643 DPRINTF(sc, ATH_DBG_RESET, 635 DPRINTF(sc, ATH_DBG_FATAL,
644 "Mac Chip Rev 0x%02x.%x is not supported by " 636 "Mac Chip Rev 0x%02x.%x is not supported by "
645 "this driver\n", ah->hw_version.macVersion, 637 "this driver\n", ah->hw_version.macVersion,
646 ah->hw_version.macRev); 638 ah->hw_version.macRev);
@@ -680,10 +672,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
680 if (AR_SREV_9280_10_OR_LATER(ah)) 672 if (AR_SREV_9280_10_OR_LATER(ah))
681 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 673 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
682 674
683 DPRINTF(sc, ATH_DBG_RESET,
684 "This Mac Chip Rev 0x%02x.%x is \n",
685 ah->hw_version.macVersion, ah->hw_version.macRev);
686
687 if (AR_SREV_9285_12_OR_LATER(ah)) { 675 if (AR_SREV_9285_12_OR_LATER(ah)) {
688 676
689 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 677 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
@@ -875,8 +863,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
875 863
876 ecode = ath9k_hw_init_macaddr(ah); 864 ecode = ath9k_hw_init_macaddr(ah);
877 if (ecode != 0) { 865 if (ecode != 0) {
878 DPRINTF(sc, ATH_DBG_RESET, 866 DPRINTF(sc, ATH_DBG_FATAL,
879 "failed initializing mac address\n"); 867 "Failed to initialize MAC address\n");
880 goto bad; 868 goto bad;
881 } 869 }
882 870
@@ -1193,23 +1181,23 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1193 switch (ah->hw_version.devid) { 1181 switch (ah->hw_version.devid) {
1194 case AR9280_DEVID_PCI: 1182 case AR9280_DEVID_PCI:
1195 if (reg == 0x7894) { 1183 if (reg == 0x7894) {
1196 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1184 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1197 "ini VAL: %x EEPROM: %x\n", value, 1185 "ini VAL: %x EEPROM: %x\n", value,
1198 (pBase->version & 0xff)); 1186 (pBase->version & 0xff));
1199 1187
1200 if ((pBase->version & 0xff) > 0x0a) { 1188 if ((pBase->version & 0xff) > 0x0a) {
1201 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1189 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1202 "PWDCLKIND: %d\n", 1190 "PWDCLKIND: %d\n",
1203 pBase->pwdclkind); 1191 pBase->pwdclkind);
1204 value &= ~AR_AN_TOP2_PWDCLKIND; 1192 value &= ~AR_AN_TOP2_PWDCLKIND;
1205 value |= AR_AN_TOP2_PWDCLKIND & 1193 value |= AR_AN_TOP2_PWDCLKIND &
1206 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1194 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1207 } else { 1195 } else {
1208 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1196 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1209 "PWDCLKIND Earlier Rev\n"); 1197 "PWDCLKIND Earlier Rev\n");
1210 } 1198 }
1211 1199
1212 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1200 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1213 "final ini VAL: %x\n", value); 1201 "final ini VAL: %x\n", value);
1214 } 1202 }
1215 break; 1203 break;
@@ -1356,13 +1344,13 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1356 min((u32) MAX_RATE_POWER, 1344 min((u32) MAX_RATE_POWER,
1357 (u32) ah->regulatory.power_limit)); 1345 (u32) ah->regulatory.power_limit));
1358 if (status != 0) { 1346 if (status != 0) {
1359 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1347 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1360 "error init'ing transmit power\n"); 1348 "Error initializing transmit power\n");
1361 return -EIO; 1349 return -EIO;
1362 } 1350 }
1363 1351
1364 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1352 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1365 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1366 "ar5416SetRfRegs failed\n"); 1354 "ar5416SetRfRegs failed\n");
1367 return -EIO; 1355 return -EIO;
1368 } 1356 }
@@ -1668,7 +1656,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1668 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1656 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1669 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1657 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1670 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1658 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1671 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1659 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1672 "Could not kill baseband RX\n"); 1660 "Could not kill baseband RX\n");
1673 return false; 1661 return false;
1674 } 1662 }
@@ -1677,14 +1665,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1677 1665
1678 if (AR_SREV_9280_10_OR_LATER(ah)) { 1666 if (AR_SREV_9280_10_OR_LATER(ah)) {
1679 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 1667 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1680 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1668 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1681 "failed to set channel\n"); 1669 "Failed to set channel\n");
1682 return false; 1670 return false;
1683 } 1671 }
1684 } else { 1672 } else {
1685 if (!(ath9k_hw_set_channel(ah, chan))) { 1673 if (!(ath9k_hw_set_channel(ah, chan))) {
1686 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1674 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1687 "failed to set channel\n"); 1675 "Failed to set channel\n");
1688 return false; 1676 return false;
1689 } 1677 }
1690 } 1678 }
@@ -1696,7 +1684,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1696 min((u32) MAX_RATE_POWER, 1684 min((u32) MAX_RATE_POWER,
1697 (u32) ah->regulatory.power_limit)) != 0) { 1685 (u32) ah->regulatory.power_limit)) != 0) {
1698 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1686 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1699 "error init'ing transmit power\n"); 1687 "Error initializing transmit power\n");
1700 return false; 1688 return false;
1701 } 1689 }
1702 1690
@@ -2224,7 +2212,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2224 ath9k_hw_mark_phy_inactive(ah); 2212 ath9k_hw_mark_phy_inactive(ah);
2225 2213
2226 if (!ath9k_hw_chip_reset(ah, chan)) { 2214 if (!ath9k_hw_chip_reset(ah, chan)) {
2227 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n"); 2215 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2228 return -EINVAL; 2216 return -EINVAL;
2229 } 2217 }
2230 2218
@@ -2367,8 +2355,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2367 u32 keyType; 2355 u32 keyType;
2368 2356
2369 if (entry >= ah->caps.keycache_size) { 2357 if (entry >= ah->caps.keycache_size) {
2370 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2358 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2371 "entry %u out of range\n", entry); 2359 "keychache entry %u out of range\n", entry);
2372 return false; 2360 return false;
2373 } 2361 }
2374 2362
@@ -2404,8 +2392,8 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2404 u32 macHi, macLo; 2392 u32 macHi, macLo;
2405 2393
2406 if (entry >= ah->caps.keycache_size) { 2394 if (entry >= ah->caps.keycache_size) {
2407 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2395 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2408 "entry %u out of range\n", entry); 2396 "keychache entry %u out of range\n", entry);
2409 return false; 2397 return false;
2410 } 2398 }
2411 2399
@@ -2436,8 +2424,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2436 u32 keyType; 2424 u32 keyType;
2437 2425
2438 if (entry >= pCap->keycache_size) { 2426 if (entry >= pCap->keycache_size) {
2439 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2427 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2440 "entry %u out of range\n", entry); 2428 "keycache entry %u out of range\n", entry);
2441 return false; 2429 return false;
2442 } 2430 }
2443 2431
@@ -2447,7 +2435,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2447 break; 2435 break;
2448 case ATH9K_CIPHER_AES_CCM: 2436 case ATH9K_CIPHER_AES_CCM:
2449 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2437 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2450 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2438 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2451 "AES-CCM not supported by mac rev 0x%x\n", 2439 "AES-CCM not supported by mac rev 0x%x\n",
2452 ah->hw_version.macRev); 2440 ah->hw_version.macRev);
2453 return false; 2441 return false;
@@ -2458,14 +2446,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2458 keyType = AR_KEYTABLE_TYPE_TKIP; 2446 keyType = AR_KEYTABLE_TYPE_TKIP;
2459 if (ATH9K_IS_MIC_ENABLED(ah) 2447 if (ATH9K_IS_MIC_ENABLED(ah)
2460 && entry + 64 >= pCap->keycache_size) { 2448 && entry + 64 >= pCap->keycache_size) {
2461 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2449 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2462 "entry %u inappropriate for TKIP\n", entry); 2450 "entry %u inappropriate for TKIP\n", entry);
2463 return false; 2451 return false;
2464 } 2452 }
2465 break; 2453 break;
2466 case ATH9K_CIPHER_WEP: 2454 case ATH9K_CIPHER_WEP:
2467 if (k->kv_len < LEN_WEP40) { 2455 if (k->kv_len < LEN_WEP40) {
2468 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2456 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2469 "WEP key length %u too small\n", k->kv_len); 2457 "WEP key length %u too small\n", k->kv_len);
2470 return false; 2458 return false;
2471 } 2459 }
@@ -2480,7 +2468,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2480 keyType = AR_KEYTABLE_TYPE_CLR; 2468 keyType = AR_KEYTABLE_TYPE_CLR;
2481 break; 2469 break;
2482 default: 2470 default:
2483 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2471 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2484 "cipher %u not supported\n", k->kv_type); 2472 "cipher %u not supported\n", k->kv_type);
2485 return false; 2473 return false;
2486 } 2474 }
@@ -2698,7 +2686,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2698 AR_RTC_FORCE_WAKE_EN); 2686 AR_RTC_FORCE_WAKE_EN);
2699 } 2687 }
2700 if (i == 0) { 2688 if (i == 0) {
2701 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2689 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2702 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2690 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2703 return false; 2691 return false;
2704 } 2692 }
@@ -2719,9 +2707,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2719 "UNDEFINED" 2707 "UNDEFINED"
2720 }; 2708 };
2721 2709
2722 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2710 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2723 modes[ah->power_mode], modes[mode], 2711 modes[ah->power_mode], modes[mode]);
2724 setChip ? "set chip " : "");
2725 2712
2726 switch (mode) { 2713 switch (mode) {
2727 case ATH9K_PM_AWAKE: 2714 case ATH9K_PM_AWAKE:
@@ -2735,7 +2722,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2735 ath9k_set_power_network_sleep(ah, setChip); 2722 ath9k_set_power_network_sleep(ah, setChip);
2736 break; 2723 break;
2737 default: 2724 default:
2738 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2725 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2739 "Unknown power mode %u\n", mode); 2726 "Unknown power mode %u\n", mode);
2740 return false; 2727 return false;
2741 } 2728 }