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authorGabor Juhos <juhosg@openwrt.org>2009-03-06 03:08:51 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-03-16 18:09:31 -0400
commita8c96d3b225d4c9e6ff341923e3f76de401c75b2 (patch)
treee6056b9520e58fafc7db2de5152ead43e013a696 /drivers/net/wireless/ath9k/eeprom.c
parent978b53264235eef1d2d2e9fd16ae26b3471c0b57 (diff)
ath9k: cleanup AR5416 version checking macros
Currently we have two different versions of this macros. Because they would have to do the same thing, we should simplify and merge them. Changes-licensed-under: ISC Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index f935341bc5c4..5a5ab23a2ba2 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -640,7 +640,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
640 pPdGainBoundaries[i] = 640 pPdGainBoundaries[i] =
641 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 641 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
642 642
643 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { 643 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
644 minDelta = pPdGainBoundaries[0] - 23; 644 minDelta = pPdGainBoundaries[0] - 23;
645 pPdGainBoundaries[0] = 23; 645 pPdGainBoundaries[0] = 23;
646 } else { 646 } else {
@@ -755,7 +755,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
755 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); 755 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
756 756
757 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 757 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
758 if (AR_SREV_5416_V20_OR_LATER(ah) && 758 if (AR_SREV_5416_20_OR_LATER(ah) &&
759 (ah->rxchainmask == 5 || ah->txchainmask == 5) && 759 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
760 (i != 0)) { 760 (i != 0)) {
761 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 761 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
@@ -771,7 +771,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
771 &tMinCalPower, gainBoundaries, 771 &tMinCalPower, gainBoundaries,
772 pdadcValues, numXpdGain); 772 pdadcValues, numXpdGain);
773 773
774 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 774 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
775 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 775 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
776 SM(pdGainOverlap_t2, 776 SM(pdGainOverlap_t2,
777 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 777 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
@@ -1707,7 +1707,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1707 break; 1707 break;
1708 } 1708 }
1709 1709
1710 if (AR_SREV_5416_V20_OR_LATER(ah) && 1710 if (AR_SREV_5416_20_OR_LATER(ah) &&
1711 (ah->rxchainmask == 5 || ah->txchainmask == 5) 1711 (ah->rxchainmask == 5 || ah->txchainmask == 5)
1712 && (i != 0)) 1712 && (i != 0))
1713 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1713 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
@@ -1728,7 +1728,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1728 SM(pModal->iqCalQCh[i], 1728 SM(pModal->iqCalQCh[i],
1729 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1729 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1730 1730
1731 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 1731 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
1732 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { 1732 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1733 txRxAttenLocal = pModal->txRxAttenCh[i]; 1733 txRxAttenLocal = pModal->txRxAttenCh[i];
1734 if (AR_SREV_9280_10_OR_LATER(ah)) { 1734 if (AR_SREV_9280_10_OR_LATER(ah)) {
@@ -2094,7 +2094,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
2094 pPdGainBoundaries[i] = 2094 pPdGainBoundaries[i] =
2095 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2095 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2096 2096
2097 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { 2097 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2098 minDelta = pPdGainBoundaries[0] - 23; 2098 minDelta = pPdGainBoundaries[0] - 23;
2099 pPdGainBoundaries[0] = 23; 2099 pPdGainBoundaries[0] = 23;
2100 } else { 2100 } else {
@@ -2228,7 +2228,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2228 xpdGainValues[2]); 2228 xpdGainValues[2]);
2229 2229
2230 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2230 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2231 if (AR_SREV_5416_V20_OR_LATER(ah) && 2231 if (AR_SREV_5416_20_OR_LATER(ah) &&
2232 (ah->rxchainmask == 5 || ah->txchainmask == 5) && 2232 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2233 (i != 0)) { 2233 (i != 0)) {
2234 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 2234 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
@@ -2262,7 +2262,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2262 numXpdGain); 2262 numXpdGain);
2263 } 2263 }
2264 2264
2265 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 2265 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2266 if (OLC_FOR_AR9280_20_LATER) { 2266 if (OLC_FOR_AR9280_20_LATER) {
2267 REG_WRITE(ah, 2267 REG_WRITE(ah,
2268 AR_PHY_TPCRG5 + regChainOffset, 2268 AR_PHY_TPCRG5 + regChainOffset,