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authorDavid S. Miller <davem@davemloft.net>2009-02-15 02:06:44 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-15 02:06:44 -0500
commitac178ef0ae9eb44fd527d87aa9b6394e05f56e1f (patch)
tree5d6bd46ecf9ce989134d3c460e1ecf5dd1fceadc /drivers/net/wireless/ath9k/eeprom.c
parentf3a7c66b5ce0b75a9774a50b5dcce93e5ba28370 (diff)
parent6d08b9b9c6eb2414c4a037407dd121298a74fb36 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c2922
1 files changed, 1434 insertions, 1488 deletions
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 5038907e7432..c0359ad2bc7b 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -14,12 +14,9 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, 19static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
23 u32 reg, u32 mask, 20 u32 reg, u32 mask,
24 u32 shift, u32 val) 21 u32 shift, u32 val)
25{ 22{
@@ -30,7 +27,7 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
30 27
31 REG_WRITE(ah, reg, regVal); 28 REG_WRITE(ah, reg, regVal);
32 29
33 if (ah->ah_config.analog_shiftreg) 30 if (ah->config.analog_shiftreg)
34 udelay(100); 31 udelay(100);
35 32
36 return; 33 return;
@@ -91,212 +88,227 @@ static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
91 return false; 88 return false;
92} 89}
93 90
94static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data) 91static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
95{ 92{
96 struct ath_softc *sc = ah->ah_sc; 93 struct ath_softc *sc = ah->ah_sc;
97 94
98 return sc->bus_ops->eeprom_read(ah, off, data); 95 return sc->bus_ops->eeprom_read(ah, off, data);
99} 96}
100 97
101static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) 98static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
99 u8 *pVpdList, u16 numIntercepts,
100 u8 *pRetVpdList)
102{ 101{
103#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 102 u16 i, k;
104 struct ath_hal_5416 *ahp = AH5416(ah); 103 u8 currPwr = pwrMin;
105 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; 104 u16 idxL = 0, idxR = 0;
106 u16 *eep_data;
107 int addr, eep_start_loc = 0;
108
109 eep_start_loc = 64;
110 105
111 if (!ath9k_hw_use_flash(ah)) { 106 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
112 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 107 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
113 "Reading from EEPROM, not flash\n"); 108 numIntercepts, &(idxL),
109 &(idxR));
110 if (idxR < 1)
111 idxR = 1;
112 if (idxL == numIntercepts - 1)
113 idxL = (u16) (numIntercepts - 2);
114 if (pPwrList[idxL] == pPwrList[idxR])
115 k = pVpdList[idxL];
116 else
117 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
118 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
119 (pPwrList[idxR] - pPwrList[idxL]));
120 pRetVpdList[i] = (u8) k;
121 currPwr += 2;
114 } 122 }
115 123
116 eep_data = (u16 *)eep;
117
118 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
119 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
121 "Unable to read eeprom region \n");
122 return false;
123 }
124 eep_data++;
125 }
126 return true; 124 return true;
127#undef SIZE_EEPROM_4K
128} 125}
129 126
130static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) 127static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
128 struct ath9k_channel *chan,
129 struct cal_target_power_leg *powInfo,
130 u16 numChannels,
131 struct cal_target_power_leg *pNewPower,
132 u16 numRates, bool isExtTarget)
131{ 133{
132#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 134 struct chan_centers centers;
133 struct ath_hal_5416 *ahp = AH5416(ah); 135 u16 clo, chi;
134 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; 136 int i;
135 u16 *eep_data; 137 int matchIndex = -1, lowIndex = -1;
136 int addr, ar5416_eep_start_loc = 0x100; 138 u16 freq;
137 139
138 eep_data = (u16 *)eep; 140 ath9k_hw_get_channel_centers(ah, chan, &centers);
141 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
139 142
140 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 143 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
141 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 144 IS_CHAN_2GHZ(chan))) {
142 eep_data)) { 145 matchIndex = 0;
143 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 146 } else {
144 "Unable to read eeprom region\n"); 147 for (i = 0; (i < numChannels) &&
145 return false; 148 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
149 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
150 IS_CHAN_2GHZ(chan))) {
151 matchIndex = i;
152 break;
153 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
154 IS_CHAN_2GHZ(chan))) &&
155 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
156 IS_CHAN_2GHZ(chan)))) {
157 lowIndex = i - 1;
158 break;
159 }
146 } 160 }
147 eep_data++; 161 if ((matchIndex == -1) && (lowIndex == -1))
162 matchIndex = i - 1;
148 } 163 }
149 return true;
150#undef SIZE_EEPROM_DEF
151}
152 164
153static bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = { 165 if (matchIndex != -1) {
154 ath9k_hw_fill_def_eeprom, 166 *pNewPower = powInfo[matchIndex];
155 ath9k_hw_fill_4k_eeprom 167 } else {
156}; 168 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
157 169 IS_CHAN_2GHZ(chan));
158static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah) 170 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
159{ 171 IS_CHAN_2GHZ(chan));
160 struct ath_hal_5416 *ahp = AH5416(ah);
161 172
162 return ath9k_fill_eeprom[ahp->ah_eep_map](ah); 173 for (i = 0; i < numRates; i++) {
174 pNewPower->tPow2x[i] =
175 (u8)ath9k_hw_interpolate(freq, clo, chi,
176 powInfo[lowIndex].tPow2x[i],
177 powInfo[lowIndex + 1].tPow2x[i]);
178 }
179 }
163} 180}
164 181
165static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) 182static void ath9k_hw_get_target_powers(struct ath_hw *ah,
183 struct ath9k_channel *chan,
184 struct cal_target_power_ht *powInfo,
185 u16 numChannels,
186 struct cal_target_power_ht *pNewPower,
187 u16 numRates, bool isHt40Target)
166{ 188{
167 struct ath_hal_5416 *ahp = AH5416(ah); 189 struct chan_centers centers;
168 struct ar5416_eeprom_def *eep = 190 u16 clo, chi;
169 (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def; 191 int i;
170 u16 *eepdata, temp, magic, magic2; 192 int matchIndex = -1, lowIndex = -1;
171 u32 sum = 0, el; 193 u16 freq;
172 bool need_swap = false;
173 int i, addr, size;
174
175 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
176 &magic)) {
177 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
178 "Reading Magic # failed\n");
179 return false;
180 }
181
182 if (!ath9k_hw_use_flash(ah)) {
183 194
184 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 195 ath9k_hw_get_channel_centers(ah, chan, &centers);
185 "Read Magic = 0x%04X\n", magic); 196 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
186 197
187 if (magic != AR5416_EEPROM_MAGIC) { 198 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
188 magic2 = swab16(magic); 199 matchIndex = 0;
200 } else {
201 for (i = 0; (i < numChannels) &&
202 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
203 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
204 IS_CHAN_2GHZ(chan))) {
205 matchIndex = i;
206 break;
207 } else
208 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
209 IS_CHAN_2GHZ(chan))) &&
210 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
211 IS_CHAN_2GHZ(chan)))) {
212 lowIndex = i - 1;
213 break;
214 }
215 }
216 if ((matchIndex == -1) && (lowIndex == -1))
217 matchIndex = i - 1;
218 }
189 219
190 if (magic2 == AR5416_EEPROM_MAGIC) { 220 if (matchIndex != -1) {
191 size = sizeof(struct ar5416_eeprom_def); 221 *pNewPower = powInfo[matchIndex];
192 need_swap = true; 222 } else {
193 eepdata = (u16 *) (&ahp->ah_eeprom); 223 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
224 IS_CHAN_2GHZ(chan));
225 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
226 IS_CHAN_2GHZ(chan));
194 227
195 for (addr = 0; addr < size / sizeof(u16); addr++) { 228 for (i = 0; i < numRates; i++) {
196 temp = swab16(*eepdata); 229 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
197 *eepdata = temp; 230 clo, chi,
198 eepdata++; 231 powInfo[lowIndex].tPow2x[i],
232 powInfo[lowIndex + 1].tPow2x[i]);
233 }
234 }
235}
199 236
200 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 237static u16 ath9k_hw_get_max_edge_power(u16 freq,
201 "0x%04X ", *eepdata); 238 struct cal_ctl_edges *pRdEdgesPower,
239 bool is2GHz, int num_band_edges)
240{
241 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
242 int i;
202 243
203 if (((addr + 1) % 6) == 0) 244 for (i = 0; (i < num_band_edges) &&
204 DPRINTF(ah->ah_sc, 245 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
205 ATH_DBG_EEPROM, "\n"); 246 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
206 } 247 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
207 } else { 248 break;
208 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 249 } else if ((i > 0) &&
209 "Invalid EEPROM Magic. " 250 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
210 "endianness mismatch.\n"); 251 is2GHz))) {
211 return -EINVAL; 252 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
253 is2GHz) < freq &&
254 pRdEdgesPower[i - 1].flag) {
255 twiceMaxEdgePower =
256 pRdEdgesPower[i - 1].tPower;
212 } 257 }
258 break;
213 } 259 }
214 } 260 }
215 261
216 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 262 return twiceMaxEdgePower;
217 need_swap ? "True" : "False"); 263}
218 264
219 if (need_swap) 265/****************************************/
220 el = swab16(ahp->ah_eeprom.def.baseEepHeader.length); 266/* EEPROM Operations for 4K sized cards */
221 else 267/****************************************/
222 el = ahp->ah_eeprom.def.baseEepHeader.length;
223 268
224 if (el > sizeof(struct ar5416_eeprom_def)) 269static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
225 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); 270{
226 else 271 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
227 el = el / sizeof(u16); 272}
228 273
229 eepdata = (u16 *)(&ahp->ah_eeprom); 274static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
275{
276 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
277}
230 278
231 for (i = 0; i < el; i++) 279static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
232 sum ^= *eepdata++; 280{
281#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
282 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
283 u16 *eep_data;
284 int addr, eep_start_loc = 0;
233 285
234 if (need_swap) { 286 eep_start_loc = 64;
235 u32 integer, j;
236 u16 word;
237 287
288 if (!ath9k_hw_use_flash(ah)) {
238 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 289 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
239 "EEPROM Endianness is not native.. Changing \n"); 290 "Reading from EEPROM, not flash\n");
240 291 }
241 word = swab16(eep->baseEepHeader.length);
242 eep->baseEepHeader.length = word;
243
244 word = swab16(eep->baseEepHeader.checksum);
245 eep->baseEepHeader.checksum = word;
246
247 word = swab16(eep->baseEepHeader.version);
248 eep->baseEepHeader.version = word;
249
250 word = swab16(eep->baseEepHeader.regDmn[0]);
251 eep->baseEepHeader.regDmn[0] = word;
252
253 word = swab16(eep->baseEepHeader.regDmn[1]);
254 eep->baseEepHeader.regDmn[1] = word;
255
256 word = swab16(eep->baseEepHeader.rfSilent);
257 eep->baseEepHeader.rfSilent = word;
258
259 word = swab16(eep->baseEepHeader.blueToothOptions);
260 eep->baseEepHeader.blueToothOptions = word;
261
262 word = swab16(eep->baseEepHeader.deviceCap);
263 eep->baseEepHeader.deviceCap = word;
264
265 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
266 struct modal_eep_header *pModal =
267 &eep->modalHeader[j];
268 integer = swab32(pModal->antCtrlCommon);
269 pModal->antCtrlCommon = integer;
270 292
271 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 293 eep_data = (u16 *)eep;
272 integer = swab32(pModal->antCtrlChain[i]);
273 pModal->antCtrlChain[i] = integer;
274 }
275 294
276 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 295 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
277 word = swab16(pModal->spurChans[i].spurChan); 296 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
278 pModal->spurChans[i].spurChan = word; 297 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
279 } 298 "Unable to read eeprom region \n");
299 return false;
280 } 300 }
301 eep_data++;
281 } 302 }
282 303 return true;
283 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || 304#undef SIZE_EEPROM_4K
284 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
285 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
286 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
287 sum, ar5416_get_eep_ver(ahp));
288 return -EINVAL;
289 }
290
291 return 0;
292} 305}
293 306
294static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) 307static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
295{ 308{
296#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 309#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
297 struct ath_hal_5416 *ahp = AH5416(ah);
298 struct ar5416_eeprom_4k *eep = 310 struct ar5416_eeprom_4k *eep =
299 (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k; 311 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
300 u16 *eepdata, temp, magic, magic2; 312 u16 *eepdata, temp, magic, magic2;
301 u32 sum = 0, el; 313 u32 sum = 0, el;
302 bool need_swap = false; 314 bool need_swap = false;
@@ -320,7 +332,7 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
320 332
321 if (magic2 == AR5416_EEPROM_MAGIC) { 333 if (magic2 == AR5416_EEPROM_MAGIC) {
322 need_swap = true; 334 need_swap = true;
323 eepdata = (u16 *) (&ahp->ah_eeprom); 335 eepdata = (u16 *) (&ah->eeprom);
324 336
325 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 337 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
326 temp = swab16(*eepdata); 338 temp = swab16(*eepdata);
@@ -347,16 +359,16 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
347 need_swap ? "True" : "False"); 359 need_swap ? "True" : "False");
348 360
349 if (need_swap) 361 if (need_swap)
350 el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length); 362 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
351 else 363 else
352 el = ahp->ah_eeprom.map4k.baseEepHeader.length; 364 el = ah->eeprom.map4k.baseEepHeader.length;
353 365
354 if (el > sizeof(struct ar5416_eeprom_def)) 366 if (el > sizeof(struct ar5416_eeprom_def))
355 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 367 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
356 else 368 else
357 el = el / sizeof(u16); 369 el = el / sizeof(u16);
358 370
359 eepdata = (u16 *)(&ahp->ah_eeprom); 371 eepdata = (u16 *)(&ah->eeprom);
360 372
361 for (i = 0; i < el; i++) 373 for (i = 0; i < el; i++)
362 sum ^= *eepdata++; 374 sum ^= *eepdata++;
@@ -406,11 +418,11 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
406 } 418 }
407 } 419 }
408 420
409 if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER || 421 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
410 ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) { 422 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
411 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 423 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
412 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 424 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
413 sum, ar5416_get_eep4k_ver(ahp)); 425 sum, ah->eep_ops->get_eeprom_ver(ah));
414 return -EINVAL; 426 return -EINVAL;
415 } 427 }
416 428
@@ -418,48 +430,48 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
418#undef EEPROM_4K_SIZE 430#undef EEPROM_4K_SIZE
419} 431}
420 432
421static int (*ath9k_check_eeprom[]) (struct ath_hal *) = { 433static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
422 ath9k_hw_check_def_eeprom, 434 enum eeprom_param param)
423 ath9k_hw_check_4k_eeprom
424};
425
426static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
427{
428 struct ath_hal_5416 *ahp = AH5416(ah);
429
430 return ath9k_check_eeprom[ahp->ah_eep_map](ah);
431}
432
433static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
434 u8 *pVpdList, u16 numIntercepts,
435 u8 *pRetVpdList)
436{ 435{
437 u16 i, k; 436 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
438 u8 currPwr = pwrMin; 437 struct modal_eep_4k_header *pModal = &eep->modalHeader;
439 u16 idxL = 0, idxR = 0; 438 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
440 439
441 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 440 switch (param) {
442 ath9k_hw_get_lower_upper_index(currPwr, pPwrList, 441 case EEP_NFTHRESH_2:
443 numIntercepts, &(idxL), 442 return pModal[1].noiseFloorThreshCh[0];
444 &(idxR)); 443 case AR_EEPROM_MAC(0):
445 if (idxR < 1) 444 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
446 idxR = 1; 445 case AR_EEPROM_MAC(1):
447 if (idxL == numIntercepts - 1) 446 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
448 idxL = (u16) (numIntercepts - 2); 447 case AR_EEPROM_MAC(2):
449 if (pPwrList[idxL] == pPwrList[idxR]) 448 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
450 k = pVpdList[idxL]; 449 case EEP_REG_0:
451 else 450 return pBase->regDmn[0];
452 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + 451 case EEP_REG_1:
453 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 452 return pBase->regDmn[1];
454 (pPwrList[idxR] - pPwrList[idxL])); 453 case EEP_OP_CAP:
455 pRetVpdList[i] = (u8) k; 454 return pBase->deviceCap;
456 currPwr += 2; 455 case EEP_OP_MODE:
456 return pBase->opCapFlags;
457 case EEP_RF_SILENT:
458 return pBase->rfSilent;
459 case EEP_OB_2:
460 return pModal->ob_01;
461 case EEP_DB_2:
462 return pModal->db1_01;
463 case EEP_MINOR_REV:
464 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
465 case EEP_TX_MASK:
466 return pBase->txMask;
467 case EEP_RX_MASK:
468 return pBase->rxMask;
469 default:
470 return 0;
457 } 471 }
458
459 return true;
460} 472}
461 473
462static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, 474static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
463 struct ath9k_channel *chan, 475 struct ath9k_channel *chan,
464 struct cal_data_per_freq_4k *pRawDataSet, 476 struct cal_data_per_freq_4k *pRawDataSet,
465 u8 *bChans, u16 availPiers, 477 u8 *bChans, u16 availPiers,
@@ -627,442 +639,11 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah,
627#undef TMP_VAL_VPD_TABLE 639#undef TMP_VAL_VPD_TABLE
628} 640}
629 641
630static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, 642static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
631 struct ath9k_channel *chan,
632 struct cal_data_per_freq *pRawDataSet,
633 u8 *bChans, u16 availPiers,
634 u16 tPdGainOverlap, int16_t *pMinCalPower,
635 u16 *pPdGainBoundaries, u8 *pPDADCValues,
636 u16 numXpdGains)
637{
638 int i, j, k;
639 int16_t ss;
640 u16 idxL = 0, idxR = 0, numPiers;
641 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
642 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
643 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
644 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
645 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
646 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
647
648 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
649 u8 minPwrT4[AR5416_NUM_PD_GAINS];
650 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
651 int16_t vpdStep;
652 int16_t tmpVal;
653 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
654 bool match;
655 int16_t minDelta = 0;
656 struct chan_centers centers;
657
658 ath9k_hw_get_channel_centers(ah, chan, &centers);
659
660 for (numPiers = 0; numPiers < availPiers; numPiers++) {
661 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
662 break;
663 }
664
665 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
666 IS_CHAN_2GHZ(chan)),
667 bChans, numPiers, &idxL, &idxR);
668
669 if (match) {
670 for (i = 0; i < numXpdGains; i++) {
671 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
672 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
673 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
674 pRawDataSet[idxL].pwrPdg[i],
675 pRawDataSet[idxL].vpdPdg[i],
676 AR5416_PD_GAIN_ICEPTS,
677 vpdTableI[i]);
678 }
679 } else {
680 for (i = 0; i < numXpdGains; i++) {
681 pVpdL = pRawDataSet[idxL].vpdPdg[i];
682 pPwrL = pRawDataSet[idxL].pwrPdg[i];
683 pVpdR = pRawDataSet[idxR].vpdPdg[i];
684 pPwrR = pRawDataSet[idxR].pwrPdg[i];
685
686 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
687
688 maxPwrT4[i] =
689 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
690 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
691
692
693 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
694 pPwrL, pVpdL,
695 AR5416_PD_GAIN_ICEPTS,
696 vpdTableL[i]);
697 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
698 pPwrR, pVpdR,
699 AR5416_PD_GAIN_ICEPTS,
700 vpdTableR[i]);
701
702 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
703 vpdTableI[i][j] =
704 (u8)(ath9k_hw_interpolate((u16)
705 FREQ2FBIN(centers.
706 synth_center,
707 IS_CHAN_2GHZ
708 (chan)),
709 bChans[idxL], bChans[idxR],
710 vpdTableL[i][j], vpdTableR[i][j]));
711 }
712 }
713 }
714
715 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
716
717 k = 0;
718
719 for (i = 0; i < numXpdGains; i++) {
720 if (i == (numXpdGains - 1))
721 pPdGainBoundaries[i] =
722 (u16)(maxPwrT4[i] / 2);
723 else
724 pPdGainBoundaries[i] =
725 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
726
727 pPdGainBoundaries[i] =
728 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
729
730 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
731 minDelta = pPdGainBoundaries[0] - 23;
732 pPdGainBoundaries[0] = 23;
733 } else {
734 minDelta = 0;
735 }
736
737 if (i == 0) {
738 if (AR_SREV_9280_10_OR_LATER(ah))
739 ss = (int16_t)(0 - (minPwrT4[i] / 2));
740 else
741 ss = 0;
742 } else {
743 ss = (int16_t)((pPdGainBoundaries[i - 1] -
744 (minPwrT4[i] / 2)) -
745 tPdGainOverlap + 1 + minDelta);
746 }
747 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
748 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
749
750 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
751 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
752 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
753 ss++;
754 }
755
756 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
757 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
758 (minPwrT4[i] / 2));
759 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
760 tgtIndex : sizeCurrVpdTable;
761
762 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
763 pPDADCValues[k++] = vpdTableI[i][ss++];
764 }
765
766 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
767 vpdTableI[i][sizeCurrVpdTable - 2]);
768 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
769
770 if (tgtIndex > maxIndex) {
771 while ((ss <= tgtIndex) &&
772 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
773 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
774 (ss - maxIndex + 1) * vpdStep));
775 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
776 255 : tmpVal);
777 ss++;
778 }
779 }
780 }
781
782 while (i < AR5416_PD_GAINS_IN_MASK) {
783 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
784 i++;
785 }
786
787 while (k < AR5416_NUM_PDADC_VALUES) {
788 pPDADCValues[k] = pPDADCValues[k - 1];
789 k++;
790 }
791
792 return;
793}
794
795static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
796 struct ath9k_channel *chan,
797 struct cal_target_power_leg *powInfo,
798 u16 numChannels,
799 struct cal_target_power_leg *pNewPower,
800 u16 numRates, bool isExtTarget)
801{
802 struct chan_centers centers;
803 u16 clo, chi;
804 int i;
805 int matchIndex = -1, lowIndex = -1;
806 u16 freq;
807
808 ath9k_hw_get_channel_centers(ah, chan, &centers);
809 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
810
811 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
812 IS_CHAN_2GHZ(chan))) {
813 matchIndex = 0;
814 } else {
815 for (i = 0; (i < numChannels) &&
816 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
817 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
818 IS_CHAN_2GHZ(chan))) {
819 matchIndex = i;
820 break;
821 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
822 IS_CHAN_2GHZ(chan))) &&
823 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
824 IS_CHAN_2GHZ(chan)))) {
825 lowIndex = i - 1;
826 break;
827 }
828 }
829 if ((matchIndex == -1) && (lowIndex == -1))
830 matchIndex = i - 1;
831 }
832
833 if (matchIndex != -1) {
834 *pNewPower = powInfo[matchIndex];
835 } else {
836 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
837 IS_CHAN_2GHZ(chan));
838 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
839 IS_CHAN_2GHZ(chan));
840
841 for (i = 0; i < numRates; i++) {
842 pNewPower->tPow2x[i] =
843 (u8)ath9k_hw_interpolate(freq, clo, chi,
844 powInfo[lowIndex].tPow2x[i],
845 powInfo[lowIndex + 1].tPow2x[i]);
846 }
847 }
848}
849
850static void ath9k_hw_get_target_powers(struct ath_hal *ah,
851 struct ath9k_channel *chan,
852 struct cal_target_power_ht *powInfo,
853 u16 numChannels,
854 struct cal_target_power_ht *pNewPower,
855 u16 numRates, bool isHt40Target)
856{
857 struct chan_centers centers;
858 u16 clo, chi;
859 int i;
860 int matchIndex = -1, lowIndex = -1;
861 u16 freq;
862
863 ath9k_hw_get_channel_centers(ah, chan, &centers);
864 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
865
866 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
867 matchIndex = 0;
868 } else {
869 for (i = 0; (i < numChannels) &&
870 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
871 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
872 IS_CHAN_2GHZ(chan))) {
873 matchIndex = i;
874 break;
875 } else
876 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
877 IS_CHAN_2GHZ(chan))) &&
878 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
879 IS_CHAN_2GHZ(chan)))) {
880 lowIndex = i - 1;
881 break;
882 }
883 }
884 if ((matchIndex == -1) && (lowIndex == -1))
885 matchIndex = i - 1;
886 }
887
888 if (matchIndex != -1) {
889 *pNewPower = powInfo[matchIndex];
890 } else {
891 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
892 IS_CHAN_2GHZ(chan));
893 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
894 IS_CHAN_2GHZ(chan));
895
896 for (i = 0; i < numRates; i++) {
897 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
898 clo, chi,
899 powInfo[lowIndex].tPow2x[i],
900 powInfo[lowIndex + 1].tPow2x[i]);
901 }
902 }
903}
904
905static u16 ath9k_hw_get_max_edge_power(u16 freq,
906 struct cal_ctl_edges *pRdEdgesPower,
907 bool is2GHz, int num_band_edges)
908{
909 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
910 int i;
911
912 for (i = 0; (i < num_band_edges) &&
913 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
914 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
915 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
916 break;
917 } else if ((i > 0) &&
918 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
919 is2GHz))) {
920 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
921 is2GHz) < freq &&
922 pRdEdgesPower[i - 1].flag) {
923 twiceMaxEdgePower =
924 pRdEdgesPower[i - 1].tPower;
925 }
926 break;
927 }
928 }
929
930 return twiceMaxEdgePower;
931}
932
933static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
934 struct ath9k_channel *chan,
935 int16_t *pTxPowerIndexOffset)
936{
937 struct ath_hal_5416 *ahp = AH5416(ah);
938 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
939 struct cal_data_per_freq *pRawDataset;
940 u8 *pCalBChans = NULL;
941 u16 pdGainOverlap_t2;
942 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
943 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
944 u16 numPiers, i, j;
945 int16_t tMinCalPower;
946 u16 numXpdGain, xpdMask;
947 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
948 u32 reg32, regOffset, regChainOffset;
949 int16_t modalIdx;
950
951 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
952 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
953
954 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
955 AR5416_EEP_MINOR_VER_2) {
956 pdGainOverlap_t2 =
957 pEepData->modalHeader[modalIdx].pdGainOverlap;
958 } else {
959 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
960 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
961 }
962
963 if (IS_CHAN_2GHZ(chan)) {
964 pCalBChans = pEepData->calFreqPier2G;
965 numPiers = AR5416_NUM_2G_CAL_PIERS;
966 } else {
967 pCalBChans = pEepData->calFreqPier5G;
968 numPiers = AR5416_NUM_5G_CAL_PIERS;
969 }
970
971 numXpdGain = 0;
972
973 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
974 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
975 if (numXpdGain >= AR5416_NUM_PD_GAINS)
976 break;
977 xpdGainValues[numXpdGain] =
978 (u16)(AR5416_PD_GAINS_IN_MASK - i);
979 numXpdGain++;
980 }
981 }
982
983 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
984 (numXpdGain - 1) & 0x3);
985 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
986 xpdGainValues[0]);
987 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
988 xpdGainValues[1]);
989 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
990 xpdGainValues[2]);
991
992 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
993 if (AR_SREV_5416_V20_OR_LATER(ah) &&
994 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
995 (i != 0)) {
996 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
997 } else
998 regChainOffset = i * 0x1000;
999
1000 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1001 if (IS_CHAN_2GHZ(chan))
1002 pRawDataset = pEepData->calPierData2G[i];
1003 else
1004 pRawDataset = pEepData->calPierData5G[i];
1005
1006 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
1007 pRawDataset, pCalBChans,
1008 numPiers, pdGainOverlap_t2,
1009 &tMinCalPower, gainBoundaries,
1010 pdadcValues, numXpdGain);
1011
1012 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1013 REG_WRITE(ah,
1014 AR_PHY_TPCRG5 + regChainOffset,
1015 SM(pdGainOverlap_t2,
1016 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1017 | SM(gainBoundaries[0],
1018 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1019 | SM(gainBoundaries[1],
1020 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1021 | SM(gainBoundaries[2],
1022 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1023 | SM(gainBoundaries[3],
1024 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1025 }
1026
1027 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1028 for (j = 0; j < 32; j++) {
1029 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1030 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1031 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
1032 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1033 REG_WRITE(ah, regOffset, reg32);
1034
1035 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1036 "PDADC (%d,%4x): %4.4x %8.8x\n",
1037 i, regChainOffset, regOffset,
1038 reg32);
1039 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1040 "PDADC: Chain %d | PDADC %3d "
1041 "Value %3d | PDADC %3d Value %3d | "
1042 "PDADC %3d Value %3d | PDADC %3d "
1043 "Value %3d |\n",
1044 i, 4 * j, pdadcValues[4 * j],
1045 4 * j + 1, pdadcValues[4 * j + 1],
1046 4 * j + 2, pdadcValues[4 * j + 2],
1047 4 * j + 3,
1048 pdadcValues[4 * j + 3]);
1049
1050 regOffset += 4;
1051 }
1052 }
1053 }
1054
1055 *pTxPowerIndexOffset = 0;
1056
1057 return true;
1058}
1059
1060static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1061 struct ath9k_channel *chan, 643 struct ath9k_channel *chan,
1062 int16_t *pTxPowerIndexOffset) 644 int16_t *pTxPowerIndexOffset)
1063{ 645{
1064 struct ath_hal_5416 *ahp = AH5416(ah); 646 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1065 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1066 struct cal_data_per_freq_4k *pRawDataset; 647 struct cal_data_per_freq_4k *pRawDataset;
1067 u8 *pCalBChans = NULL; 648 u8 *pCalBChans = NULL;
1068 u16 pdGainOverlap_t2; 649 u16 pdGainOverlap_t2;
@@ -1111,7 +692,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1111 692
1112 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 693 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1113 if (AR_SREV_5416_V20_OR_LATER(ah) && 694 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1114 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && 695 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
1115 (i != 0)) { 696 (i != 0)) {
1116 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 697 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1117 } else 698 } else
@@ -1174,298 +755,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1174 return true; 755 return true;
1175} 756}
1176 757
1177static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, 758static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
1178 struct ath9k_channel *chan,
1179 int16_t *ratesArray,
1180 u16 cfgCtl,
1181 u16 AntennaReduction,
1182 u16 twiceMaxRegulatoryPower,
1183 u16 powerLimit)
1184{
1185#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1186#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
1187
1188 struct ath_hal_5416 *ahp = AH5416(ah);
1189 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1190 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1191 static const u16 tpScaleReductionTable[5] =
1192 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1193
1194 int i;
1195 int16_t twiceLargestAntenna;
1196 struct cal_ctl_data *rep;
1197 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1198 0, { 0, 0, 0, 0}
1199 };
1200 struct cal_target_power_leg targetPowerOfdmExt = {
1201 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1202 0, { 0, 0, 0, 0 }
1203 };
1204 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1205 0, {0, 0, 0, 0}
1206 };
1207 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1208 u16 ctlModesFor11a[] =
1209 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1210 u16 ctlModesFor11g[] =
1211 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1212 CTL_2GHT40
1213 };
1214 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1215 struct chan_centers centers;
1216 int tx_chainmask;
1217 u16 twiceMinEdgePower;
1218
1219 tx_chainmask = ahp->ah_txchainmask;
1220
1221 ath9k_hw_get_channel_centers(ah, chan, &centers);
1222
1223 twiceLargestAntenna = max(
1224 pEepData->modalHeader
1225 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1226 pEepData->modalHeader
1227 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1228
1229 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1230 pEepData->modalHeader
1231 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1232
1233 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1234 twiceLargestAntenna, 0);
1235
1236 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1237
1238 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1239 maxRegAllowedPower -=
1240 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1241 }
1242
1243 scaledPower = min(powerLimit, maxRegAllowedPower);
1244
1245 switch (ar5416_get_ntxchains(tx_chainmask)) {
1246 case 1:
1247 break;
1248 case 2:
1249 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1250 break;
1251 case 3:
1252 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1253 break;
1254 }
1255
1256 scaledPower = max((u16)0, scaledPower);
1257
1258 if (IS_CHAN_2GHZ(chan)) {
1259 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1260 SUB_NUM_CTL_MODES_AT_2G_40;
1261 pCtlMode = ctlModesFor11g;
1262
1263 ath9k_hw_get_legacy_target_powers(ah, chan,
1264 pEepData->calTargetPowerCck,
1265 AR5416_NUM_2G_CCK_TARGET_POWERS,
1266 &targetPowerCck, 4, false);
1267 ath9k_hw_get_legacy_target_powers(ah, chan,
1268 pEepData->calTargetPower2G,
1269 AR5416_NUM_2G_20_TARGET_POWERS,
1270 &targetPowerOfdm, 4, false);
1271 ath9k_hw_get_target_powers(ah, chan,
1272 pEepData->calTargetPower2GHT20,
1273 AR5416_NUM_2G_20_TARGET_POWERS,
1274 &targetPowerHt20, 8, false);
1275
1276 if (IS_CHAN_HT40(chan)) {
1277 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1278 ath9k_hw_get_target_powers(ah, chan,
1279 pEepData->calTargetPower2GHT40,
1280 AR5416_NUM_2G_40_TARGET_POWERS,
1281 &targetPowerHt40, 8, true);
1282 ath9k_hw_get_legacy_target_powers(ah, chan,
1283 pEepData->calTargetPowerCck,
1284 AR5416_NUM_2G_CCK_TARGET_POWERS,
1285 &targetPowerCckExt, 4, true);
1286 ath9k_hw_get_legacy_target_powers(ah, chan,
1287 pEepData->calTargetPower2G,
1288 AR5416_NUM_2G_20_TARGET_POWERS,
1289 &targetPowerOfdmExt, 4, true);
1290 }
1291 } else {
1292 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1293 SUB_NUM_CTL_MODES_AT_5G_40;
1294 pCtlMode = ctlModesFor11a;
1295
1296 ath9k_hw_get_legacy_target_powers(ah, chan,
1297 pEepData->calTargetPower5G,
1298 AR5416_NUM_5G_20_TARGET_POWERS,
1299 &targetPowerOfdm, 4, false);
1300 ath9k_hw_get_target_powers(ah, chan,
1301 pEepData->calTargetPower5GHT20,
1302 AR5416_NUM_5G_20_TARGET_POWERS,
1303 &targetPowerHt20, 8, false);
1304
1305 if (IS_CHAN_HT40(chan)) {
1306 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1307 ath9k_hw_get_target_powers(ah, chan,
1308 pEepData->calTargetPower5GHT40,
1309 AR5416_NUM_5G_40_TARGET_POWERS,
1310 &targetPowerHt40, 8, true);
1311 ath9k_hw_get_legacy_target_powers(ah, chan,
1312 pEepData->calTargetPower5G,
1313 AR5416_NUM_5G_20_TARGET_POWERS,
1314 &targetPowerOfdmExt, 4, true);
1315 }
1316 }
1317
1318 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1319 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1320 (pCtlMode[ctlMode] == CTL_2GHT40);
1321 if (isHt40CtlMode)
1322 freq = centers.synth_center;
1323 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1324 freq = centers.ext_center;
1325 else
1326 freq = centers.ctl_center;
1327
1328 if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2)
1329 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1330
1331 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1332 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
1333 "EXT_ADDITIVE %d\n",
1334 ctlMode, numCtlModes, isHt40CtlMode,
1335 (pCtlMode[ctlMode] & EXT_ADDITIVE));
1336
1337 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1338 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1339 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
1340 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
1341 "chan %d\n",
1342 i, cfgCtl, pCtlMode[ctlMode],
1343 pEepData->ctlIndex[i], chan->channel);
1344
1345 if ((((cfgCtl & ~CTL_MODE_M) |
1346 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1347 pEepData->ctlIndex[i]) ||
1348 (((cfgCtl & ~CTL_MODE_M) |
1349 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1350 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1351 rep = &(pEepData->ctlData[i]);
1352
1353 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1354 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1355 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1356
1357 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1358 " MATCH-EE_IDX %d: ch %d is2 %d "
1359 "2xMinEdge %d chainmask %d chains %d\n",
1360 i, freq, IS_CHAN_2GHZ(chan),
1361 twiceMinEdgePower, tx_chainmask,
1362 ar5416_get_ntxchains
1363 (tx_chainmask));
1364 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1365 twiceMaxEdgePower = min(twiceMaxEdgePower,
1366 twiceMinEdgePower);
1367 } else {
1368 twiceMaxEdgePower = twiceMinEdgePower;
1369 break;
1370 }
1371 }
1372 }
1373
1374 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1375
1376 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1377 " SEL-Min ctlMode %d pCtlMode %d "
1378 "2xMaxEdge %d sP %d minCtlPwr %d\n",
1379 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
1380 scaledPower, minCtlPower);
1381
1382 switch (pCtlMode[ctlMode]) {
1383 case CTL_11B:
1384 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1385 targetPowerCck.tPow2x[i] =
1386 min((u16)targetPowerCck.tPow2x[i],
1387 minCtlPower);
1388 }
1389 break;
1390 case CTL_11A:
1391 case CTL_11G:
1392 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1393 targetPowerOfdm.tPow2x[i] =
1394 min((u16)targetPowerOfdm.tPow2x[i],
1395 minCtlPower);
1396 }
1397 break;
1398 case CTL_5GHT20:
1399 case CTL_2GHT20:
1400 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1401 targetPowerHt20.tPow2x[i] =
1402 min((u16)targetPowerHt20.tPow2x[i],
1403 minCtlPower);
1404 }
1405 break;
1406 case CTL_11B_EXT:
1407 targetPowerCckExt.tPow2x[0] = min((u16)
1408 targetPowerCckExt.tPow2x[0],
1409 minCtlPower);
1410 break;
1411 case CTL_11A_EXT:
1412 case CTL_11G_EXT:
1413 targetPowerOfdmExt.tPow2x[0] = min((u16)
1414 targetPowerOfdmExt.tPow2x[0],
1415 minCtlPower);
1416 break;
1417 case CTL_5GHT40:
1418 case CTL_2GHT40:
1419 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1420 targetPowerHt40.tPow2x[i] =
1421 min((u16)targetPowerHt40.tPow2x[i],
1422 minCtlPower);
1423 }
1424 break;
1425 default:
1426 break;
1427 }
1428 }
1429
1430 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1431 ratesArray[rate18mb] = ratesArray[rate24mb] =
1432 targetPowerOfdm.tPow2x[0];
1433 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1434 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1435 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1436 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1437
1438 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1439 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1440
1441 if (IS_CHAN_2GHZ(chan)) {
1442 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1443 ratesArray[rate2s] = ratesArray[rate2l] =
1444 targetPowerCck.tPow2x[1];
1445 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1446 targetPowerCck.tPow2x[2];
1447 ;
1448 ratesArray[rate11s] = ratesArray[rate11l] =
1449 targetPowerCck.tPow2x[3];
1450 ;
1451 }
1452 if (IS_CHAN_HT40(chan)) {
1453 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1454 ratesArray[rateHt40_0 + i] =
1455 targetPowerHt40.tPow2x[i];
1456 }
1457 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1458 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1459 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1460 if (IS_CHAN_2GHZ(chan)) {
1461 ratesArray[rateExtCck] =
1462 targetPowerCckExt.tPow2x[0];
1463 }
1464 }
1465 return true;
1466}
1467
1468static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1469 struct ath9k_channel *chan, 759 struct ath9k_channel *chan,
1470 int16_t *ratesArray, 760 int16_t *ratesArray,
1471 u16 cfgCtl, 761 u16 cfgCtl,
@@ -1473,8 +763,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1473 u16 twiceMaxRegulatoryPower, 763 u16 twiceMaxRegulatoryPower,
1474 u16 powerLimit) 764 u16 powerLimit)
1475{ 765{
1476 struct ath_hal_5416 *ahp = AH5416(ah); 766 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1477 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1478 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 767 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1479 static const u16 tpScaleReductionTable[5] = 768 static const u16 tpScaleReductionTable[5] =
1480 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 769 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
@@ -1502,7 +791,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1502 int tx_chainmask; 791 int tx_chainmask;
1503 u16 twiceMinEdgePower; 792 u16 twiceMinEdgePower;
1504 793
1505 tx_chainmask = ahp->ah_txchainmask; 794 tx_chainmask = ah->txchainmask;
1506 795
1507 ath9k_hw_get_channel_centers(ah, chan, &centers); 796 ath9k_hw_get_channel_centers(ah, chan, &centers);
1508 797
@@ -1513,9 +802,9 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1513 802
1514 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 803 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1515 804
1516 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { 805 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
1517 maxRegAllowedPower -= 806 maxRegAllowedPower -=
1518 (tpScaleReductionTable[(ah->ah_tpScale)] * 2); 807 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
1519 } 808 }
1520 809
1521 scaledPower = min(powerLimit, maxRegAllowedPower); 810 scaledPower = min(powerLimit, maxRegAllowedPower);
@@ -1563,8 +852,8 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1563 else 852 else
1564 freq = centers.ctl_center; 853 freq = centers.ctl_center;
1565 854
1566 if (ar5416_get_eep_ver(ahp) == 14 && 855 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1567 ar5416_get_eep_rev(ahp) <= 2) 856 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1568 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 857 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1569 858
1570 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 859 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
@@ -1701,17 +990,15 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1701 return true; 990 return true;
1702} 991}
1703 992
1704static int ath9k_hw_def_set_txpower(struct ath_hal *ah, 993static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1705 struct ath9k_channel *chan, 994 struct ath9k_channel *chan,
1706 u16 cfgCtl, 995 u16 cfgCtl,
1707 u8 twiceAntennaReduction, 996 u8 twiceAntennaReduction,
1708 u8 twiceMaxRegulatoryPower, 997 u8 twiceMaxRegulatoryPower,
1709 u8 powerLimit) 998 u8 powerLimit)
1710{ 999{
1711 struct ath_hal_5416 *ahp = AH5416(ah); 1000 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1712 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; 1001 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1713 struct modal_eep_header *pModal =
1714 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1715 int16_t ratesArray[Ar5416RateSize]; 1002 int16_t ratesArray[Ar5416RateSize];
1716 int16_t txPowerIndexOffset = 0; 1003 int16_t txPowerIndexOffset = 0;
1717 u8 ht40PowerIncForPdadc = 2; 1004 u8 ht40PowerIncForPdadc = 2;
@@ -1724,7 +1011,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1724 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1011 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1725 } 1012 }
1726 1013
1727 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, 1014 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1728 &ratesArray[0], cfgCtl, 1015 &ratesArray[0], cfgCtl,
1729 twiceAntennaReduction, 1016 twiceAntennaReduction,
1730 twiceMaxRegulatoryPower, 1017 twiceMaxRegulatoryPower,
@@ -1735,7 +1022,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1735 return -EIO; 1022 return -EIO;
1736 } 1023 }
1737 1024
1738 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { 1025 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1739 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1026 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1740 "ath9k_hw_set_txpower: unable to set power table\n"); 1027 "ath9k_hw_set_txpower: unable to set power table\n");
1741 return -EIO; 1028 return -EIO;
@@ -1814,10 +1101,6 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1814 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 1101 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1815 } 1102 }
1816 1103
1817 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1818 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1819 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1820
1821 i = rate6mb; 1104 i = rate6mb;
1822 1105
1823 if (IS_CHAN_HT40(chan)) 1106 if (IS_CHAN_HT40(chan))
@@ -1826,263 +1109,509 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1826 i = rateHt20_0; 1109 i = rateHt20_0;
1827 1110
1828 if (AR_SREV_9280_10_OR_LATER(ah)) 1111 if (AR_SREV_9280_10_OR_LATER(ah))
1829 ah->ah_maxPowerLevel = 1112 ah->regulatory.max_power_level =
1830 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; 1113 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1831 else 1114 else
1832 ah->ah_maxPowerLevel = ratesArray[i]; 1115 ah->regulatory.max_power_level = ratesArray[i];
1833 1116
1834 return 0; 1117 return 0;
1835} 1118}
1836 1119
1837static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, 1120static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1838 struct ath9k_channel *chan, 1121 struct ath9k_channel *chan)
1839 u16 cfgCtl,
1840 u8 twiceAntennaReduction,
1841 u8 twiceMaxRegulatoryPower,
1842 u8 powerLimit)
1843{ 1122{
1844 struct ath_hal_5416 *ahp = AH5416(ah); 1123 struct modal_eep_4k_header *pModal;
1845 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; 1124 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1846 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 1125 u8 biaslevel;
1847 int16_t ratesArray[Ar5416RateSize];
1848 int16_t txPowerIndexOffset = 0;
1849 u8 ht40PowerIncForPdadc = 2;
1850 int i;
1851 1126
1852 memset(ratesArray, 0, sizeof(ratesArray)); 1127 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1128 return;
1853 1129
1854 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1130 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1855 AR5416_EEP_MINOR_VER_2) { 1131 return;
1856 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1132
1133 pModal = &eep->modalHeader;
1134
1135 if (pModal->xpaBiasLvl != 0xff) {
1136 biaslevel = pModal->xpaBiasLvl;
1137 INI_RA(&ah->iniAddac, 7, 1) =
1138 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1857 } 1139 }
1140}
1858 1141
1859 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, 1142static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1860 &ratesArray[0], cfgCtl, 1143 struct ath9k_channel *chan)
1861 twiceAntennaReduction, 1144{
1862 twiceMaxRegulatoryPower, 1145 struct modal_eep_4k_header *pModal;
1863 powerLimit)) { 1146 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1864 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1147 int regChainOffset;
1865 "ath9k_hw_set_txpower: unable to set " 1148 u8 txRxAttenLocal;
1866 "tx power per rate table\n"); 1149 u8 ob[5], db1[5], db2[5];
1867 return -EIO; 1150 u8 ant_div_control1, ant_div_control2;
1151 u32 regVal;
1152
1153
1154 pModal = &eep->modalHeader;
1155
1156 txRxAttenLocal = 23;
1157
1158 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1159 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1160
1161 regChainOffset = 0;
1162 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1163 pModal->antCtrlChain[0]);
1164
1165 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1166 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1167 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1168 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1169 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1170 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1171
1172 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1173 AR5416_EEP_MINOR_VER_3) {
1174 txRxAttenLocal = pModal->txRxAttenCh[0];
1175 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1176 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1177 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1178 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1179 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1180 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1181 pModal->xatten2Margin[0]);
1182 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1183 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1868 } 1184 }
1869 1185
1870 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { 1186 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1187 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1188 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1189 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1190
1191 if (AR_SREV_9285_11(ah))
1192 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1193
1194 /* Initialize Ant Diversity settings from EEPROM */
1195 if (pModal->version == 3) {
1196 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1197 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1198 regVal = REG_READ(ah, 0x99ac);
1199 regVal &= (~(0x7f000000));
1200 regVal |= ((ant_div_control1 & 0x1) << 24);
1201 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1202 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1203 regVal |= ((ant_div_control2 & 0x3) << 25);
1204 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1205 REG_WRITE(ah, 0x99ac, regVal);
1206 regVal = REG_READ(ah, 0x99ac);
1207 regVal = REG_READ(ah, 0xa208);
1208 regVal &= (~(0x1 << 13));
1209 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1210 REG_WRITE(ah, 0xa208, regVal);
1211 regVal = REG_READ(ah, 0xa208);
1212 }
1213
1214 if (pModal->version >= 2) {
1215 ob[0] = (pModal->ob_01 & 0xf);
1216 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1217 ob[2] = (pModal->ob_234 & 0xf);
1218 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1219 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1220
1221 db1[0] = (pModal->db1_01 & 0xf);
1222 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1223 db1[2] = (pModal->db1_234 & 0xf);
1224 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1225 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1226
1227 db2[0] = (pModal->db2_01 & 0xf);
1228 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1229 db2[2] = (pModal->db2_234 & 0xf);
1230 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1231 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1232
1233 } else if (pModal->version == 1) {
1234
1871 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1235 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1872 "ath9k_hw_set_txpower: unable to set power table\n"); 1236 "EEPROM Model version is set to 1 \n");
1873 return -EIO; 1237 ob[0] = (pModal->ob_01 & 0xf);
1238 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1239 db1[0] = (pModal->db1_01 & 0xf);
1240 db1[1] = db1[2] = db1[3] =
1241 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1242 db2[0] = (pModal->db2_01 & 0xf);
1243 db2[1] = db2[2] = db2[3] =
1244 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1245 } else {
1246 int i;
1247 for (i = 0; i < 5; i++) {
1248 ob[i] = pModal->ob_01;
1249 db1[i] = pModal->db1_01;
1250 db2[i] = pModal->db1_01;
1251 }
1874 } 1252 }
1875 1253
1876 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1254 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1877 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1255 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
1878 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1256 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1879 ratesArray[i] = AR5416_MAX_RATE_POWER; 1257 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
1258 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1259 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
1260 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1261 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
1262 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1263 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
1264
1265 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1266 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
1267 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1268 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
1269 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1270 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
1271 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1272 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
1273 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1274 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1275
1276 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1277 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
1278 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1279 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
1280 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1281 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
1282 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1283 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
1284 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1285 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
1286
1287
1288 if (AR_SREV_9285_11(ah))
1289 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1290
1291 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1292 pModal->switchSettling);
1293 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1294 pModal->adcDesiredSize);
1295
1296 REG_WRITE(ah, AR_PHY_RF_CTL4,
1297 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1298 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1299 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1300 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1301
1302 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1303 pModal->txEndToRxOn);
1304 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1305 pModal->thresh62);
1306 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1307 pModal->thresh62);
1308
1309 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1310 AR5416_EEP_MINOR_VER_2) {
1311 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1312 pModal->txFrameToDataStart);
1313 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1314 pModal->txFrameToPaOn);
1880 } 1315 }
1881 1316
1882 if (AR_SREV_9280_10_OR_LATER(ah)) { 1317 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1883 for (i = 0; i < Ar5416RateSize; i++) 1318 AR5416_EEP_MINOR_VER_3) {
1884 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1319 if (IS_CHAN_HT40(chan))
1320 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1321 AR_PHY_SETTLING_SWITCH,
1322 pModal->swSettleHt40);
1885 } 1323 }
1886 1324
1887 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1325 return true;
1888 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1326}
1889 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1890 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1891 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1892 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1893 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1894 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1895 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1896 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1897 1327
1898 if (IS_CHAN_2GHZ(chan)) { 1328static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1899 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1329 struct ath9k_channel *chan)
1900 ATH9K_POW_SM(ratesArray[rate2s], 24) 1330{
1901 | ATH9K_POW_SM(ratesArray[rate2l], 16) 1331 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1902 | ATH9K_POW_SM(ratesArray[rateXr], 8) 1332 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1903 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1904 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1905 ATH9K_POW_SM(ratesArray[rate11s], 24)
1906 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1907 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1908 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1909 }
1910 1333
1911 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1334 return pModal->antCtrlCommon & 0xFFFF;
1912 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 1335}
1913 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1914 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1915 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1916 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1917 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1918 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1919 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1920 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1921 1336
1922 if (IS_CHAN_HT40(chan)) { 1337static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1923 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1338 enum ieee80211_band freq_band)
1924 ATH9K_POW_SM(ratesArray[rateHt40_3] + 1339{
1925 ht40PowerIncForPdadc, 24) 1340 return 1;
1926 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 1341}
1927 ht40PowerIncForPdadc, 16)
1928 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1929 ht40PowerIncForPdadc, 8)
1930 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1931 ht40PowerIncForPdadc, 0));
1932 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1933 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1934 ht40PowerIncForPdadc, 24)
1935 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1936 ht40PowerIncForPdadc, 16)
1937 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1938 ht40PowerIncForPdadc, 8)
1939 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1940 ht40PowerIncForPdadc, 0));
1941 1342
1942 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 1343u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1943 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 1344{
1944 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 1345#define EEP_MAP4K_SPURCHAN \
1945 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 1346 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1946 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1947 }
1948 1347
1949 i = rate6mb; 1348 u16 spur_val = AR_NO_SPUR;
1950 1349
1951 if (IS_CHAN_HT40(chan)) 1350 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1952 i = rateHt40_0; 1351 "Getting spur idx %d is2Ghz. %d val %x\n",
1953 else if (IS_CHAN_HT20(chan)) 1352 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1954 i = rateHt20_0;
1955 1353
1956 if (AR_SREV_9280_10_OR_LATER(ah)) 1354 switch (ah->config.spurmode) {
1957 ah->ah_maxPowerLevel = 1355 case SPUR_DISABLE:
1958 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; 1356 break;
1959 else 1357 case SPUR_ENABLE_IOCTL:
1960 ah->ah_maxPowerLevel = ratesArray[i]; 1358 spur_val = ah->config.spurchans[i][is2GHz];
1359 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360 "Getting spur val from new loc. %d\n", spur_val);
1361 break;
1362 case SPUR_ENABLE_EEPROM:
1363 spur_val = EEP_MAP4K_SPURCHAN;
1364 break;
1365 }
1961 1366
1962 return 0; 1367 return spur_val;
1368
1369#undef EEP_MAP4K_SPURCHAN
1963} 1370}
1964 1371
1965static int (*ath9k_set_txpower[]) (struct ath_hal *, 1372struct eeprom_ops eep_4k_ops = {
1966 struct ath9k_channel *, 1373 .check_eeprom = ath9k_hw_4k_check_eeprom,
1967 u16, u8, u8, u8) = { 1374 .get_eeprom = ath9k_hw_4k_get_eeprom,
1968 ath9k_hw_def_set_txpower, 1375 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1969 ath9k_hw_4k_set_txpower 1376 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1377 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1378 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1379 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1380 .set_board_values = ath9k_hw_4k_set_board_values,
1381 .set_addac = ath9k_hw_4k_set_addac,
1382 .set_txpower = ath9k_hw_4k_set_txpower,
1383 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1970}; 1384};
1971 1385
1972int ath9k_hw_set_txpower(struct ath_hal *ah, 1386/************************************************/
1973 struct ath9k_channel *chan, 1387/* EEPROM Operations for non-4K (Default) cards */
1974 u16 cfgCtl, 1388/************************************************/
1975 u8 twiceAntennaReduction, 1389
1976 u8 twiceMaxRegulatoryPower, 1390static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1977 u8 powerLimit)
1978{ 1391{
1979 struct ath_hal_5416 *ahp = AH5416(ah); 1392 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1393}
1980 1394
1981 return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl, 1395static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1982 twiceAntennaReduction, twiceMaxRegulatoryPower, 1396{
1983 powerLimit); 1397 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1984} 1398}
1985 1399
1986static void ath9k_hw_set_def_addac(struct ath_hal *ah, 1400static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1987 struct ath9k_channel *chan)
1988{ 1401{
1989#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 1402#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1990 struct modal_eep_header *pModal; 1403 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1991 struct ath_hal_5416 *ahp = AH5416(ah); 1404 u16 *eep_data;
1992 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; 1405 int addr, ar5416_eep_start_loc = 0x100;
1993 u8 biaslevel;
1994 1406
1995 if (ah->ah_macVersion != AR_SREV_VERSION_9160) 1407 eep_data = (u16 *)eep;
1996 return;
1997 1408
1998 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) 1409 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1999 return; 1410 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1411 eep_data)) {
1412 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1413 "Unable to read eeprom region\n");
1414 return false;
1415 }
1416 eep_data++;
1417 }
1418 return true;
1419#undef SIZE_EEPROM_DEF
1420}
2000 1421
2001 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 1422static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1423{
1424 struct ar5416_eeprom_def *eep =
1425 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1426 u16 *eepdata, temp, magic, magic2;
1427 u32 sum = 0, el;
1428 bool need_swap = false;
1429 int i, addr, size;
2002 1430
2003 if (pModal->xpaBiasLvl != 0xff) { 1431 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
2004 biaslevel = pModal->xpaBiasLvl; 1432 &magic)) {
2005 } else { 1433 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2006 u16 resetFreqBin, freqBin, freqCount = 0; 1434 "Reading Magic # failed\n");
2007 struct chan_centers centers; 1435 return false;
1436 }
2008 1437
2009 ath9k_hw_get_channel_centers(ah, chan, &centers); 1438 if (!ath9k_hw_use_flash(ah)) {
2010 1439
2011 resetFreqBin = FREQ2FBIN(centers.synth_center, 1440 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2012 IS_CHAN_2GHZ(chan)); 1441 "Read Magic = 0x%04X\n", magic);
2013 freqBin = XPA_LVL_FREQ(0) & 0xff;
2014 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
2015 1442
2016 freqCount++; 1443 if (magic != AR5416_EEPROM_MAGIC) {
1444 magic2 = swab16(magic);
2017 1445
2018 while (freqCount < 3) { 1446 if (magic2 == AR5416_EEPROM_MAGIC) {
2019 if (XPA_LVL_FREQ(freqCount) == 0x0) 1447 size = sizeof(struct ar5416_eeprom_def);
2020 break; 1448 need_swap = true;
1449 eepdata = (u16 *) (&ah->eeprom);
2021 1450
2022 freqBin = XPA_LVL_FREQ(freqCount) & 0xff; 1451 for (addr = 0; addr < size / sizeof(u16); addr++) {
2023 if (resetFreqBin >= freqBin) 1452 temp = swab16(*eepdata);
2024 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); 1453 *eepdata = temp;
2025 else 1454 eepdata++;
2026 break; 1455
2027 freqCount++; 1456 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1457 "0x%04X ", *eepdata);
1458
1459 if (((addr + 1) % 6) == 0)
1460 DPRINTF(ah->ah_sc,
1461 ATH_DBG_EEPROM, "\n");
1462 }
1463 } else {
1464 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1465 "Invalid EEPROM Magic. "
1466 "endianness mismatch.\n");
1467 return -EINVAL;
1468 }
2028 } 1469 }
2029 } 1470 }
2030 1471
2031 if (IS_CHAN_2GHZ(chan)) { 1472 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
2032 INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac, 1473 need_swap ? "True" : "False");
2033 7, 1) & (~0x18)) | biaslevel << 3;
2034 } else {
2035 INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac,
2036 6, 1) & (~0xc0)) | biaslevel << 6;
2037 }
2038#undef XPA_LVL_FREQ
2039}
2040 1474
2041static void ath9k_hw_set_4k_addac(struct ath_hal *ah, 1475 if (need_swap)
2042 struct ath9k_channel *chan) 1476 el = swab16(ah->eeprom.def.baseEepHeader.length);
2043{ 1477 else
2044 struct modal_eep_4k_header *pModal; 1478 el = ah->eeprom.def.baseEepHeader.length;
2045 struct ath_hal_5416 *ahp = AH5416(ah);
2046 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2047 u8 biaslevel;
2048 1479
2049 if (ah->ah_macVersion != AR_SREV_VERSION_9160) 1480 if (el > sizeof(struct ar5416_eeprom_def))
2050 return; 1481 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1482 else
1483 el = el / sizeof(u16);
2051 1484
2052 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) 1485 eepdata = (u16 *)(&ah->eeprom);
2053 return;
2054 1486
2055 pModal = &eep->modalHeader; 1487 for (i = 0; i < el; i++)
1488 sum ^= *eepdata++;
2056 1489
2057 if (pModal->xpaBiasLvl != 0xff) { 1490 if (need_swap) {
2058 biaslevel = pModal->xpaBiasLvl; 1491 u32 integer, j;
2059 INI_RA(&ahp->ah_iniAddac, 7, 1) = 1492 u16 word;
2060 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
2061 }
2062}
2063 1493
2064static void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = { 1494 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2065 ath9k_hw_set_def_addac, 1495 "EEPROM Endianness is not native.. Changing \n");
2066 ath9k_hw_set_4k_addac
2067};
2068 1496
2069void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) 1497 word = swab16(eep->baseEepHeader.length);
2070{ 1498 eep->baseEepHeader.length = word;
2071 struct ath_hal_5416 *ahp = AH5416(ah); 1499
1500 word = swab16(eep->baseEepHeader.checksum);
1501 eep->baseEepHeader.checksum = word;
1502
1503 word = swab16(eep->baseEepHeader.version);
1504 eep->baseEepHeader.version = word;
1505
1506 word = swab16(eep->baseEepHeader.regDmn[0]);
1507 eep->baseEepHeader.regDmn[0] = word;
1508
1509 word = swab16(eep->baseEepHeader.regDmn[1]);
1510 eep->baseEepHeader.regDmn[1] = word;
1511
1512 word = swab16(eep->baseEepHeader.rfSilent);
1513 eep->baseEepHeader.rfSilent = word;
1514
1515 word = swab16(eep->baseEepHeader.blueToothOptions);
1516 eep->baseEepHeader.blueToothOptions = word;
1517
1518 word = swab16(eep->baseEepHeader.deviceCap);
1519 eep->baseEepHeader.deviceCap = word;
1520
1521 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1522 struct modal_eep_header *pModal =
1523 &eep->modalHeader[j];
1524 integer = swab32(pModal->antCtrlCommon);
1525 pModal->antCtrlCommon = integer;
2072 1526
2073 ath9k_set_addac[ahp->ah_eep_map](ah, chan); 1527 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1528 integer = swab32(pModal->antCtrlChain[i]);
1529 pModal->antCtrlChain[i] = integer;
1530 }
1531
1532 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1533 word = swab16(pModal->spurChans[i].spurChan);
1534 pModal->spurChans[i].spurChan = word;
1535 }
1536 }
1537 }
1538
1539 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1540 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1541 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1542 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1543 sum, ah->eep_ops->get_eeprom_ver(ah));
1544 return -EINVAL;
1545 }
1546
1547 return 0;
2074} 1548}
2075 1549
1550static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1551 enum eeprom_param param)
1552{
1553#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
1554 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1555 struct modal_eep_header *pModal = eep->modalHeader;
1556 struct base_eep_header *pBase = &eep->baseEepHeader;
2076 1557
1558 switch (param) {
1559 case EEP_NFTHRESH_5:
1560 return pModal[0].noiseFloorThreshCh[0];
1561 case EEP_NFTHRESH_2:
1562 return pModal[1].noiseFloorThreshCh[0];
1563 case AR_EEPROM_MAC(0):
1564 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1565 case AR_EEPROM_MAC(1):
1566 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1567 case AR_EEPROM_MAC(2):
1568 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1569 case EEP_REG_0:
1570 return pBase->regDmn[0];
1571 case EEP_REG_1:
1572 return pBase->regDmn[1];
1573 case EEP_OP_CAP:
1574 return pBase->deviceCap;
1575 case EEP_OP_MODE:
1576 return pBase->opCapFlags;
1577 case EEP_RF_SILENT:
1578 return pBase->rfSilent;
1579 case EEP_OB_5:
1580 return pModal[0].ob;
1581 case EEP_DB_5:
1582 return pModal[0].db;
1583 case EEP_OB_2:
1584 return pModal[1].ob;
1585 case EEP_DB_2:
1586 return pModal[1].db;
1587 case EEP_MINOR_REV:
1588 return AR5416_VER_MASK;
1589 case EEP_TX_MASK:
1590 return pBase->txMask;
1591 case EEP_RX_MASK:
1592 return pBase->rxMask;
1593 case EEP_RXGAIN_TYPE:
1594 return pBase->rxGainType;
1595 case EEP_TXGAIN_TYPE:
1596 return pBase->txGainType;
1597 case EEP_DAC_HPWR_5G:
1598 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1599 return pBase->dacHiPwrMode_5G;
1600 else
1601 return 0;
1602 default:
1603 return 0;
1604 }
1605#undef AR5416_VER_MASK
1606}
2077 1607
2078/* XXX: Clean me up, make me more legible */ 1608/* XXX: Clean me up, make me more legible */
2079static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, 1609static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
2080 struct ath9k_channel *chan) 1610 struct ath9k_channel *chan)
2081{ 1611{
2082#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 1612#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
2083 struct modal_eep_header *pModal; 1613 struct modal_eep_header *pModal;
2084 struct ath_hal_5416 *ahp = AH5416(ah); 1614 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2085 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2086 int i, regChainOffset; 1615 int i, regChainOffset;
2087 u8 txRxAttenLocal; 1616 u8 txRxAttenLocal;
2088 1617
@@ -2091,7 +1620,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2091 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 1620 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
2092 1621
2093 REG_WRITE(ah, AR_PHY_SWITCH_COM, 1622 REG_WRITE(ah, AR_PHY_SWITCH_COM,
2094 ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); 1623 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
2095 1624
2096 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1625 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2097 if (AR_SREV_9280(ah)) { 1626 if (AR_SREV_9280(ah)) {
@@ -2100,7 +1629,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2100 } 1629 }
2101 1630
2102 if (AR_SREV_5416_V20_OR_LATER(ah) && 1631 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2103 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) 1632 (ah->rxchainmask == 5 || ah->txchainmask == 5)
2104 && (i != 0)) 1633 && (i != 0))
2105 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1634 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2106 else 1635 else
@@ -2321,253 +1850,778 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2321#undef AR5416_VER_MASK 1850#undef AR5416_VER_MASK
2322} 1851}
2323 1852
2324static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, 1853static void ath9k_hw_def_set_addac(struct ath_hw *ah,
2325 struct ath9k_channel *chan) 1854 struct ath9k_channel *chan)
2326{ 1855{
2327 struct modal_eep_4k_header *pModal; 1856#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
2328 struct ath_hal_5416 *ahp = AH5416(ah); 1857 struct modal_eep_header *pModal;
2329 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; 1858 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2330 int regChainOffset; 1859 u8 biaslevel;
2331 u8 txRxAttenLocal;
2332 u8 ob[5], db1[5], db2[5];
2333 u8 ant_div_control1, ant_div_control2;
2334 u32 regVal;
2335 1860
1861 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1862 return;
2336 1863
2337 pModal = &eep->modalHeader; 1864 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1865 return;
2338 1866
2339 txRxAttenLocal = 23; 1867 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2340 1868
2341 REG_WRITE(ah, AR_PHY_SWITCH_COM, 1869 if (pModal->xpaBiasLvl != 0xff) {
2342 ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); 1870 biaslevel = pModal->xpaBiasLvl;
1871 } else {
1872 u16 resetFreqBin, freqBin, freqCount = 0;
1873 struct chan_centers centers;
2343 1874
2344 regChainOffset = 0; 1875 ath9k_hw_get_channel_centers(ah, chan, &centers);
2345 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2346 pModal->antCtrlChain[0]);
2347 1876
2348 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 1877 resetFreqBin = FREQ2FBIN(centers.synth_center,
2349 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & 1878 IS_CHAN_2GHZ(chan));
2350 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 1879 freqBin = XPA_LVL_FREQ(0) & 0xff;
2351 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1880 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
2352 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
2353 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
2354 1881
2355 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1882 freqCount++;
2356 AR5416_EEP_MINOR_VER_3) {
2357 txRxAttenLocal = pModal->txRxAttenCh[0];
2358 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2359 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
2360 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2361 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
2362 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2363 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
2364 pModal->xatten2Margin[0]);
2365 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2366 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
2367 }
2368 1883
2369 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1884 while (freqCount < 3) {
2370 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1885 if (XPA_LVL_FREQ(freqCount) == 0x0)
2371 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1886 break;
2372 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
2373 1887
2374 if (AR_SREV_9285_11(ah)) 1888 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
2375 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 1889 if (resetFreqBin >= freqBin)
1890 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
1891 else
1892 break;
1893 freqCount++;
1894 }
1895 }
2376 1896
2377 /* Initialize Ant Diversity settings from EEPROM */ 1897 if (IS_CHAN_2GHZ(chan)) {
2378 if (pModal->version == 3) { 1898 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
2379 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); 1899 7, 1) & (~0x18)) | biaslevel << 3;
2380 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); 1900 } else {
2381 regVal = REG_READ(ah, 0x99ac); 1901 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
2382 regVal &= (~(0x7f000000)); 1902 6, 1) & (~0xc0)) | biaslevel << 6;
2383 regVal |= ((ant_div_control1 & 0x1) << 24);
2384 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
2385 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
2386 regVal |= ((ant_div_control2 & 0x3) << 25);
2387 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
2388 REG_WRITE(ah, 0x99ac, regVal);
2389 regVal = REG_READ(ah, 0x99ac);
2390 regVal = REG_READ(ah, 0xa208);
2391 regVal &= (~(0x1 << 13));
2392 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
2393 REG_WRITE(ah, 0xa208, regVal);
2394 regVal = REG_READ(ah, 0xa208);
2395 } 1903 }
1904#undef XPA_LVL_FREQ
1905}
2396 1906
2397 if (pModal->version >= 2) { 1907static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
2398 ob[0] = (pModal->ob_01 & 0xf); 1908 struct ath9k_channel *chan,
2399 ob[1] = (pModal->ob_01 >> 4) & 0xf; 1909 struct cal_data_per_freq *pRawDataSet,
2400 ob[2] = (pModal->ob_234 & 0xf); 1910 u8 *bChans, u16 availPiers,
2401 ob[3] = ((pModal->ob_234 >> 4) & 0xf); 1911 u16 tPdGainOverlap, int16_t *pMinCalPower,
2402 ob[4] = ((pModal->ob_234 >> 8) & 0xf); 1912 u16 *pPdGainBoundaries, u8 *pPDADCValues,
1913 u16 numXpdGains)
1914{
1915 int i, j, k;
1916 int16_t ss;
1917 u16 idxL = 0, idxR = 0, numPiers;
1918 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
1919 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1920 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
1921 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1922 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
1923 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2403 1924
2404 db1[0] = (pModal->db1_01 & 0xf); 1925 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2405 db1[1] = ((pModal->db1_01 >> 4) & 0xf); 1926 u8 minPwrT4[AR5416_NUM_PD_GAINS];
2406 db1[2] = (pModal->db1_234 & 0xf); 1927 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
2407 db1[3] = ((pModal->db1_234 >> 4) & 0xf); 1928 int16_t vpdStep;
2408 db1[4] = ((pModal->db1_234 >> 8) & 0xf); 1929 int16_t tmpVal;
1930 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
1931 bool match;
1932 int16_t minDelta = 0;
1933 struct chan_centers centers;
2409 1934
2410 db2[0] = (pModal->db2_01 & 0xf); 1935 ath9k_hw_get_channel_centers(ah, chan, &centers);
2411 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
2412 db2[2] = (pModal->db2_234 & 0xf);
2413 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
2414 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
2415 1936
2416 } else if (pModal->version == 1) { 1937 for (numPiers = 0; numPiers < availPiers; numPiers++) {
1938 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
1939 break;
1940 }
2417 1941
2418 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1942 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2419 "EEPROM Model version is set to 1 \n"); 1943 IS_CHAN_2GHZ(chan)),
2420 ob[0] = (pModal->ob_01 & 0xf); 1944 bChans, numPiers, &idxL, &idxR);
2421 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; 1945
2422 db1[0] = (pModal->db1_01 & 0xf); 1946 if (match) {
2423 db1[1] = db1[2] = db1[3] = 1947 for (i = 0; i < numXpdGains; i++) {
2424 db1[4] = ((pModal->db1_01 >> 4) & 0xf); 1948 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2425 db2[0] = (pModal->db2_01 & 0xf); 1949 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2426 db2[1] = db2[2] = db2[3] = 1950 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2427 db2[4] = ((pModal->db2_01 >> 4) & 0xf); 1951 pRawDataSet[idxL].pwrPdg[i],
1952 pRawDataSet[idxL].vpdPdg[i],
1953 AR5416_PD_GAIN_ICEPTS,
1954 vpdTableI[i]);
1955 }
2428 } else { 1956 } else {
2429 int i; 1957 for (i = 0; i < numXpdGains; i++) {
2430 for (i = 0; i < 5; i++) { 1958 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2431 ob[i] = pModal->ob_01; 1959 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2432 db1[i] = pModal->db1_01; 1960 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2433 db2[i] = pModal->db1_01; 1961 pPwrR = pRawDataSet[idxR].pwrPdg[i];
1962
1963 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
1964
1965 maxPwrT4[i] =
1966 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
1967 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
1968
1969
1970 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
1971 pPwrL, pVpdL,
1972 AR5416_PD_GAIN_ICEPTS,
1973 vpdTableL[i]);
1974 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
1975 pPwrR, pVpdR,
1976 AR5416_PD_GAIN_ICEPTS,
1977 vpdTableR[i]);
1978
1979 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
1980 vpdTableI[i][j] =
1981 (u8)(ath9k_hw_interpolate((u16)
1982 FREQ2FBIN(centers.
1983 synth_center,
1984 IS_CHAN_2GHZ
1985 (chan)),
1986 bChans[idxL], bChans[idxR],
1987 vpdTableL[i][j], vpdTableR[i][j]));
1988 }
2434 } 1989 }
2435 } 1990 }
2436 1991
2437 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, 1992 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2438 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
2439 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2440 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
2441 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2442 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
2443 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2444 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
2445 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2446 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
2447 1993
2448 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, 1994 k = 0;
2449 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
2450 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2451 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
2452 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2453 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
2454 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2455 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
2456 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2457 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
2458 1995
2459 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, 1996 for (i = 0; i < numXpdGains; i++) {
2460 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); 1997 if (i == (numXpdGains - 1))
2461 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, 1998 pPdGainBoundaries[i] =
2462 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); 1999 (u16)(maxPwrT4[i] / 2);
2463 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, 2000 else
2464 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); 2001 pPdGainBoundaries[i] =
2465 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, 2002 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2466 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
2467 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2468 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
2469 2003
2004 pPdGainBoundaries[i] =
2005 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2470 2006
2471 if (AR_SREV_9285_11(ah)) 2007 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
2472 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); 2008 minDelta = pPdGainBoundaries[0] - 23;
2009 pPdGainBoundaries[0] = 23;
2010 } else {
2011 minDelta = 0;
2012 }
2473 2013
2474 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 2014 if (i == 0) {
2475 pModal->switchSettling); 2015 if (AR_SREV_9280_10_OR_LATER(ah))
2476 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 2016 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2477 pModal->adcDesiredSize); 2017 else
2018 ss = 0;
2019 } else {
2020 ss = (int16_t)((pPdGainBoundaries[i - 1] -
2021 (minPwrT4[i] / 2)) -
2022 tPdGainOverlap + 1 + minDelta);
2023 }
2024 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2025 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2478 2026
2479 REG_WRITE(ah, AR_PHY_RF_CTL4, 2027 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2480 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 2028 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2481 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 2029 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2482 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 2030 ss++;
2483 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 2031 }
2484 2032
2485 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 2033 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2486 pModal->txEndToRxOn); 2034 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2487 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 2035 (minPwrT4[i] / 2));
2488 pModal->thresh62); 2036 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2489 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 2037 tgtIndex : sizeCurrVpdTable;
2490 pModal->thresh62);
2491 2038
2492 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 2039 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2493 AR5416_EEP_MINOR_VER_2) { 2040 pPDADCValues[k++] = vpdTableI[i][ss++];
2494 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, 2041 }
2495 pModal->txFrameToDataStart); 2042
2496 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, 2043 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2497 pModal->txFrameToPaOn); 2044 vpdTableI[i][sizeCurrVpdTable - 2]);
2045 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2046
2047 if (tgtIndex > maxIndex) {
2048 while ((ss <= tgtIndex) &&
2049 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2050 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2051 (ss - maxIndex + 1) * vpdStep));
2052 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2053 255 : tmpVal);
2054 ss++;
2055 }
2056 }
2498 } 2057 }
2499 2058
2500 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 2059 while (i < AR5416_PD_GAINS_IN_MASK) {
2501 AR5416_EEP_MINOR_VER_3) { 2060 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2502 if (IS_CHAN_HT40(chan)) 2061 i++;
2503 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2504 AR_PHY_SETTLING_SWITCH,
2505 pModal->swSettleHt40);
2506 } 2062 }
2507 2063
2508 return true; 2064 while (k < AR5416_NUM_PDADC_VALUES) {
2509} 2065 pPDADCValues[k] = pPDADCValues[k - 1];
2066 k++;
2067 }
2510 2068
2511static bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *, 2069 return;
2512 struct ath9k_channel *) = { 2070}
2513 ath9k_hw_eeprom_set_def_board_values,
2514 ath9k_hw_eeprom_set_4k_board_values
2515};
2516 2071
2517bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 2072static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2518 struct ath9k_channel *chan) 2073 struct ath9k_channel *chan,
2074 int16_t *pTxPowerIndexOffset)
2519{ 2075{
2520 struct ath_hal_5416 *ahp = AH5416(ah); 2076 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2077 struct cal_data_per_freq *pRawDataset;
2078 u8 *pCalBChans = NULL;
2079 u16 pdGainOverlap_t2;
2080 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2081 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2082 u16 numPiers, i, j;
2083 int16_t tMinCalPower;
2084 u16 numXpdGain, xpdMask;
2085 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2086 u32 reg32, regOffset, regChainOffset;
2087 int16_t modalIdx;
2521 2088
2522 return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan); 2089 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2523} 2090 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2524 2091
2525static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah, 2092 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2526 struct ath9k_channel *chan) 2093 AR5416_EEP_MINOR_VER_2) {
2527{ 2094 pdGainOverlap_t2 =
2528 struct ath_hal_5416 *ahp = AH5416(ah); 2095 pEepData->modalHeader[modalIdx].pdGainOverlap;
2529 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; 2096 } else {
2530 struct modal_eep_header *pModal = 2097 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2531 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 2098 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2099 }
2532 2100
2533 return pModal->antCtrlCommon & 0xFFFF; 2101 if (IS_CHAN_2GHZ(chan)) {
2102 pCalBChans = pEepData->calFreqPier2G;
2103 numPiers = AR5416_NUM_2G_CAL_PIERS;
2104 } else {
2105 pCalBChans = pEepData->calFreqPier5G;
2106 numPiers = AR5416_NUM_5G_CAL_PIERS;
2107 }
2108
2109 numXpdGain = 0;
2110
2111 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2112 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2113 if (numXpdGain >= AR5416_NUM_PD_GAINS)
2114 break;
2115 xpdGainValues[numXpdGain] =
2116 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2117 numXpdGain++;
2118 }
2119 }
2120
2121 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2122 (numXpdGain - 1) & 0x3);
2123 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2124 xpdGainValues[0]);
2125 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2126 xpdGainValues[1]);
2127 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2128 xpdGainValues[2]);
2129
2130 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2131 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2132 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2133 (i != 0)) {
2134 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2135 } else
2136 regChainOffset = i * 0x1000;
2137
2138 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2139 if (IS_CHAN_2GHZ(chan))
2140 pRawDataset = pEepData->calPierData2G[i];
2141 else
2142 pRawDataset = pEepData->calPierData5G[i];
2143
2144 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
2145 pRawDataset, pCalBChans,
2146 numPiers, pdGainOverlap_t2,
2147 &tMinCalPower, gainBoundaries,
2148 pdadcValues, numXpdGain);
2149
2150 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
2151 REG_WRITE(ah,
2152 AR_PHY_TPCRG5 + regChainOffset,
2153 SM(pdGainOverlap_t2,
2154 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
2155 | SM(gainBoundaries[0],
2156 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
2157 | SM(gainBoundaries[1],
2158 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
2159 | SM(gainBoundaries[2],
2160 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
2161 | SM(gainBoundaries[3],
2162 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
2163 }
2164
2165 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2166 for (j = 0; j < 32; j++) {
2167 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2168 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2169 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2170 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2171 REG_WRITE(ah, regOffset, reg32);
2172
2173 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2174 "PDADC (%d,%4x): %4.4x %8.8x\n",
2175 i, regChainOffset, regOffset,
2176 reg32);
2177 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2178 "PDADC: Chain %d | PDADC %3d "
2179 "Value %3d | PDADC %3d Value %3d | "
2180 "PDADC %3d Value %3d | PDADC %3d "
2181 "Value %3d |\n",
2182 i, 4 * j, pdadcValues[4 * j],
2183 4 * j + 1, pdadcValues[4 * j + 1],
2184 4 * j + 2, pdadcValues[4 * j + 2],
2185 4 * j + 3,
2186 pdadcValues[4 * j + 3]);
2187
2188 regOffset += 4;
2189 }
2190 }
2191 }
2192
2193 *pTxPowerIndexOffset = 0;
2194
2195 return true;
2534} 2196}
2535 2197
2536static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah, 2198static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2537 struct ath9k_channel *chan) 2199 struct ath9k_channel *chan,
2200 int16_t *ratesArray,
2201 u16 cfgCtl,
2202 u16 AntennaReduction,
2203 u16 twiceMaxRegulatoryPower,
2204 u16 powerLimit)
2538{ 2205{
2539 struct ath_hal_5416 *ahp = AH5416(ah); 2206#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2540 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; 2207#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2541 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2542 2208
2543 return pModal->antCtrlCommon & 0xFFFF; 2209 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2544} 2210 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2211 static const u16 tpScaleReductionTable[5] =
2212 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2545 2213
2546static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *, 2214 int i;
2547 struct ath9k_channel *) = { 2215 int16_t twiceLargestAntenna;
2548 ath9k_hw_get_def_eeprom_antenna_cfg, 2216 struct cal_ctl_data *rep;
2549 ath9k_hw_get_4k_eeprom_antenna_cfg 2217 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2550}; 2218 0, { 0, 0, 0, 0}
2219 };
2220 struct cal_target_power_leg targetPowerOfdmExt = {
2221 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2222 0, { 0, 0, 0, 0 }
2223 };
2224 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2225 0, {0, 0, 0, 0}
2226 };
2227 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2228 u16 ctlModesFor11a[] =
2229 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2230 u16 ctlModesFor11g[] =
2231 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2232 CTL_2GHT40
2233 };
2234 u16 numCtlModes, *pCtlMode, ctlMode, freq;
2235 struct chan_centers centers;
2236 int tx_chainmask;
2237 u16 twiceMinEdgePower;
2551 2238
2552u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, 2239 tx_chainmask = ah->txchainmask;
2553 struct ath9k_channel *chan) 2240
2554{ 2241 ath9k_hw_get_channel_centers(ah, chan, &centers);
2555 struct ath_hal_5416 *ahp = AH5416(ah); 2242
2243 twiceLargestAntenna = max(
2244 pEepData->modalHeader
2245 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2246 pEepData->modalHeader
2247 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2248
2249 twiceLargestAntenna = max((u8)twiceLargestAntenna,
2250 pEepData->modalHeader
2251 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2252
2253 twiceLargestAntenna = (int16_t)min(AntennaReduction -
2254 twiceLargestAntenna, 0);
2255
2256 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2257
2258 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2259 maxRegAllowedPower -=
2260 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2261 }
2262
2263 scaledPower = min(powerLimit, maxRegAllowedPower);
2264
2265 switch (ar5416_get_ntxchains(tx_chainmask)) {
2266 case 1:
2267 break;
2268 case 2:
2269 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2270 break;
2271 case 3:
2272 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2273 break;
2274 }
2275
2276 scaledPower = max((u16)0, scaledPower);
2277
2278 if (IS_CHAN_2GHZ(chan)) {
2279 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2280 SUB_NUM_CTL_MODES_AT_2G_40;
2281 pCtlMode = ctlModesFor11g;
2282
2283 ath9k_hw_get_legacy_target_powers(ah, chan,
2284 pEepData->calTargetPowerCck,
2285 AR5416_NUM_2G_CCK_TARGET_POWERS,
2286 &targetPowerCck, 4, false);
2287 ath9k_hw_get_legacy_target_powers(ah, chan,
2288 pEepData->calTargetPower2G,
2289 AR5416_NUM_2G_20_TARGET_POWERS,
2290 &targetPowerOfdm, 4, false);
2291 ath9k_hw_get_target_powers(ah, chan,
2292 pEepData->calTargetPower2GHT20,
2293 AR5416_NUM_2G_20_TARGET_POWERS,
2294 &targetPowerHt20, 8, false);
2295
2296 if (IS_CHAN_HT40(chan)) {
2297 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2298 ath9k_hw_get_target_powers(ah, chan,
2299 pEepData->calTargetPower2GHT40,
2300 AR5416_NUM_2G_40_TARGET_POWERS,
2301 &targetPowerHt40, 8, true);
2302 ath9k_hw_get_legacy_target_powers(ah, chan,
2303 pEepData->calTargetPowerCck,
2304 AR5416_NUM_2G_CCK_TARGET_POWERS,
2305 &targetPowerCckExt, 4, true);
2306 ath9k_hw_get_legacy_target_powers(ah, chan,
2307 pEepData->calTargetPower2G,
2308 AR5416_NUM_2G_20_TARGET_POWERS,
2309 &targetPowerOfdmExt, 4, true);
2310 }
2311 } else {
2312 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2313 SUB_NUM_CTL_MODES_AT_5G_40;
2314 pCtlMode = ctlModesFor11a;
2315
2316 ath9k_hw_get_legacy_target_powers(ah, chan,
2317 pEepData->calTargetPower5G,
2318 AR5416_NUM_5G_20_TARGET_POWERS,
2319 &targetPowerOfdm, 4, false);
2320 ath9k_hw_get_target_powers(ah, chan,
2321 pEepData->calTargetPower5GHT20,
2322 AR5416_NUM_5G_20_TARGET_POWERS,
2323 &targetPowerHt20, 8, false);
2324
2325 if (IS_CHAN_HT40(chan)) {
2326 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2327 ath9k_hw_get_target_powers(ah, chan,
2328 pEepData->calTargetPower5GHT40,
2329 AR5416_NUM_5G_40_TARGET_POWERS,
2330 &targetPowerHt40, 8, true);
2331 ath9k_hw_get_legacy_target_powers(ah, chan,
2332 pEepData->calTargetPower5G,
2333 AR5416_NUM_5G_20_TARGET_POWERS,
2334 &targetPowerOfdmExt, 4, true);
2335 }
2336 }
2337
2338 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2339 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2340 (pCtlMode[ctlMode] == CTL_2GHT40);
2341 if (isHt40CtlMode)
2342 freq = centers.synth_center;
2343 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2344 freq = centers.ext_center;
2345 else
2346 freq = centers.ctl_center;
2347
2348 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2349 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2350 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2351
2352 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2353 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2354 "EXT_ADDITIVE %d\n",
2355 ctlMode, numCtlModes, isHt40CtlMode,
2356 (pCtlMode[ctlMode] & EXT_ADDITIVE));
2357
2358 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2359 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2360 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2361 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2362 "chan %d\n",
2363 i, cfgCtl, pCtlMode[ctlMode],
2364 pEepData->ctlIndex[i], chan->channel);
2365
2366 if ((((cfgCtl & ~CTL_MODE_M) |
2367 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2368 pEepData->ctlIndex[i]) ||
2369 (((cfgCtl & ~CTL_MODE_M) |
2370 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2371 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2372 rep = &(pEepData->ctlData[i]);
2373
2374 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2375 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2376 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2377
2378 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2379 " MATCH-EE_IDX %d: ch %d is2 %d "
2380 "2xMinEdge %d chainmask %d chains %d\n",
2381 i, freq, IS_CHAN_2GHZ(chan),
2382 twiceMinEdgePower, tx_chainmask,
2383 ar5416_get_ntxchains
2384 (tx_chainmask));
2385 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2386 twiceMaxEdgePower = min(twiceMaxEdgePower,
2387 twiceMinEdgePower);
2388 } else {
2389 twiceMaxEdgePower = twiceMinEdgePower;
2390 break;
2391 }
2392 }
2393 }
2394
2395 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2396
2397 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2398 " SEL-Min ctlMode %d pCtlMode %d "
2399 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2400 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2401 scaledPower, minCtlPower);
2556 2402
2557 return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan); 2403 switch (pCtlMode[ctlMode]) {
2404 case CTL_11B:
2405 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2406 targetPowerCck.tPow2x[i] =
2407 min((u16)targetPowerCck.tPow2x[i],
2408 minCtlPower);
2409 }
2410 break;
2411 case CTL_11A:
2412 case CTL_11G:
2413 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2414 targetPowerOfdm.tPow2x[i] =
2415 min((u16)targetPowerOfdm.tPow2x[i],
2416 minCtlPower);
2417 }
2418 break;
2419 case CTL_5GHT20:
2420 case CTL_2GHT20:
2421 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2422 targetPowerHt20.tPow2x[i] =
2423 min((u16)targetPowerHt20.tPow2x[i],
2424 minCtlPower);
2425 }
2426 break;
2427 case CTL_11B_EXT:
2428 targetPowerCckExt.tPow2x[0] = min((u16)
2429 targetPowerCckExt.tPow2x[0],
2430 minCtlPower);
2431 break;
2432 case CTL_11A_EXT:
2433 case CTL_11G_EXT:
2434 targetPowerOfdmExt.tPow2x[0] = min((u16)
2435 targetPowerOfdmExt.tPow2x[0],
2436 minCtlPower);
2437 break;
2438 case CTL_5GHT40:
2439 case CTL_2GHT40:
2440 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2441 targetPowerHt40.tPow2x[i] =
2442 min((u16)targetPowerHt40.tPow2x[i],
2443 minCtlPower);
2444 }
2445 break;
2446 default:
2447 break;
2448 }
2449 }
2450
2451 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2452 ratesArray[rate18mb] = ratesArray[rate24mb] =
2453 targetPowerOfdm.tPow2x[0];
2454 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2455 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2456 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2457 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2458
2459 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2460 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2461
2462 if (IS_CHAN_2GHZ(chan)) {
2463 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2464 ratesArray[rate2s] = ratesArray[rate2l] =
2465 targetPowerCck.tPow2x[1];
2466 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2467 targetPowerCck.tPow2x[2];
2468 ;
2469 ratesArray[rate11s] = ratesArray[rate11l] =
2470 targetPowerCck.tPow2x[3];
2471 ;
2472 }
2473 if (IS_CHAN_HT40(chan)) {
2474 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2475 ratesArray[rateHt40_0 + i] =
2476 targetPowerHt40.tPow2x[i];
2477 }
2478 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2479 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2480 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2481 if (IS_CHAN_2GHZ(chan)) {
2482 ratesArray[rateExtCck] =
2483 targetPowerCckExt.tPow2x[0];
2484 }
2485 }
2486 return true;
2558} 2487}
2559 2488
2560static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah, 2489static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2561 enum ieee80211_band freq_band) 2490 struct ath9k_channel *chan,
2491 u16 cfgCtl,
2492 u8 twiceAntennaReduction,
2493 u8 twiceMaxRegulatoryPower,
2494 u8 powerLimit)
2562{ 2495{
2563 return 1; 2496 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2497 struct modal_eep_header *pModal =
2498 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2499 int16_t ratesArray[Ar5416RateSize];
2500 int16_t txPowerIndexOffset = 0;
2501 u8 ht40PowerIncForPdadc = 2;
2502 int i;
2503
2504 memset(ratesArray, 0, sizeof(ratesArray));
2505
2506 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2507 AR5416_EEP_MINOR_VER_2) {
2508 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2509 }
2510
2511 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
2512 &ratesArray[0], cfgCtl,
2513 twiceAntennaReduction,
2514 twiceMaxRegulatoryPower,
2515 powerLimit)) {
2516 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2517 "ath9k_hw_set_txpower: unable to set "
2518 "tx power per rate table\n");
2519 return -EIO;
2520 }
2521
2522 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
2523 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2524 "ath9k_hw_set_txpower: unable to set power table\n");
2525 return -EIO;
2526 }
2527
2528 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2529 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2530 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2531 ratesArray[i] = AR5416_MAX_RATE_POWER;
2532 }
2533
2534 if (AR_SREV_9280_10_OR_LATER(ah)) {
2535 for (i = 0; i < Ar5416RateSize; i++)
2536 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2537 }
2538
2539 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2540 ATH9K_POW_SM(ratesArray[rate18mb], 24)
2541 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2542 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2543 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2544 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2545 ATH9K_POW_SM(ratesArray[rate54mb], 24)
2546 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2547 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2548 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2549
2550 if (IS_CHAN_2GHZ(chan)) {
2551 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2552 ATH9K_POW_SM(ratesArray[rate2s], 24)
2553 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2554 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2555 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2556 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2557 ATH9K_POW_SM(ratesArray[rate11s], 24)
2558 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2559 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2560 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2561 }
2562
2563 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2564 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2565 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2566 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2567 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2568 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2569 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2570 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2571 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2572 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2573
2574 if (IS_CHAN_HT40(chan)) {
2575 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2576 ATH9K_POW_SM(ratesArray[rateHt40_3] +
2577 ht40PowerIncForPdadc, 24)
2578 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2579 ht40PowerIncForPdadc, 16)
2580 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2581 ht40PowerIncForPdadc, 8)
2582 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2583 ht40PowerIncForPdadc, 0));
2584 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2585 ATH9K_POW_SM(ratesArray[rateHt40_7] +
2586 ht40PowerIncForPdadc, 24)
2587 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2588 ht40PowerIncForPdadc, 16)
2589 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2590 ht40PowerIncForPdadc, 8)
2591 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2592 ht40PowerIncForPdadc, 0));
2593
2594 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2595 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2596 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
2597 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2598 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
2599 }
2600
2601 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2602 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
2603 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
2604
2605 i = rate6mb;
2606
2607 if (IS_CHAN_HT40(chan))
2608 i = rateHt40_0;
2609 else if (IS_CHAN_HT20(chan))
2610 i = rateHt20_0;
2611
2612 if (AR_SREV_9280_10_OR_LATER(ah))
2613 ah->regulatory.max_power_level =
2614 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2615 else
2616 ah->regulatory.max_power_level = ratesArray[i];
2617
2618 return 0;
2564} 2619}
2565 2620
2566static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, 2621static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2567 enum ieee80211_band freq_band) 2622 enum ieee80211_band freq_band)
2568{ 2623{
2569 struct ath_hal_5416 *ahp = AH5416(ah); 2624 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2570 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2571 struct modal_eep_header *pModal = 2625 struct modal_eep_header *pModal =
2572 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); 2626 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2573 struct base_eep_header *pBase = &eep->baseEepHeader; 2627 struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -2582,183 +2636,75 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah,
2582 return num_ant_config; 2636 return num_ant_config;
2583} 2637}
2584 2638
2585static u8 (*ath9k_get_num_ant_config[])(struct ath_hal *, 2639static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2586 enum ieee80211_band) = { 2640 struct ath9k_channel *chan)
2587 ath9k_hw_get_def_num_ant_config,
2588 ath9k_hw_get_4k_num_ant_config
2589};
2590
2591u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
2592 enum ieee80211_band freq_band)
2593{ 2641{
2594 struct ath_hal_5416 *ahp = AH5416(ah); 2642 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2643 struct modal_eep_header *pModal =
2644 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2595 2645
2596 return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band); 2646 return pModal->antCtrlCommon & 0xFFFF;
2597} 2647}
2598 2648
2599u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) 2649u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2600{ 2650{
2601#define EEP_MAP4K_SPURCHAN \
2602 (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan)
2603#define EEP_DEF_SPURCHAN \ 2651#define EEP_DEF_SPURCHAN \
2604 (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 2652 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2605 struct ath_hal_5416 *ahp = AH5416(ah); 2653
2606 u16 spur_val = AR_NO_SPUR; 2654 u16 spur_val = AR_NO_SPUR;
2607 2655
2608 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2656 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2609 "Getting spur idx %d is2Ghz. %d val %x\n", 2657 "Getting spur idx %d is2Ghz. %d val %x\n",
2610 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); 2658 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2611 2659
2612 switch (ah->ah_config.spurmode) { 2660 switch (ah->config.spurmode) {
2613 case SPUR_DISABLE: 2661 case SPUR_DISABLE:
2614 break; 2662 break;
2615 case SPUR_ENABLE_IOCTL: 2663 case SPUR_ENABLE_IOCTL:
2616 spur_val = ah->ah_config.spurchans[i][is2GHz]; 2664 spur_val = ah->config.spurchans[i][is2GHz];
2617 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2665 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2618 "Getting spur val from new loc. %d\n", spur_val); 2666 "Getting spur val from new loc. %d\n", spur_val);
2619 break; 2667 break;
2620 case SPUR_ENABLE_EEPROM: 2668 case SPUR_ENABLE_EEPROM:
2621 if (ahp->ah_eep_map == EEP_MAP_4KBITS) 2669 spur_val = EEP_DEF_SPURCHAN;
2622 spur_val = EEP_MAP4K_SPURCHAN;
2623 else
2624 spur_val = EEP_DEF_SPURCHAN;
2625 break; 2670 break;
2626
2627 } 2671 }
2628 2672
2629 return spur_val; 2673 return spur_val;
2630#undef EEP_DEF_SPURCHAN
2631#undef EEP_MAP4K_SPURCHAN
2632}
2633
2634static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
2635 enum eeprom_param param)
2636{
2637 struct ath_hal_5416 *ahp = AH5416(ah);
2638 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2639 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2640 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
2641
2642 switch (param) {
2643 case EEP_NFTHRESH_2:
2644 return pModal[1].noiseFloorThreshCh[0];
2645 case AR_EEPROM_MAC(0):
2646 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2647 case AR_EEPROM_MAC(1):
2648 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2649 case AR_EEPROM_MAC(2):
2650 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2651 case EEP_REG_0:
2652 return pBase->regDmn[0];
2653 case EEP_REG_1:
2654 return pBase->regDmn[1];
2655 case EEP_OP_CAP:
2656 return pBase->deviceCap;
2657 case EEP_OP_MODE:
2658 return pBase->opCapFlags;
2659 case EEP_RF_SILENT:
2660 return pBase->rfSilent;
2661 case EEP_OB_2:
2662 return pModal->ob_01;
2663 case EEP_DB_2:
2664 return pModal->db1_01;
2665 case EEP_MINOR_REV:
2666 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
2667 case EEP_TX_MASK:
2668 return pBase->txMask;
2669 case EEP_RX_MASK:
2670 return pBase->rxMask;
2671 default:
2672 return 0;
2673 }
2674}
2675
2676static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
2677 enum eeprom_param param)
2678{
2679#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
2680 struct ath_hal_5416 *ahp = AH5416(ah);
2681 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2682 struct modal_eep_header *pModal = eep->modalHeader;
2683 struct base_eep_header *pBase = &eep->baseEepHeader;
2684 2674
2685 switch (param) { 2675#undef EEP_DEF_SPURCHAN
2686 case EEP_NFTHRESH_5:
2687 return pModal[0].noiseFloorThreshCh[0];
2688 case EEP_NFTHRESH_2:
2689 return pModal[1].noiseFloorThreshCh[0];
2690 case AR_EEPROM_MAC(0):
2691 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2692 case AR_EEPROM_MAC(1):
2693 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2694 case AR_EEPROM_MAC(2):
2695 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2696 case EEP_REG_0:
2697 return pBase->regDmn[0];
2698 case EEP_REG_1:
2699 return pBase->regDmn[1];
2700 case EEP_OP_CAP:
2701 return pBase->deviceCap;
2702 case EEP_OP_MODE:
2703 return pBase->opCapFlags;
2704 case EEP_RF_SILENT:
2705 return pBase->rfSilent;
2706 case EEP_OB_5:
2707 return pModal[0].ob;
2708 case EEP_DB_5:
2709 return pModal[0].db;
2710 case EEP_OB_2:
2711 return pModal[1].ob;
2712 case EEP_DB_2:
2713 return pModal[1].db;
2714 case EEP_MINOR_REV:
2715 return AR5416_VER_MASK;
2716 case EEP_TX_MASK:
2717 return pBase->txMask;
2718 case EEP_RX_MASK:
2719 return pBase->rxMask;
2720 case EEP_RXGAIN_TYPE:
2721 return pBase->rxGainType;
2722 case EEP_TXGAIN_TYPE:
2723 return pBase->txGainType;
2724 case EEP_DAC_HPWR_5G:
2725 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
2726 return pBase->dacHiPwrMode_5G;
2727 else
2728 return 0;
2729 default:
2730 return 0;
2731 }
2732#undef AR5416_VER_MASK
2733} 2676}
2734 2677
2735static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = { 2678struct eeprom_ops eep_def_ops = {
2736 ath9k_hw_get_eeprom_def, 2679 .check_eeprom = ath9k_hw_def_check_eeprom,
2737 ath9k_hw_get_eeprom_4k 2680 .get_eeprom = ath9k_hw_def_get_eeprom,
2681 .fill_eeprom = ath9k_hw_def_fill_eeprom,
2682 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
2683 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
2684 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
2685 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
2686 .set_board_values = ath9k_hw_def_set_board_values,
2687 .set_addac = ath9k_hw_def_set_addac,
2688 .set_txpower = ath9k_hw_def_set_txpower,
2689 .get_spur_channel = ath9k_hw_def_get_spur_channel
2738}; 2690};
2739 2691
2740u32 ath9k_hw_get_eeprom(struct ath_hal *ah, 2692int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2741 enum eeprom_param param)
2742{
2743 struct ath_hal_5416 *ahp = AH5416(ah);
2744
2745 return ath9k_get_eeprom[ahp->ah_eep_map](ah, param);
2746}
2747
2748int ath9k_hw_eeprom_attach(struct ath_hal *ah)
2749{ 2693{
2750 int status; 2694 int status;
2751 struct ath_hal_5416 *ahp = AH5416(ah);
2752 2695
2753 if (AR_SREV_9285(ah)) 2696 if (AR_SREV_9285(ah)) {
2754 ahp->ah_eep_map = EEP_MAP_4KBITS; 2697 ah->eep_map = EEP_MAP_4KBITS;
2755 else 2698 ah->eep_ops = &eep_4k_ops;
2756 ahp->ah_eep_map = EEP_MAP_DEFAULT; 2699 } else {
2700 ah->eep_map = EEP_MAP_DEFAULT;
2701 ah->eep_ops = &eep_def_ops;
2702 }
2757 2703
2758 if (!ath9k_hw_fill_eeprom(ah)) 2704 if (!ah->eep_ops->fill_eeprom(ah))
2759 return -EIO; 2705 return -EIO;
2760 2706
2761 status = ath9k_hw_check_eeprom(ah); 2707 status = ah->eep_ops->check_eeprom(ah);
2762 2708
2763 return status; 2709 return status;
2764} 2710}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 10:44:06 -0500