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authorSujith <Sujith.Manoharan@atheros.com>2008-10-29 00:46:30 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-11-10 15:16:05 -0500
commitf1dc56003b23d2d5bb5a756de6b1633a76c9e697 (patch)
treef530aa716620322192bb0e7e083c903bf0e55544 /drivers/net/wireless/ath9k/ath9k.h
parent5640b08ef7e88b606c740e746cb77bc97d78508e (diff)
ath9k: Refactor hw.c
Split hw.c into more manageable files: ani.c calib.c eeprom.c mac.c Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/ath9k.h')
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h376
1 files changed, 216 insertions, 160 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index a6063dea0fa2..3a180ce1770b 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -828,195 +828,251 @@ struct chan_centers {
828 u16 ext_center; 828 u16 ext_center;
829}; 829};
830 830
831int ath_hal_getcapability(struct ath_hal *ah, 831/* Helpers */
832 enum ath9k_capability_type type, 832
833 u32 capability, 833enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
834 u32 *result); 834 const struct ath9k_channel *chan);
835const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, 835bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
836 u32 mode); 836u32 ath9k_hw_reverse_bits(u32 val, u32 n);
837void ath9k_hw_detach(struct ath_hal *ah); 837bool ath9k_get_channel_edges(struct ath_hal *ah,
838struct ath_hal *ath9k_hw_attach(u16 devid, 838 u16 flags, u16 *low,
839 struct ath_softc *sc, 839 u16 *high);
840 void __iomem *mem, 840u16 ath9k_hw_computetxtime(struct ath_hal *ah,
841 int *error); 841 const struct ath9k_rate_table *rates,
842bool ath9k_regd_init_channels(struct ath_hal *ah, 842 u32 frameLen, u16 rateix,
843 u32 maxchans, u32 *nchans, 843 bool shortPreamble);
844 u8 *regclassids,
845 u32 maxregids, u32 *nregids,
846 u16 cc,
847 bool enableOutdoor,
848 bool enableExtendedChannels);
849u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); 844u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
850enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, 845void ath9k_hw_get_channel_centers(struct ath_hal *ah,
851 enum ath9k_int ints); 846 struct ath9k_channel *chan,
852bool ath9k_hw_reset(struct ath_hal *ah, 847 struct chan_centers *centers);
853 struct ath9k_channel *chan, 848
849/* Attach, Detach */
850
851const char *ath9k_hw_probe(u16 vendorid, u16 devid);
852void ath9k_hw_detach(struct ath_hal *ah);
853struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
854 void __iomem *mem, int *error);
855void ath9k_hw_rfdetach(struct ath_hal *ah);
856
857
858/* HW Reset */
859
860bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
854 enum ath9k_ht_macmode macmode, 861 enum ath9k_ht_macmode macmode,
855 u8 txchainmask, u8 rxchainmask, 862 u8 txchainmask, u8 rxchainmask,
856 enum ath9k_ht_extprotspacing extprotspacing, 863 enum ath9k_ht_extprotspacing extprotspacing,
857 bool bChannelChange, 864 bool bChannelChange, int *status);
858 int *status); 865
859bool ath9k_hw_phy_disable(struct ath_hal *ah); 866/* Key Cache Management */
860void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, 867
861 bool *isCalDone);
862void ath9k_hw_ani_monitor(struct ath_hal *ah,
863 const struct ath9k_node_stats *stats,
864 struct ath9k_channel *chan);
865bool ath9k_hw_calibrate(struct ath_hal *ah,
866 struct ath9k_channel *chan,
867 u8 rxchainmask,
868 bool longcal,
869 bool *isCalDone);
870s16 ath9k_hw_getchan_noise(struct ath_hal *ah,
871 struct ath9k_channel *chan);
872void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
873 u16 assocId);
874void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
875void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
876 u16 assocId);
877bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
878void ath9k_hw_reset_tsf(struct ath_hal *ah);
879bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
880bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
881 const u8 *mac);
882bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
883 u16 entry,
884 const struct ath9k_keyval *k,
885 const u8 *mac,
886 int xorKey);
887bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
888 u32 setting);
889void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
890bool ath9k_hw_intrpend(struct ath_hal *ah);
891bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
892bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
893 bool bIncTrigLevel);
894void ath9k_hw_procmibevent(struct ath_hal *ah,
895 const struct ath9k_node_stats *stats);
896bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
897void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
898bool ath9k_hw_phycounters(struct ath_hal *ah);
899bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); 868bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
900bool ath9k_hw_getcapability(struct ath_hal *ah, 869bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
901 enum ath9k_capability_type type, 870bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
902 u32 capability, 871 const struct ath9k_keyval *k,
903 u32 *result); 872 const u8 *mac, int xorKey);
904bool ath9k_hw_setcapability(struct ath_hal *ah, 873bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
905 enum ath9k_capability_type type, 874
906 u32 capability, 875/* Power Management */
907 u32 setting, 876
908 int *status);
909u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
910void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
911void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
912bool ath9k_hw_setbssidmask(struct ath_hal *ah,
913 const u8 *mask);
914bool ath9k_hw_setpower(struct ath_hal *ah, 877bool ath9k_hw_setpower(struct ath_hal *ah,
915 enum ath9k_power_mode mode); 878 enum ath9k_power_mode mode);
916enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); 879void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
917u64 ath9k_hw_gettsf64(struct ath_hal *ah); 880
881/* Beacon timers */
882
883void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
884void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
885 const struct ath9k_beacon_state *bs);
886
887/* Rate table */
888
889const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
890 u32 mode);
891
892/* HW Capabilities */
893
894bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
895bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
896 u32 capability, u32 *result);
897bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
898 u32 capability, u32 setting, int *status);
899
900/* GPIO / RFKILL / Antennae */
901
902void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
903u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
904void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
905 u32 ah_signal_type);
906void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
907#ifdef CONFIG_RFKILL
908void ath9k_enable_rfkill(struct ath_hal *ah);
909#endif
910int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg);
918u32 ath9k_hw_getdefantenna(struct ath_hal *ah); 911u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
919bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); 912void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
920bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 913bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
921 enum ath9k_ant_setting settings, 914 enum ath9k_ant_setting settings,
922 struct ath9k_channel *chan, 915 struct ath9k_channel *chan,
923 u8 *tx_chainmask, 916 u8 *tx_chainmask,
924 u8 *rx_chainmask, 917 u8 *rx_chainmask,
925 u8 *antenna_cfgd); 918 u8 *antenna_cfgd);
926void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); 919
927int ath9k_hw_select_antconfig(struct ath_hal *ah, 920/* General Operation */
928 u32 cfg); 921
929bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, 922u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
930 u32 txdp); 923void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
924bool ath9k_hw_phy_disable(struct ath_hal *ah);
925bool ath9k_hw_disable(struct ath_hal *ah);
926bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
927void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
928bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
929void ath9k_hw_setopmode(struct ath_hal *ah);
930void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
931void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
932bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
933void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
934u64 ath9k_hw_gettsf64(struct ath_hal *ah);
935void ath9k_hw_reset_tsf(struct ath_hal *ah);
936bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
937bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
938void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
939
940/* Regulatory */
941
942bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
943struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah,
944 const struct ath9k_channel *c);
945u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
946u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
947 struct ath9k_channel *chan);
948bool ath9k_regd_init_channels(struct ath_hal *ah,
949 u32 maxchans, u32 *nchans, u8 *regclassids,
950 u32 maxregids, u32 *nregids, u16 cc,
951 bool enableOutdoor, bool enableExtendedChannels);
952
953/* ANI */
954
955void ath9k_ani_reset(struct ath_hal *ah);
956void ath9k_hw_ani_monitor(struct ath_hal *ah,
957 const struct ath9k_node_stats *stats,
958 struct ath9k_channel *chan);
959bool ath9k_hw_phycounters(struct ath_hal *ah);
960void ath9k_enable_mib_counters(struct ath_hal *ah);
961void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
962u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
963 u32 *rxc_pcnt,
964 u32 *rxf_pcnt,
965 u32 *txf_pcnt);
966void ath9k_hw_procmibevent(struct ath_hal *ah,
967 const struct ath9k_node_stats *stats);
968void ath9k_hw_ani_setup(struct ath_hal *ah);
969void ath9k_hw_ani_attach(struct ath_hal *ah);
970void ath9k_hw_ani_detach(struct ath_hal *ah);
971
972/* Calibration */
973
974void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
975 bool *isCalDone);
976void ath9k_hw_start_nfcal(struct ath_hal *ah);
977void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
978int16_t ath9k_hw_getnf(struct ath_hal *ah,
979 struct ath9k_channel *chan);
980void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
981s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
982bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
983 u8 rxchainmask, bool longcal,
984 bool *isCalDone);
985bool ath9k_hw_init_cal(struct ath_hal *ah,
986 struct ath9k_channel *chan);
987
988
989/* EEPROM */
990
991int ath9k_hw_set_txpower(struct ath_hal *ah,
992 struct ath9k_channel *chan,
993 u16 cfgCtl,
994 u8 twiceAntennaReduction,
995 u8 twiceMaxRegulatoryPower,
996 u8 powerLimit);
997void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
998bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
999 struct ath9k_channel *chan,
1000 int16_t *ratesArray,
1001 u16 cfgCtl,
1002 u8 AntennaReduction,
1003 u8 twiceMaxRegulatoryPower,
1004 u8 powerLimit);
1005bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
1006 struct ath9k_channel *chan,
1007 int16_t *pTxPowerIndexOffset);
1008bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
1009 struct ath9k_channel *chan);
1010int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
1011 struct ath9k_channel *chan,
1012 u8 index, u16 *config);
1013u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
1014 enum ieee80211_band freq_band);
1015u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
1016int ath9k_hw_eeprom_attach(struct ath_hal *ah);
1017
1018/* Interrupt Handling */
1019
1020bool ath9k_hw_intrpend(struct ath_hal *ah);
1021bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
1022enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
1023enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
1024
1025/* MAC (PCU/QCU) */
1026
1027void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1028u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1029bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
931bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); 1030bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
932u16 ath9k_hw_computetxtime(struct ath_hal *ah, 1031u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
933 const struct ath9k_rate_table *rates, 1032bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
934 u32 frameLen, u16 rateix, 1033bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
935 bool shortPreamble); 1034bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1035 u32 segLen, bool firstSeg,
1036 bool lastSeg, const struct ath_desc *ds0);
1037void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1038int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1039void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1040 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1041 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
936void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, 1042void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
937 struct ath_desc *lastds, 1043 struct ath_desc *lastds,
938 u32 durUpdateEn, u32 rtsctsRate, 1044 u32 durUpdateEn, u32 rtsctsRate,
939 u32 rtsctsDuration, 1045 u32 rtsctsDuration,
940 struct ath9k_11n_rate_series series[], 1046 struct ath9k_11n_rate_series series[],
941 u32 nseries, u32 flags); 1047 u32 nseries, u32 flags);
942void ath9k_hw_set11n_burstduration(struct ath_hal *ah, 1048void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
943 struct ath_desc *ds, 1049 u32 aggrLen);
1050void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1051 u32 numDelims);
1052void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1053void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1054void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
944 u32 burstDuration); 1055 u32 burstDuration);
945void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); 1056void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
946u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1057 u32 vmf);
947bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); 1058void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
948u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
949u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
950 struct ath9k_channel *chan);
951u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
952bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
953 struct ath9k_tx_queue_info *qinfo);
954bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 1059bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
955 const struct ath9k_tx_queue_info *qinfo); 1060 const struct ath9k_tx_queue_info *qinfo);
956struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah, 1061bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
957 const struct ath9k_channel *c); 1062 struct ath9k_tx_queue_info *qinfo);
958void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, 1063int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
959 u32 pktLen, enum ath9k_pkt_type type, 1064 const struct ath9k_tx_queue_info *qinfo);
960 u32 txPower, u32 keyIx, 1065bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
961 enum ath9k_key_type keyType, u32 flags); 1066bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
962bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 1067int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
963 u32 segLen, bool firstSeg, 1068 u32 pa, struct ath_desc *nds, u64 tsf);
964 bool lastSeg,
965 const struct ath_desc *ds0);
966u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
967 u32 *rxc_pcnt,
968 u32 *rxf_pcnt,
969 u32 *txf_pcnt);
970void ath9k_hw_dmaRegDump(struct ath_hal *ah);
971void ath9k_hw_beaconinit(struct ath_hal *ah,
972 u32 next_beacon, u32 beacon_period);
973void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
974 const struct ath9k_beacon_state *bs);
975bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, 1069bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
976 u32 size, u32 flags); 1070 u32 size, u32 flags);
1071bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
977void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); 1072void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
978void ath9k_hw_rxena(struct ath_hal *ah); 1073void ath9k_hw_rxena(struct ath_hal *ah);
979void ath9k_hw_setopmode(struct ath_hal *ah);
980bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
981void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
982 u32 filter1);
983u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
984void ath9k_hw_startpcureceive(struct ath_hal *ah); 1074void ath9k_hw_startpcureceive(struct ath_hal *ah);
985void ath9k_hw_stoppcurecv(struct ath_hal *ah); 1075void ath9k_hw_stoppcurecv(struct ath_hal *ah);
986bool ath9k_hw_stopdmarecv(struct ath_hal *ah); 1076bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
987int ath9k_hw_rxprocdesc(struct ath_hal *ah, 1077
988 struct ath_desc *ds, u32 pa,
989 struct ath_desc *nds, u64 tsf);
990u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
991int ath9k_hw_txprocdesc(struct ath_hal *ah,
992 struct ath_desc *ds);
993void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
994 u32 numDelims);
995void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
996 u32 aggrLen);
997void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
998bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
999void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1000void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1001void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1002 struct ath_desc *ds, u32 vmf);
1003bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1004bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1005int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1006 const struct ath9k_tx_queue_info *qinfo);
1007u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1008const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1009bool ath9k_hw_disable(struct ath_hal *ah);
1010void ath9k_hw_rfdetach(struct ath_hal *ah);
1011void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1012 struct ath9k_channel *chan,
1013 struct chan_centers *centers);
1014bool ath9k_get_channel_edges(struct ath_hal *ah,
1015 u16 flags, u16 *low,
1016 u16 *high);
1017void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
1018 u32 ah_signal_type);
1019void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);
1020u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
1021void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
1022#endif 1078#endif