Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

Conflicts:
	drivers/net/igb/igb_main.c
	drivers/net/qlge/qlge_main.c
	drivers/net/wireless/ath9k/ath9k.h
	drivers/net/wireless/ath9k/core.h
	drivers/net/wireless/ath9k/hw.c

1 files changed, 33 insertions, 0 deletions

diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index f0b105a11ae2..b64be8e9a690 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -579,6 +579,7 @@ struct ath_softc {
         void __iomem *mem;
         int irq;
         spinlock_t sc_resetlock;
+        spinlock_t sc_serial_rw;
         struct mutex mutex;
 
         u8 curbssid[ETH_ALEN];
@@ -724,4 +725,36 @@ void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 void ath9k_wiphy_work(struct work_struct *work);
 
+/*
+ * Read and write, they both share the same lock. We do this to serialize
+ * reads and writes on Atheros 802.11n PCI devices only. This is required
+ * as the FIFO on these devices can only accept sanely 2 requests. After
+ * that the device goes bananas. Serializing the reads/writes prevents this
+ * from happening.
+ */
+
+static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
+{
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
+                unsigned long flags;
+                spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
+                iowrite32(val, ah->ah_sc->mem + reg_offset);
+                spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
+        } else
+                iowrite32(val, ah->ah_sc->mem + reg_offset);
+}
+
+static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
+{
+        u32 val;
+        if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
+                unsigned long flags;
+                spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
+                val = ioread32(ah->ah_sc->mem + reg_offset);
+                spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
+        } else
+                val = ioread32(ah->ah_sc->mem + reg_offset);
+        return val;
+}
+
 #endif /* ATH9K_H */