diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2008-11-28 11:48:05 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-12-05 09:35:08 -0500 |
commit | 04bd4638097c767278fdf12d50fecc8b60194d39 (patch) | |
tree | 8bad1080889360aa06ffc967bb2625eecd3db26e /drivers/net/wireless/ath9k/ani.c | |
parent | d9a1f48648edbe99fa432626ce6964a1b58f7281 (diff) |
ath9k: Use cleaner debug masks
Remove all the useless __func__ prefixes in debug messages,
and replace the DPRINTF macro with a function.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/ani.c')
-rw-r--r-- | drivers/net/wireless/ath9k/ani.c | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index ada12e9aa7f9..c25b72be1139 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c | |||
@@ -53,8 +53,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
53 | 53 | ||
54 | if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { | 54 | if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { |
55 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 55 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
56 | "%s: level out of range (%u > %u)\n", | 56 | "level out of range (%u > %u)\n", |
57 | __func__, level, | 57 | level, |
58 | (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); | 58 | (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); |
59 | return false; | 59 | return false; |
60 | } | 60 | } |
@@ -158,8 +158,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
158 | 158 | ||
159 | if (level >= ARRAY_SIZE(firstep)) { | 159 | if (level >= ARRAY_SIZE(firstep)) { |
160 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 160 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
161 | "%s: level out of range (%u > %u)\n", | 161 | "level out of range (%u > %u)\n", |
162 | __func__, level, | 162 | level, |
163 | (unsigned) ARRAY_SIZE(firstep)); | 163 | (unsigned) ARRAY_SIZE(firstep)); |
164 | return false; | 164 | return false; |
165 | } | 165 | } |
@@ -180,8 +180,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
180 | 180 | ||
181 | if (level >= ARRAY_SIZE(cycpwrThr1)) { | 181 | if (level >= ARRAY_SIZE(cycpwrThr1)) { |
182 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 182 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
183 | "%s: level out of range (%u > %u)\n", | 183 | "level out of range (%u > %u)\n", |
184 | __func__, level, | 184 | level, |
185 | (unsigned) | 185 | (unsigned) |
186 | ARRAY_SIZE(cycpwrThr1)); | 186 | ARRAY_SIZE(cycpwrThr1)); |
187 | return false; | 187 | return false; |
@@ -200,11 +200,11 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, | |||
200 | break; | 200 | break; |
201 | default: | 201 | default: |
202 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 202 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
203 | "%s: invalid cmd %u\n", __func__, cmd); | 203 | "invalid cmd %u\n", cmd); |
204 | return false; | 204 | return false; |
205 | } | 205 | } |
206 | 206 | ||
207 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__); | 207 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n"); |
208 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 208 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
209 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, " | 209 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, " |
210 | "ofdmWeakSigDetectOff=%d\n", | 210 | "ofdmWeakSigDetectOff=%d\n", |
@@ -262,8 +262,8 @@ static void ath9k_ani_restart(struct ath_hal *ah) | |||
262 | AR_PHY_COUNTMAX - aniState->cckTrigHigh; | 262 | AR_PHY_COUNTMAX - aniState->cckTrigHigh; |
263 | } | 263 | } |
264 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 264 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
265 | "%s: Writing ofdmbase=%u cckbase=%u\n", | 265 | "Writing ofdmbase=%u cckbase=%u\n", |
266 | __func__, aniState->ofdmPhyErrBase, | 266 | aniState->ofdmPhyErrBase, |
267 | aniState->cckPhyErrBase); | 267 | aniState->cckPhyErrBase); |
268 | REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); | 268 | REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); |
269 | REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); | 269 | REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); |
@@ -490,8 +490,7 @@ void ath9k_ani_reset(struct ath_hal *ah) | |||
490 | if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA | 490 | if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA |
491 | && ah->ah_opmode != ATH9K_M_IBSS) { | 491 | && ah->ah_opmode != ATH9K_M_IBSS) { |
492 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 492 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
493 | "%s: Reset ANI state opmode %u\n", __func__, | 493 | "Reset ANI state opmode %u\n", ah->ah_opmode); |
494 | ah->ah_opmode); | ||
495 | ahp->ah_stats.ast_ani_reset++; | 494 | ahp->ah_stats.ast_ani_reset++; |
496 | 495 | ||
497 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); | 496 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); |
@@ -581,9 +580,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, | |||
581 | phyCnt2 < aniState->cckPhyErrBase) { | 580 | phyCnt2 < aniState->cckPhyErrBase) { |
582 | if (phyCnt1 < aniState->ofdmPhyErrBase) { | 581 | if (phyCnt1 < aniState->ofdmPhyErrBase) { |
583 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 582 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
584 | "%s: phyCnt1 0x%x, resetting " | 583 | "phyCnt1 0x%x, resetting " |
585 | "counter value to 0x%x\n", | 584 | "counter value to 0x%x\n", |
586 | __func__, phyCnt1, | 585 | phyCnt1, |
587 | aniState->ofdmPhyErrBase); | 586 | aniState->ofdmPhyErrBase); |
588 | REG_WRITE(ah, AR_PHY_ERR_1, | 587 | REG_WRITE(ah, AR_PHY_ERR_1, |
589 | aniState->ofdmPhyErrBase); | 588 | aniState->ofdmPhyErrBase); |
@@ -592,9 +591,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, | |||
592 | } | 591 | } |
593 | if (phyCnt2 < aniState->cckPhyErrBase) { | 592 | if (phyCnt2 < aniState->cckPhyErrBase) { |
594 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | 593 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, |
595 | "%s: phyCnt2 0x%x, resetting " | 594 | "phyCnt2 0x%x, resetting " |
596 | "counter value to 0x%x\n", | 595 | "counter value to 0x%x\n", |
597 | __func__, phyCnt2, | 596 | phyCnt2, |
598 | aniState->cckPhyErrBase); | 597 | aniState->cckPhyErrBase); |
599 | REG_WRITE(ah, AR_PHY_ERR_2, | 598 | REG_WRITE(ah, AR_PHY_ERR_2, |
600 | aniState->cckPhyErrBase); | 599 | aniState->cckPhyErrBase); |
@@ -692,8 +691,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | |||
692 | 691 | ||
693 | if (cycles == 0 || cycles > cc) { | 692 | if (cycles == 0 || cycles > cc) { |
694 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | 693 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, |
695 | "%s: cycle counter wrap. ExtBusy = 0\n", | 694 | "cycle counter wrap. ExtBusy = 0\n"); |
696 | __func__); | ||
697 | good = 0; | 695 | good = 0; |
698 | } else { | 696 | } else { |
699 | u32 cc_d = cc - cycles; | 697 | u32 cc_d = cc - cycles; |