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authorNick Kossifidis <mick@madwifi-project.org>2009-02-08 23:00:34 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:44:42 -0500
commit33a31826b4fe9f26d6b383bad19b7ae522fda006 (patch)
treee0cd44187c8362f3fe9402f752508df559c6d5b9 /drivers/net/wireless/ath5k/phy.c
parent7b08b3b4a973de20d28d8a322c002c0a5444002a (diff)
ath5k: PHY code cleanup
* Clean up initial rf buffer settings (new file rfbufer.h) and introduce a new way to access specific rf registers (will use it later) * Clean up initial rf gain settings by moving them on a new file (rfgain.h) so we can later work on gain optimization functions * Update initial rf buffer settings and initial rf gain settings from HALs. This breaks things for now because our current dumps come from pre-configured rf buffer (regdumps already had the needed values set from binary HAL). Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath5k/phy.c')
-rw-r--r--drivers/net/wireless/ath5k/phy.c1171
1 files changed, 38 insertions, 1133 deletions
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index 7ba18e09463b..5021749a439e 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -2,7 +2,7 @@
2 * PHY functions 2 * PHY functions
3 * 3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
@@ -26,1084 +26,8 @@
26#include "ath5k.h" 26#include "ath5k.h"
27#include "reg.h" 27#include "reg.h"
28#include "base.h" 28#include "base.h"
29 29#include "rfbuffer.h"
30/* Struct to hold initial RF register values (RF Banks) */ 30#include "rfgain.h"
31struct ath5k_ini_rf {
32 u8 rf_bank; /* check out ath5k_reg.h */
33 u16 rf_register; /* register address */
34 u32 rf_value[5]; /* register value for different modes (above) */
35};
36
37/*
38 * Mode-specific RF Gain table (64bytes) for RF5111/5112
39 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
40 * RF Gain values are included in AR5K_AR5210_INI)
41 */
42struct ath5k_ini_rfgain {
43 u16 rfg_register; /* RF Gain register address */
44 u32 rfg_value[2]; /* [freq (see below)] */
45};
46
47struct ath5k_gain_opt {
48 u32 go_default;
49 u32 go_steps_count;
50 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
51};
52
53/* RF5111 mode-specific init registers */
54static const struct ath5k_ini_rf rfregs_5111[] = {
55 { 0, 0x989c,
56 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58 { 0, 0x989c,
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60 { 0, 0x989c,
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62 { 0, 0x989c,
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64 { 0, 0x989c,
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66 { 0, 0x989c,
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68 { 0, 0x989c,
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70 { 0, 0x989c,
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72 { 0, 0x989c,
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74 { 0, 0x989c,
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76 { 0, 0x989c,
77 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
78 { 0, 0x989c,
79 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
80 { 0, 0x989c,
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82 { 0, 0x989c,
83 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
84 { 0, 0x989c,
85 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
86 { 0, 0x989c,
87 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
88 { 0, 0x98d4,
89 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
90 { 1, 0x98d4,
91 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
92 { 2, 0x98d4,
93 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
94 { 3, 0x98d8,
95 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
96 { 6, 0x989c,
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98 { 6, 0x989c,
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100 { 6, 0x989c,
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102 { 6, 0x989c,
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104 { 6, 0x989c,
105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
106 { 6, 0x989c,
107 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
108 { 6, 0x989c,
109 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
110 { 6, 0x989c,
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112 { 6, 0x989c,
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114 { 6, 0x989c,
115 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
116 { 6, 0x989c,
117 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
118 { 6, 0x989c,
119 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
120 { 6, 0x989c,
121 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
122 { 6, 0x989c,
123 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
124 { 6, 0x989c,
125 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
126 { 6, 0x989c,
127 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
128 { 6, 0x98d4,
129 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
130 { 7, 0x989c,
131 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
132 { 7, 0x989c,
133 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
134 { 7, 0x989c,
135 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
136 { 7, 0x989c,
137 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
138 { 7, 0x989c,
139 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
140 { 7, 0x989c,
141 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
142 { 7, 0x989c,
143 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
144 { 7, 0x98cc,
145 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
146};
147
148/* Initial RF Gain settings for RF5111 */
149static const struct ath5k_ini_rfgain rfgain_5111[] = {
150 /* 5Ghz 2Ghz */
151 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
152 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
153 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
154 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
155 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
156 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
157 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
158 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
159 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
160 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
161 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
162 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
163 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
164 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
165 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
166 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
167 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
168 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
169 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
170 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
171 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
172 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
173 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
174 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
175 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
176 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
177 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
178 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
179 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
180 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
181 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
182 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
183 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
184 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
185 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
186 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
187 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
188 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
189 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
190 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
191 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
192 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
193 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
194 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
195 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
196 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
197 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
198 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
199 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
200 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
201 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
213 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
214 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
215};
216
217static const struct ath5k_gain_opt rfgain_opt_5111 = {
218 4,
219 9,
220 {
221 { { 4, 1, 1, 1 }, 6 },
222 { { 4, 0, 1, 1 }, 4 },
223 { { 3, 1, 1, 1 }, 3 },
224 { { 4, 0, 0, 1 }, 1 },
225 { { 4, 1, 1, 0 }, 0 },
226 { { 4, 0, 1, 0 }, -2 },
227 { { 3, 1, 1, 0 }, -3 },
228 { { 4, 0, 0, 0 }, -4 },
229 { { 2, 1, 1, 0 }, -6 }
230 }
231};
232
233/* RF5112 mode-specific init registers */
234static const struct ath5k_ini_rf rfregs_5112[] = {
235 { 1, 0x98d4,
236 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
237 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
238 { 2, 0x98d0,
239 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
240 { 3, 0x98dc,
241 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
242 { 6, 0x989c,
243 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
244 { 6, 0x989c,
245 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
246 { 6, 0x989c,
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248 { 6, 0x989c,
249 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
250 { 6, 0x989c,
251 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
252 { 6, 0x989c,
253 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
254 { 6, 0x989c,
255 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
256 { 6, 0x989c,
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258 { 6, 0x989c,
259 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
260 { 6, 0x989c,
261 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
262 { 6, 0x989c,
263 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
264 { 6, 0x989c,
265 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
266 { 6, 0x989c,
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268 { 6, 0x989c,
269 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
270 { 6, 0x989c,
271 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
272 { 6, 0x989c,
273 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
274 { 6, 0x989c,
275 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
276 { 6, 0x989c,
277 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
278 { 6, 0x989c,
279 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
280 { 6, 0x989c,
281 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
282 { 6, 0x989c,
283 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
284 { 6, 0x989c,
285 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
286 { 6, 0x989c,
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288 { 6, 0x989c,
289 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
290 { 6, 0x989c,
291 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
292 { 6, 0x989c,
293 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
294 { 6, 0x989c,
295 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
296 { 6, 0x989c,
297 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
298 { 6, 0x989c,
299 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
300 { 6, 0x989c,
301 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
302 { 6, 0x989c,
303 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
304 { 6, 0x989c,
305 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
306 { 6, 0x989c,
307 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
308 { 6, 0x989c,
309 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
310 { 6, 0x989c,
311 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
312 { 6, 0x989c,
313 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
314 { 6, 0x989c,
315 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
316 { 6, 0x98d0,
317 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
318 { 7, 0x989c,
319 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
320 { 7, 0x989c,
321 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
322 { 7, 0x989c,
323 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
324 { 7, 0x989c,
325 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
326 { 7, 0x989c,
327 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
328 { 7, 0x989c,
329 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
330 { 7, 0x989c,
331 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
332 { 7, 0x989c,
333 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
334 { 7, 0x989c,
335 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
336 { 7, 0x989c,
337 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
338 { 7, 0x989c,
339 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
340 { 7, 0x989c,
341 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
342 { 7, 0x98c4,
343 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
344};
345
346/* RF5112A mode-specific init registers */
347static const struct ath5k_ini_rf rfregs_5112a[] = {
348 { 1, 0x98d4,
349 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
350 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
351 { 2, 0x98d0,
352 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
353 { 3, 0x98dc,
354 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
355 { 6, 0x989c,
356 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
357 { 6, 0x989c,
358 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
359 { 6, 0x989c,
360 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
361 { 6, 0x989c,
362 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
363 { 6, 0x989c,
364 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
365 { 6, 0x989c,
366 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
367 { 6, 0x989c,
368 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
369 { 6, 0x989c,
370 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
371 { 6, 0x989c,
372 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
373 { 6, 0x989c,
374 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
375 { 6, 0x989c,
376 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
377 { 6, 0x989c,
378 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
379 { 6, 0x989c,
380 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
381 { 6, 0x989c,
382 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
383 { 6, 0x989c,
384 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
385 { 6, 0x989c,
386 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
387 { 6, 0x989c,
388 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
389 { 6, 0x989c,
390 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
391 { 6, 0x989c,
392 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
393 { 6, 0x989c,
394 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
395 { 6, 0x989c,
396 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
397 { 6, 0x989c,
398 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
399 { 6, 0x989c,
400 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
401 { 6, 0x989c,
402 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
403 { 6, 0x989c,
404 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
405 { 6, 0x989c,
406 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
407 { 6, 0x989c,
408 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
409 { 6, 0x989c,
410 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
411 { 6, 0x989c,
412 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
413 { 6, 0x989c,
414 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
415 { 6, 0x989c,
416 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
417 { 6, 0x989c,
418 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
419 { 6, 0x989c,
420 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
421 { 6, 0x989c,
422 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
423 { 6, 0x989c,
424 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
425 { 6, 0x989c,
426 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
427 { 6, 0x989c,
428 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
429 { 6, 0x989c,
430 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
431 { 6, 0x989c,
432 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
433 { 6, 0x98d8,
434 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
435 { 7, 0x989c,
436 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
437 { 7, 0x989c,
438 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
439 { 7, 0x989c,
440 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
441 { 7, 0x989c,
442 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
443 { 7, 0x989c,
444 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
445 { 7, 0x989c,
446 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
447 { 7, 0x989c,
448 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
449 { 7, 0x989c,
450 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
451 { 7, 0x989c,
452 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
453 { 7, 0x989c,
454 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
455 { 7, 0x989c,
456 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
457 { 7, 0x989c,
458 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
459 { 7, 0x98c4,
460 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
461};
462
463
464static const struct ath5k_ini_rf rfregs_2112a[] = {
465 { 1, AR5K_RF_BUFFER_CONTROL_4,
466 /* mode b mode g mode gTurbo */
467 { 0x00000020, 0x00000020, 0x00000020 } },
468 { 2, AR5K_RF_BUFFER_CONTROL_3,
469 { 0x03060408, 0x03060408, 0x03070408 } },
470 { 3, AR5K_RF_BUFFER_CONTROL_6,
471 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
472 { 6, AR5K_RF_BUFFER,
473 { 0x0a000000, 0x0a000000, 0x0a000000 } },
474 { 6, AR5K_RF_BUFFER,
475 { 0x00000000, 0x00000000, 0x00000000 } },
476 { 6, AR5K_RF_BUFFER,
477 { 0x00800000, 0x00800000, 0x00800000 } },
478 { 6, AR5K_RF_BUFFER,
479 { 0x002a0000, 0x002a0000, 0x002a0000 } },
480 { 6, AR5K_RF_BUFFER,
481 { 0x00010000, 0x00010000, 0x00010000 } },
482 { 6, AR5K_RF_BUFFER,
483 { 0x00000000, 0x00000000, 0x00000000 } },
484 { 6, AR5K_RF_BUFFER,
485 { 0x00180000, 0x00180000, 0x00180000 } },
486 { 6, AR5K_RF_BUFFER,
487 { 0x006e0000, 0x006e0000, 0x006e0000 } },
488 { 6, AR5K_RF_BUFFER,
489 { 0x00c70000, 0x00c70000, 0x00c70000 } },
490 { 6, AR5K_RF_BUFFER,
491 { 0x004b0000, 0x004b0000, 0x004b0000 } },
492 { 6, AR5K_RF_BUFFER,
493 { 0x04480000, 0x04480000, 0x04480000 } },
494 { 6, AR5K_RF_BUFFER,
495 { 0x002a0000, 0x002a0000, 0x002a0000 } },
496 { 6, AR5K_RF_BUFFER,
497 { 0x00e40000, 0x00e40000, 0x00e40000 } },
498 { 6, AR5K_RF_BUFFER,
499 { 0x00000000, 0x00000000, 0x00000000 } },
500 { 6, AR5K_RF_BUFFER,
501 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
502 { 6, AR5K_RF_BUFFER,
503 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
504 { 6, AR5K_RF_BUFFER,
505 { 0x043f0000, 0x043f0000, 0x043f0000 } },
506 { 6, AR5K_RF_BUFFER,
507 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
508 { 6, AR5K_RF_BUFFER,
509 { 0x02190000, 0x02190000, 0x02190000 } },
510 { 6, AR5K_RF_BUFFER,
511 { 0x00240000, 0x00240000, 0x00240000 } },
512 { 6, AR5K_RF_BUFFER,
513 { 0x00b40000, 0x00b40000, 0x00b40000 } },
514 { 6, AR5K_RF_BUFFER,
515 { 0x00990000, 0x00990000, 0x00990000 } },
516 { 6, AR5K_RF_BUFFER,
517 { 0x00500000, 0x00500000, 0x00500000 } },
518 { 6, AR5K_RF_BUFFER,
519 { 0x002a0000, 0x002a0000, 0x002a0000 } },
520 { 6, AR5K_RF_BUFFER,
521 { 0x00120000, 0x00120000, 0x00120000 } },
522 { 6, AR5K_RF_BUFFER,
523 { 0xc0320000, 0xc0320000, 0xc0320000 } },
524 { 6, AR5K_RF_BUFFER,
525 { 0x01740000, 0x01740000, 0x01740000 } },
526 { 6, AR5K_RF_BUFFER,
527 { 0x00110000, 0x00110000, 0x00110000 } },
528 { 6, AR5K_RF_BUFFER,
529 { 0x86280000, 0x86280000, 0x86280000 } },
530 { 6, AR5K_RF_BUFFER,
531 { 0x31840000, 0x31840000, 0x31840000 } },
532 { 6, AR5K_RF_BUFFER,
533 { 0x00f20080, 0x00f20080, 0x00f20080 } },
534 { 6, AR5K_RF_BUFFER,
535 { 0x00070019, 0x00070019, 0x00070019 } },
536 { 6, AR5K_RF_BUFFER,
537 { 0x00000000, 0x00000000, 0x00000000 } },
538 { 6, AR5K_RF_BUFFER,
539 { 0x00000000, 0x00000000, 0x00000000 } },
540 { 6, AR5K_RF_BUFFER,
541 { 0x000000b2, 0x000000b2, 0x000000b2 } },
542 { 6, AR5K_RF_BUFFER,
543 { 0x00b02184, 0x00b02184, 0x00b02184 } },
544 { 6, AR5K_RF_BUFFER,
545 { 0x004125a4, 0x004125a4, 0x004125a4 } },
546 { 6, AR5K_RF_BUFFER,
547 { 0x00119220, 0x00119220, 0x00119220 } },
548 { 6, AR5K_RF_BUFFER,
549 { 0x001a4800, 0x001a4800, 0x001a4800 } },
550 { 6, AR5K_RF_BUFFER_CONTROL_5,
551 { 0x000b0230, 0x000b0230, 0x000b0230 } },
552 { 7, AR5K_RF_BUFFER,
553 { 0x00000094, 0x00000094, 0x00000094 } },
554 { 7, AR5K_RF_BUFFER,
555 { 0x00000091, 0x00000091, 0x00000091 } },
556 { 7, AR5K_RF_BUFFER,
557 { 0x00000012, 0x00000012, 0x00000012 } },
558 { 7, AR5K_RF_BUFFER,
559 { 0x00000080, 0x00000080, 0x00000080 } },
560 { 7, AR5K_RF_BUFFER,
561 { 0x000000d9, 0x000000d9, 0x000000d9 } },
562 { 7, AR5K_RF_BUFFER,
563 { 0x00000060, 0x00000060, 0x00000060 } },
564 { 7, AR5K_RF_BUFFER,
565 { 0x000000f0, 0x000000f0, 0x000000f0 } },
566 { 7, AR5K_RF_BUFFER,
567 { 0x000000a2, 0x000000a2, 0x000000a2 } },
568 { 7, AR5K_RF_BUFFER,
569 { 0x00000052, 0x00000052, 0x00000052 } },
570 { 7, AR5K_RF_BUFFER,
571 { 0x000000d4, 0x000000d4, 0x000000d4 } },
572 { 7, AR5K_RF_BUFFER,
573 { 0x000014cc, 0x000014cc, 0x000014cc } },
574 { 7, AR5K_RF_BUFFER,
575 { 0x0000048c, 0x0000048c, 0x0000048c } },
576 { 7, AR5K_RF_BUFFER_CONTROL_1,
577 { 0x00000003, 0x00000003, 0x00000003 } },
578};
579
580/* RF5413/5414 mode-specific init registers */
581static const struct ath5k_ini_rf rfregs_5413[] = {
582 { 1, 0x98d4,
583 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
584 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
585 { 2, 0x98d0,
586 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
587 { 3, 0x98dc,
588 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
589 { 6, 0x989c,
590 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
591 { 6, 0x989c,
592 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
593 { 6, 0x989c,
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595 { 6, 0x989c,
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597 { 6, 0x989c,
598 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
599 { 6, 0x989c,
600 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
601 { 6, 0x989c,
602 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
603 { 6, 0x989c,
604 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
605 { 6, 0x989c,
606 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
607 { 6, 0x989c,
608 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
609 { 6, 0x989c,
610 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
611 { 6, 0x989c,
612 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
613 { 6, 0x989c,
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615 { 6, 0x989c,
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617 { 6, 0x989c,
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619 { 6, 0x989c,
620 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
621 { 6, 0x989c,
622 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
623 { 6, 0x989c,
624 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
625 { 6, 0x989c,
626 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
627 { 6, 0x989c,
628 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
629 { 6, 0x989c,
630 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
631 { 6, 0x989c,
632 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
633 { 6, 0x989c,
634 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
635 { 6, 0x989c,
636 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
637 { 6, 0x989c,
638 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
639 { 6, 0x989c,
640 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
641 { 6, 0x989c,
642 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
643 { 6, 0x989c,
644 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
645 { 6, 0x989c,
646 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
647 { 6, 0x989c,
648 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
649 { 6, 0x989c,
650 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
651 { 6, 0x989c,
652 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
653 { 6, 0x989c,
654 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
655 { 6, 0x989c,
656 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
657 { 6, 0x989c,
658 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
659 { 6, 0x989c,
660 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
661 { 6, 0x98c8,
662 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
663 { 7, 0x989c,
664 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
665 { 7, 0x989c,
666 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
667 { 7, 0x98cc,
668 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
669};
670
671/* RF2413/2414 mode-specific init registers */
672static const struct ath5k_ini_rf rfregs_2413[] = {
673 { 1, AR5K_RF_BUFFER_CONTROL_4,
674 /* mode b mode g mode gTurbo */
675 { 0x00000020, 0x00000020, 0x00000020 } },
676 { 2, AR5K_RF_BUFFER_CONTROL_3,
677 { 0x02001408, 0x02001408, 0x02001408 } },
678 { 3, AR5K_RF_BUFFER_CONTROL_6,
679 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
680 { 6, AR5K_RF_BUFFER,
681 { 0xf0000000, 0xf0000000, 0xf0000000 } },
682 { 6, AR5K_RF_BUFFER,
683 { 0x00000000, 0x00000000, 0x00000000 } },
684 { 6, AR5K_RF_BUFFER,
685 { 0x03000000, 0x03000000, 0x03000000 } },
686 { 6, AR5K_RF_BUFFER,
687 { 0x00000000, 0x00000000, 0x00000000 } },
688 { 6, AR5K_RF_BUFFER,
689 { 0x00000000, 0x00000000, 0x00000000 } },
690 { 6, AR5K_RF_BUFFER,
691 { 0x00000000, 0x00000000, 0x00000000 } },
692 { 6, AR5K_RF_BUFFER,
693 { 0x00000000, 0x00000000, 0x00000000 } },
694 { 6, AR5K_RF_BUFFER,
695 { 0x00000000, 0x00000000, 0x00000000 } },
696 { 6, AR5K_RF_BUFFER,
697 { 0x40400000, 0x40400000, 0x40400000 } },
698 { 6, AR5K_RF_BUFFER,
699 { 0x65050000, 0x65050000, 0x65050000 } },
700 { 6, AR5K_RF_BUFFER,
701 { 0x00000000, 0x00000000, 0x00000000 } },
702 { 6, AR5K_RF_BUFFER,
703 { 0x00000000, 0x00000000, 0x00000000 } },
704 { 6, AR5K_RF_BUFFER,
705 { 0x00420000, 0x00420000, 0x00420000 } },
706 { 6, AR5K_RF_BUFFER,
707 { 0x00b50000, 0x00b50000, 0x00b50000 } },
708 { 6, AR5K_RF_BUFFER,
709 { 0x00030000, 0x00030000, 0x00030000 } },
710 { 6, AR5K_RF_BUFFER,
711 { 0x00f70000, 0x00f70000, 0x00f70000 } },
712 { 6, AR5K_RF_BUFFER,
713 { 0x009d0000, 0x009d0000, 0x009d0000 } },
714 { 6, AR5K_RF_BUFFER,
715 { 0x00220000, 0x00220000, 0x00220000 } },
716 { 6, AR5K_RF_BUFFER,
717 { 0x04220000, 0x04220000, 0x04220000 } },
718 { 6, AR5K_RF_BUFFER,
719 { 0x00230018, 0x00230018, 0x00230018 } },
720 { 6, AR5K_RF_BUFFER,
721 { 0x00280050, 0x00280050, 0x00280050 } },
722 { 6, AR5K_RF_BUFFER,
723 { 0x005000c3, 0x005000c3, 0x005000c3 } },
724 { 6, AR5K_RF_BUFFER,
725 { 0x0004007f, 0x0004007f, 0x0004007f } },
726 { 6, AR5K_RF_BUFFER,
727 { 0x00000458, 0x00000458, 0x00000458 } },
728 { 6, AR5K_RF_BUFFER,
729 { 0x00000000, 0x00000000, 0x00000000 } },
730 { 6, AR5K_RF_BUFFER,
731 { 0x0000c000, 0x0000c000, 0x0000c000 } },
732 { 6, AR5K_RF_BUFFER_CONTROL_5,
733 { 0x00400230, 0x00400230, 0x00400230 } },
734 { 7, AR5K_RF_BUFFER,
735 { 0x00006400, 0x00006400, 0x00006400 } },
736 { 7, AR5K_RF_BUFFER,
737 { 0x00000800, 0x00000800, 0x00000800 } },
738 { 7, AR5K_RF_BUFFER_CONTROL_2,
739 { 0x0000000e, 0x0000000e, 0x0000000e } },
740};
741
742/* RF2425 mode-specific init registers */
743static const struct ath5k_ini_rf rfregs_2425[] = {
744 { 1, AR5K_RF_BUFFER_CONTROL_4,
745 /* mode g mode gTurbo */
746 { 0x00000020, 0x00000020 } },
747 { 2, AR5K_RF_BUFFER_CONTROL_3,
748 { 0x02001408, 0x02001408 } },
749 { 3, AR5K_RF_BUFFER_CONTROL_6,
750 { 0x00e020c0, 0x00e020c0 } },
751 { 6, AR5K_RF_BUFFER,
752 { 0x10000000, 0x10000000 } },
753 { 6, AR5K_RF_BUFFER,
754 { 0x00000000, 0x00000000 } },
755 { 6, AR5K_RF_BUFFER,
756 { 0x00000000, 0x00000000 } },
757 { 6, AR5K_RF_BUFFER,
758 { 0x00000000, 0x00000000 } },
759 { 6, AR5K_RF_BUFFER,
760 { 0x00000000, 0x00000000 } },
761 { 6, AR5K_RF_BUFFER,
762 { 0x00000000, 0x00000000 } },
763 { 6, AR5K_RF_BUFFER,
764 { 0x00000000, 0x00000000 } },
765 { 6, AR5K_RF_BUFFER,
766 { 0x00000000, 0x00000000 } },
767 { 6, AR5K_RF_BUFFER,
768 { 0x00000000, 0x00000000 } },
769 { 6, AR5K_RF_BUFFER,
770 { 0x00000000, 0x00000000 } },
771 { 6, AR5K_RF_BUFFER,
772 { 0x00000000, 0x00000000 } },
773 { 6, AR5K_RF_BUFFER,
774 { 0x002a0000, 0x002a0000 } },
775 { 6, AR5K_RF_BUFFER,
776 { 0x00000000, 0x00000000 } },
777 { 6, AR5K_RF_BUFFER,
778 { 0x00000000, 0x00000000 } },
779 { 6, AR5K_RF_BUFFER,
780 { 0x00100000, 0x00100000 } },
781 { 6, AR5K_RF_BUFFER,
782 { 0x00020000, 0x00020000 } },
783 { 6, AR5K_RF_BUFFER,
784 { 0x00730000, 0x00730000 } },
785 { 6, AR5K_RF_BUFFER,
786 { 0x00f80000, 0x00f80000 } },
787 { 6, AR5K_RF_BUFFER,
788 { 0x00e70000, 0x00e70000 } },
789 { 6, AR5K_RF_BUFFER,
790 { 0x00140000, 0x00140000 } },
791 { 6, AR5K_RF_BUFFER,
792 { 0x00910040, 0x00910040 } },
793 { 6, AR5K_RF_BUFFER,
794 { 0x0007001a, 0x0007001a } },
795 { 6, AR5K_RF_BUFFER,
796 { 0x00410000, 0x00410000 } },
797 { 6, AR5K_RF_BUFFER,
798 { 0x00810060, 0x00810060 } },
799 { 6, AR5K_RF_BUFFER,
800 { 0x00020803, 0x00020803 } },
801 { 6, AR5K_RF_BUFFER,
802 { 0x00000000, 0x00000000 } },
803 { 6, AR5K_RF_BUFFER,
804 { 0x00000000, 0x00000000 } },
805 { 6, AR5K_RF_BUFFER,
806 { 0x00001660, 0x00001660 } },
807 { 6, AR5K_RF_BUFFER,
808 { 0x00001688, 0x00001688 } },
809 { 6, AR5K_RF_BUFFER_CONTROL_1,
810 { 0x00000001, 0x00000001 } },
811 { 7, AR5K_RF_BUFFER,
812 { 0x00006400, 0x00006400 } },
813 { 7, AR5K_RF_BUFFER,
814 { 0x00000800, 0x00000800 } },
815 { 7, AR5K_RF_BUFFER_CONTROL_2,
816 { 0x0000000e, 0x0000000e } },
817};
818
819/* Initial RF Gain settings for RF5112 */
820static const struct ath5k_ini_rfgain rfgain_5112[] = {
821 /* 5Ghz 2Ghz */
822 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
823 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
824 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
825 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
826 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
827 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
828 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
829 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
830 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
831 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
832 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
833 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
834 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
835 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
836 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
837 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
838 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
839 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
840 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
841 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
842 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
843 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
844 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
845 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
846 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
847 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
848 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
849 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
850 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
851 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
852 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
853 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
854 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
855 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
856 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
857 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
858 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
859 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
860 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
861 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
862 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
863 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
864 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
865 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
866 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
867 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
868 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
869 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
870 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
871 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
872 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
873 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
874 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
875 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
876 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
877 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
878 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
879 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
880 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
881 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
882 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
883 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
884 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
885 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
886};
887
888/* Initial RF Gain settings for RF5413 */
889static const struct ath5k_ini_rfgain rfgain_5413[] = {
890 /* 5Ghz 2Ghz */
891 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
892 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
893 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
894 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
895 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
896 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
897 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
898 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
899 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
900 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
901 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
902 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
903 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
904 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
905 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
906 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
907 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
908 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
909 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
910 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
911 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
912 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
913 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
914 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
915 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
916 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
917 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
918 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
919 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
920 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
921 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
922 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
923 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
924 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
925 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
926 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
927 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
928 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
929 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
930 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
931 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
932 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
933 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
934 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
935 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
936 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
937 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
938 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
939 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
940 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
941 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
942 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
943 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
944 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
945 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
946 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
947 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
948 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
949 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
950 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
951 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
952 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
953 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
954 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
955};
956
957/* Initial RF Gain settings for RF2413 */
958static const struct ath5k_ini_rfgain rfgain_2413[] = {
959 { AR5K_RF_GAIN(0), { 0x00000000 } },
960 { AR5K_RF_GAIN(1), { 0x00000040 } },
961 { AR5K_RF_GAIN(2), { 0x00000080 } },
962 { AR5K_RF_GAIN(3), { 0x00000181 } },
963 { AR5K_RF_GAIN(4), { 0x000001c1 } },
964 { AR5K_RF_GAIN(5), { 0x00000001 } },
965 { AR5K_RF_GAIN(6), { 0x00000041 } },
966 { AR5K_RF_GAIN(7), { 0x00000081 } },
967 { AR5K_RF_GAIN(8), { 0x00000168 } },
968 { AR5K_RF_GAIN(9), { 0x000001a8 } },
969 { AR5K_RF_GAIN(10), { 0x000001e8 } },
970 { AR5K_RF_GAIN(11), { 0x00000028 } },
971 { AR5K_RF_GAIN(12), { 0x00000068 } },
972 { AR5K_RF_GAIN(13), { 0x00000189 } },
973 { AR5K_RF_GAIN(14), { 0x000001c9 } },
974 { AR5K_RF_GAIN(15), { 0x00000009 } },
975 { AR5K_RF_GAIN(16), { 0x00000049 } },
976 { AR5K_RF_GAIN(17), { 0x00000089 } },
977 { AR5K_RF_GAIN(18), { 0x00000190 } },
978 { AR5K_RF_GAIN(19), { 0x000001d0 } },
979 { AR5K_RF_GAIN(20), { 0x00000010 } },
980 { AR5K_RF_GAIN(21), { 0x00000050 } },
981 { AR5K_RF_GAIN(22), { 0x00000090 } },
982 { AR5K_RF_GAIN(23), { 0x00000191 } },
983 { AR5K_RF_GAIN(24), { 0x000001d1 } },
984 { AR5K_RF_GAIN(25), { 0x00000011 } },
985 { AR5K_RF_GAIN(26), { 0x00000051 } },
986 { AR5K_RF_GAIN(27), { 0x00000091 } },
987 { AR5K_RF_GAIN(28), { 0x00000178 } },
988 { AR5K_RF_GAIN(29), { 0x000001b8 } },
989 { AR5K_RF_GAIN(30), { 0x000001f8 } },
990 { AR5K_RF_GAIN(31), { 0x00000038 } },
991 { AR5K_RF_GAIN(32), { 0x00000078 } },
992 { AR5K_RF_GAIN(33), { 0x00000199 } },
993 { AR5K_RF_GAIN(34), { 0x000001d9 } },
994 { AR5K_RF_GAIN(35), { 0x00000019 } },
995 { AR5K_RF_GAIN(36), { 0x00000059 } },
996 { AR5K_RF_GAIN(37), { 0x00000099 } },
997 { AR5K_RF_GAIN(38), { 0x000000d9 } },
998 { AR5K_RF_GAIN(39), { 0x000000f9 } },
999 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1000 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1001 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1002 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1003 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1004 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1005 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1006 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1007 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1008 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1009 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1010 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1011 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1012 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1013 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1014 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1015 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1016 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1017 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1018 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1019 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1020 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1021 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1022 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1023};
1024
1025/* Initial RF Gain settings for RF2425 */
1026static const struct ath5k_ini_rfgain rfgain_2425[] = {
1027 { AR5K_RF_GAIN(0), { 0x00000000 } },
1028 { AR5K_RF_GAIN(1), { 0x00000040 } },
1029 { AR5K_RF_GAIN(2), { 0x00000080 } },
1030 { AR5K_RF_GAIN(3), { 0x00000181 } },
1031 { AR5K_RF_GAIN(4), { 0x000001c1 } },
1032 { AR5K_RF_GAIN(5), { 0x00000001 } },
1033 { AR5K_RF_GAIN(6), { 0x00000041 } },
1034 { AR5K_RF_GAIN(7), { 0x00000081 } },
1035 { AR5K_RF_GAIN(8), { 0x00000188 } },
1036 { AR5K_RF_GAIN(9), { 0x000001c8 } },
1037 { AR5K_RF_GAIN(10), { 0x00000008 } },
1038 { AR5K_RF_GAIN(11), { 0x00000048 } },
1039 { AR5K_RF_GAIN(12), { 0x00000088 } },
1040 { AR5K_RF_GAIN(13), { 0x00000189 } },
1041 { AR5K_RF_GAIN(14), { 0x000001c9 } },
1042 { AR5K_RF_GAIN(15), { 0x00000009 } },
1043 { AR5K_RF_GAIN(16), { 0x00000049 } },
1044 { AR5K_RF_GAIN(17), { 0x00000089 } },
1045 { AR5K_RF_GAIN(18), { 0x000001b0 } },
1046 { AR5K_RF_GAIN(19), { 0x000001f0 } },
1047 { AR5K_RF_GAIN(20), { 0x00000030 } },
1048 { AR5K_RF_GAIN(21), { 0x00000070 } },
1049 { AR5K_RF_GAIN(22), { 0x00000171 } },
1050 { AR5K_RF_GAIN(23), { 0x000001b1 } },
1051 { AR5K_RF_GAIN(24), { 0x000001f1 } },
1052 { AR5K_RF_GAIN(25), { 0x00000031 } },
1053 { AR5K_RF_GAIN(26), { 0x00000071 } },
1054 { AR5K_RF_GAIN(27), { 0x000001b8 } },
1055 { AR5K_RF_GAIN(28), { 0x000001f8 } },
1056 { AR5K_RF_GAIN(29), { 0x00000038 } },
1057 { AR5K_RF_GAIN(30), { 0x00000078 } },
1058 { AR5K_RF_GAIN(31), { 0x000000b8 } },
1059 { AR5K_RF_GAIN(32), { 0x000001b9 } },
1060 { AR5K_RF_GAIN(33), { 0x000001f9 } },
1061 { AR5K_RF_GAIN(34), { 0x00000039 } },
1062 { AR5K_RF_GAIN(35), { 0x00000079 } },
1063 { AR5K_RF_GAIN(36), { 0x000000b9 } },
1064 { AR5K_RF_GAIN(37), { 0x000000f9 } },
1065 { AR5K_RF_GAIN(38), { 0x000000f9 } },
1066 { AR5K_RF_GAIN(39), { 0x000000f9 } },
1067 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1068 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1069 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1070 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1071 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1072 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1073 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1074 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1075 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1076 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1077 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1078 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1079 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1080 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1081 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1082 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1083 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1084 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1085 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1086 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1087 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1088 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1089 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1090 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1091};
1092
1093static const struct ath5k_gain_opt rfgain_opt_5112 = {
1094 1,
1095 8,
1096 {
1097 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1098 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1099 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1100 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1101 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1102 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1103 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1104 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1105 }
1106};
1107 31
1108/* 32/*
1109 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
@@ -1297,7 +221,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1297{ 221{
1298 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 222 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1299 u32 *rf; 223 u32 *rf;
1300 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111); 224 const unsigned int rf_size = ARRAY_SIZE(rfb_5111);
1301 unsigned int i; 225 unsigned int i;
1302 int obdb = -1, bank = -1; 226 int obdb = -1, bank = -1;
1303 u32 ee_mode; 227 u32 ee_mode;
@@ -1308,17 +232,17 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1308 232
1309 /* Copy values to modify them */ 233 /* Copy values to modify them */
1310 for (i = 0; i < rf_size; i++) { 234 for (i = 0; i < rf_size; i++) {
1311 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) { 235 if (rfb_5111[i].rfb_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1312 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 236 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1313 return -EINVAL; 237 return -EINVAL;
1314 } 238 }
1315 239
1316 if (bank != rfregs_5111[i].rf_bank) { 240 if (bank != rfb_5111[i].rfb_bank) {
1317 bank = rfregs_5111[i].rf_bank; 241 bank = rfb_5111[i].rfb_bank;
1318 ah->ah_offset[bank] = i; 242 ah->ah_offset[bank] = i;
1319 } 243 }
1320 244
1321 rf[i] = rfregs_5111[i].rf_value[mode]; 245 rf[i] = rfb_5111[i].rfb_mode_data[mode];
1322 } 246 }
1323 247
1324 /* Modify bank 0 */ 248 /* Modify bank 0 */
@@ -1384,7 +308,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1384 /* Write RF values */ 308 /* Write RF values */
1385 for (i = 0; i < rf_size; i++) { 309 for (i = 0; i < rf_size; i++) {
1386 AR5K_REG_WAIT(i); 310 AR5K_REG_WAIT(i);
1387 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register); 311 ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
1388 } 312 }
1389 313
1390 return 0; 314 return 0;
@@ -1396,7 +320,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1396static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah, 320static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1397 struct ieee80211_channel *channel, unsigned int mode) 321 struct ieee80211_channel *channel, unsigned int mode)
1398{ 322{
1399 const struct ath5k_ini_rf *rf_ini; 323 const struct ath5k_ini_rfbuffer *rf_ini;
1400 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 324 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1401 u32 *rf; 325 u32 *rf;
1402 unsigned int rf_size, i; 326 unsigned int rf_size, i;
@@ -1407,37 +331,27 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1407 331
1408 rf = ah->ah_rf_banks; 332 rf = ah->ah_rf_banks;
1409 333
1410 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A 334 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1411 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 335 rf_ini = rfb_5112a;
1412 rf_ini = rfregs_2112a; 336 rf_size = ARRAY_SIZE(rfb_5112a);
1413 rf_size = ARRAY_SIZE(rfregs_5112a);
1414 if (mode < 2) {
1415 ATH5K_ERR(ah->ah_sc, "invalid channel mode: %i\n",
1416 mode);
1417 return -EINVAL;
1418 }
1419 mode = mode - 2; /*no a/turboa modes for 2112*/
1420 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1421 rf_ini = rfregs_5112a;
1422 rf_size = ARRAY_SIZE(rfregs_5112a);
1423 } else { 337 } else {
1424 rf_ini = rfregs_5112; 338 rf_ini = rfb_5112;
1425 rf_size = ARRAY_SIZE(rfregs_5112); 339 rf_size = ARRAY_SIZE(rfb_5112);
1426 } 340 }
1427 341
1428 /* Copy values to modify them */ 342 /* Copy values to modify them */
1429 for (i = 0; i < rf_size; i++) { 343 for (i = 0; i < rf_size; i++) {
1430 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { 344 if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1431 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 345 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1432 return -EINVAL; 346 return -EINVAL;
1433 } 347 }
1434 348
1435 if (bank != rf_ini[i].rf_bank) { 349 if (bank != rf_ini[i].rfb_bank) {
1436 bank = rf_ini[i].rf_bank; 350 bank = rf_ini[i].rfb_bank;
1437 ah->ah_offset[bank] = i; 351 ah->ah_offset[bank] = i;
1438 } 352 }
1439 353
1440 rf[i] = rf_ini[i].rf_value[mode]; 354 rf[i] = rf_ini[i].rfb_mode_data[mode];
1441 } 355 }
1442 356
1443 /* Modify bank 6 */ 357 /* Modify bank 6 */
@@ -1491,7 +405,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1491 405
1492 /* Write RF values */ 406 /* Write RF values */
1493 for (i = 0; i < rf_size; i++) 407 for (i = 0; i < rf_size; i++)
1494 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register); 408 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
1495 409
1496 return 0; 410 return 0;
1497} 411}
@@ -1503,7 +417,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1503static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah, 417static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1504 struct ieee80211_channel *channel, unsigned int mode) 418 struct ieee80211_channel *channel, unsigned int mode)
1505{ 419{
1506 const struct ath5k_ini_rf *rf_ini; 420 const struct ath5k_ini_rfbuffer *rf_ini;
1507 u32 *rf; 421 u32 *rf;
1508 unsigned int rf_size, i; 422 unsigned int rf_size, i;
1509 int bank = -1; 423 int bank = -1;
@@ -1514,12 +428,12 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1514 428
1515 switch (ah->ah_radio) { 429 switch (ah->ah_radio) {
1516 case AR5K_RF5413: 430 case AR5K_RF5413:
1517 rf_ini = rfregs_5413; 431 rf_ini = rfb_5413;
1518 rf_size = ARRAY_SIZE(rfregs_5413); 432 rf_size = ARRAY_SIZE(rfb_5413);
1519 break; 433 break;
1520 case AR5K_RF2413: 434 case AR5K_RF2413:
1521 rf_ini = rfregs_2413; 435 rf_ini = rfb_2413;
1522 rf_size = ARRAY_SIZE(rfregs_2413); 436 rf_size = ARRAY_SIZE(rfb_2413);
1523 437
1524 if (mode < 2) { 438 if (mode < 2) {
1525 ATH5K_ERR(ah->ah_sc, 439 ATH5K_ERR(ah->ah_sc,
@@ -1527,11 +441,10 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1527 return -EINVAL; 441 return -EINVAL;
1528 } 442 }
1529 443
1530 mode = mode - 2;
1531 break; 444 break;
1532 case AR5K_RF2425: 445 case AR5K_RF2425:
1533 rf_ini = rfregs_2425; 446 rf_ini = rfb_2425;
1534 rf_size = ARRAY_SIZE(rfregs_2425); 447 rf_size = ARRAY_SIZE(rfb_2425);
1535 448
1536 if (mode < 2) { 449 if (mode < 2) {
1537 ATH5K_ERR(ah->ah_sc, 450 ATH5K_ERR(ah->ah_sc,
@@ -1539,12 +452,6 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1539 return -EINVAL; 452 return -EINVAL;
1540 } 453 }
1541 454
1542 /* Map b to g */
1543 if (mode == 2)
1544 mode = 0;
1545 else
1546 mode = mode - 3;
1547
1548 break; 455 break;
1549 default: 456 default:
1550 return -EINVAL; 457 return -EINVAL;
@@ -1552,17 +459,17 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1552 459
1553 /* Copy values to modify them */ 460 /* Copy values to modify them */
1554 for (i = 0; i < rf_size; i++) { 461 for (i = 0; i < rf_size; i++) {
1555 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) { 462 if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1556 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 463 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1557 return -EINVAL; 464 return -EINVAL;
1558 } 465 }
1559 466
1560 if (bank != rf_ini[i].rf_bank) { 467 if (bank != rf_ini[i].rfb_bank) {
1561 bank = rf_ini[i].rf_bank; 468 bank = rf_ini[i].rfb_bank;
1562 ah->ah_offset[bank] = i; 469 ah->ah_offset[bank] = i;
1563 } 470 }
1564 471
1565 rf[i] = rf_ini[i].rf_value[mode]; 472 rf[i] = rf_ini[i].rfb_mode_data[mode];
1566 } 473 }
1567 474
1568 /* 475 /*
@@ -1577,7 +484,7 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1577 484
1578 /* Write RF values */ 485 /* Write RF values */
1579 for (i = 0; i < rf_size; i++) 486 for (i = 0; i < rf_size; i++)
1580 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register); 487 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
1581 488
1582 return 0; 489 return 0;
1583} 490}
@@ -1593,26 +500,26 @@ int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1593 500
1594 switch (ah->ah_radio) { 501 switch (ah->ah_radio) {
1595 case AR5K_RF5111: 502 case AR5K_RF5111:
1596 ah->ah_rf_banks_size = sizeof(rfregs_5111); 503 ah->ah_rf_banks_size = sizeof(rfb_5111);
1597 func = ath5k_hw_rf5111_rfregs; 504 func = ath5k_hw_rf5111_rfregs;
1598 break; 505 break;
1599 case AR5K_RF5112: 506 case AR5K_RF5112:
1600 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 507 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1601 ah->ah_rf_banks_size = sizeof(rfregs_5112a); 508 ah->ah_rf_banks_size = sizeof(rfb_5112a);
1602 else 509 else
1603 ah->ah_rf_banks_size = sizeof(rfregs_5112); 510 ah->ah_rf_banks_size = sizeof(rfb_5112);
1604 func = ath5k_hw_rf5112_rfregs; 511 func = ath5k_hw_rf5112_rfregs;
1605 break; 512 break;
1606 case AR5K_RF5413: 513 case AR5K_RF5413:
1607 ah->ah_rf_banks_size = sizeof(rfregs_5413); 514 ah->ah_rf_banks_size = sizeof(rfb_5413);
1608 func = ath5k_hw_rf5413_rfregs; 515 func = ath5k_hw_rf5413_rfregs;
1609 break; 516 break;
1610 case AR5K_RF2413: 517 case AR5K_RF2413:
1611 ah->ah_rf_banks_size = sizeof(rfregs_2413); 518 ah->ah_rf_banks_size = sizeof(rfb_2413);
1612 func = ath5k_hw_rf5413_rfregs; 519 func = ath5k_hw_rf5413_rfregs;
1613 break; 520 break;
1614 case AR5K_RF2425: 521 case AR5K_RF2425:
1615 ah->ah_rf_banks_size = sizeof(rfregs_2425); 522 ah->ah_rf_banks_size = sizeof(rfb_2425);
1616 func = ath5k_hw_rf5413_rfregs; 523 func = ath5k_hw_rf5413_rfregs;
1617 break; 524 break;
1618 default: 525 default:
@@ -1656,12 +563,10 @@ int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1656 case AR5K_RF2413: 563 case AR5K_RF2413:
1657 ath5k_rfg = rfgain_2413; 564 ath5k_rfg = rfgain_2413;
1658 size = ARRAY_SIZE(rfgain_2413); 565 size = ARRAY_SIZE(rfgain_2413);
1659 freq = 0; /* only 2Ghz */
1660 break; 566 break;
1661 case AR5K_RF2425: 567 case AR5K_RF2425:
1662 ath5k_rfg = rfgain_2425; 568 ath5k_rfg = rfgain_2425;
1663 size = ARRAY_SIZE(rfgain_2425); 569 size = ARRAY_SIZE(rfgain_2425);
1664 freq = 0; /* only 2Ghz */
1665 break; 570 break;
1666 default: 571 default:
1667 return -EINVAL; 572 return -EINVAL;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 22:19:25 -0500