ath5k: Update interrupt masking code

*Properly get/set all available ISR/IMR values and review common/uncommon bits
*Better handling of per-txq interrupts (we can now resolve what q is generating
 each interrupt -this will help in debuging wme later)
*Some minor updates from legacy-hal
*Properly handle RXNOFRM and TXNOFRM interrupt masking (even when we don't set
 them on IMR they keep showing up, so we disable them by zeroing AR5K_RXNOFRM
 and AR5K_TXNOFRM registers). This doesn't exist on legacy-hal but i've tested
 it on various cards and it works fine.

Changes-Licensed-under: ISC
Signed-Off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 60 insertions, 26 deletions

diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h
index 53ea439aff48..b11792039911 100644
--- a/drivers/net/wireless/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath5k/ath5k.h
@@ -507,11 +507,15 @@ enum ath5k_tx_queue_id {
 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
-#define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0020  /* Disable random post-backoff */
-#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040  /* Enable ready time expiry policy (?)*/
-#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080  /* Enable backoff while bursting */
-#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x0100  /* Disable backoff while bursting */
-#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x0200  /* Enable hw compression -not implemented-*/
+#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE          0x0020  /* Enable CBRORN interrupt */
+#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE          0x0040  /* Enable CBRURN interrupt */
+#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE           0x0080  /* Enable QTRIG interrupt */
+#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE         0x0100  /* Enable TXNOFRM interrupt */
+#define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0200  /* Disable random post-backoff */
+#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300  /* Enable ready time expiry policy (?)*/
+#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800  /* Enable backoff while bursting */
+#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x1000  /* Disable backoff while bursting */
+#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x2000  /* Enable hw compression -not implemented-*/
 
 /*
  * A struct to hold tx queue's parameters
@@ -853,7 +857,7 @@ enum ath5k_ant_setting {
  *      checked. We should do this with ath5k_hw_update_mib_counters() but
  *      it seems we should also then do some noise immunity work.
  * @AR5K_INT_RXPHY: RX PHY Error
- * @AR5K_INT_RXKCM: ??
+ * @AR5K_INT_RXKCM: RX Key cache miss
  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
  *      beacon that must be handled in software. The alternative is if you
  *      have VEOL support, in that case you let the hardware deal with things.
@@ -869,7 +873,7 @@ enum ath5k_ant_setting {
  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
  *      errors. These types of errors we can enable seem to be of type
  *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
- * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
+ * @AR5K_INT_GLOBAL: Used to clear and set the IER
  * @AR5K_INT_NOCARD: signals the card has been removed
  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
  *      bit value
@@ -881,36 +885,61 @@ enum ath5k_ant_setting {
  * MACs.
  */
 enum ath5k_int {
-        AR5K_INT_RX     = 0x00000001, /* Not common */
+        AR5K_INT_RXOK   = 0x00000001,
         AR5K_INT_RXDESC = 0x00000002,
+        AR5K_INT_RXERR  = 0x00000004,
         AR5K_INT_RXNOFRM = 0x00000008,
         AR5K_INT_RXEOL  = 0x00000010,
         AR5K_INT_RXORN  = 0x00000020,
-        AR5K_INT_TX     = 0x00000040, /* Not common */
+        AR5K_INT_TXOK   = 0x00000040,
         AR5K_INT_TXDESC = 0x00000080,
+        AR5K_INT_TXERR  = 0x00000100,
+        AR5K_INT_TXNOFRM = 0x00000200,
+        AR5K_INT_TXEOL  = 0x00000400,
         AR5K_INT_TXURN  = 0x00000800,
         AR5K_INT_MIB    = 0x00001000,
+        AR5K_INT_SWI    = 0x00002000,
         AR5K_INT_RXPHY  = 0x00004000,
         AR5K_INT_RXKCM  = 0x00008000,
         AR5K_INT_SWBA   = 0x00010000,
+        AR5K_INT_BRSSI  = 0x00020000,
         AR5K_INT_BMISS  = 0x00040000,
-        AR5K_INT_BNR    = 0x00100000, /* Not common */
-        AR5K_INT_GPIO   = 0x01000000,
-        AR5K_INT_FATAL  = 0x40000000, /* Not common */
-        AR5K_INT_GLOBAL = 0x80000000,
-
-        AR5K_INT_COMMON  = AR5K_INT_RXNOFRM
-                        | AR5K_INT_RXDESC
-                        | AR5K_INT_RXEOL
-                        | AR5K_INT_RXORN
-                        | AR5K_INT_TXURN
-                        | AR5K_INT_TXDESC
-                        | AR5K_INT_MIB
-                        | AR5K_INT_RXPHY
-                        | AR5K_INT_RXKCM
-                        | AR5K_INT_SWBA
-                        | AR5K_INT_BMISS
-                        | AR5K_INT_GPIO,
+        AR5K_INT_FATAL  = 0x00080000, /* Non common */
+        AR5K_INT_BNR    = 0x00100000, /* Non common */
+        AR5K_INT_TIM    = 0x00200000, /* Non common */
+        AR5K_INT_DTIM   = 0x00400000, /* Non common */
+        AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
+        AR5K_INT_GPIO   =       0x01000000,
+        AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
+        AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
+        AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
+        AR5K_INT_QCBRORN =      0x10000000, /* Non common */
+        AR5K_INT_QCBRURN =      0x20000000, /* Non common */
+        AR5K_INT_QTRIG  =       0x40000000, /* Non common */
+        AR5K_INT_GLOBAL =       0x80000000,
+
+        AR5K_INT_COMMON  = AR5K_INT_RXOK
+                | AR5K_INT_RXDESC
+                | AR5K_INT_RXERR
+                | AR5K_INT_RXNOFRM
+                | AR5K_INT_RXEOL
+                | AR5K_INT_RXORN
+                | AR5K_INT_TXOK
+                | AR5K_INT_TXDESC
+                | AR5K_INT_TXERR
+                | AR5K_INT_TXNOFRM
+                | AR5K_INT_TXEOL
+                | AR5K_INT_TXURN
+                | AR5K_INT_MIB
+                | AR5K_INT_SWI
+                | AR5K_INT_RXPHY
+                | AR5K_INT_RXKCM
+                | AR5K_INT_SWBA
+                | AR5K_INT_BRSSI
+                | AR5K_INT_BMISS
+                | AR5K_INT_GPIO
+                | AR5K_INT_GLOBAL,
+
         AR5K_INT_NOCARD = 0xffffffff
 };
 
@@ -1081,6 +1110,11 @@ struct ath5k_hw {
         u32                     ah_txq_imr_txurn;
         u32                     ah_txq_imr_txdesc;
         u32                     ah_txq_imr_txeol;
+        u32                     ah_txq_imr_cbrorn;
+        u32                     ah_txq_imr_cbrurn;
+        u32                     ah_txq_imr_qtrig;
+        u32                     ah_txq_imr_nofrm;
+        u32                     ah_txq_isr;
         u32                     *ah_rf_banks;
         size_t                  ah_rf_banks_size;
         struct ath5k_gain       ah_gain;