ath9k_hw: Rename antenna diversity macros

The register macros for antenna diversity are common for AR9462 and AR9565, rename them. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
author: Sujith Manoharan <c_manoha@qualcomm.com> 2012-09-11 01:16:38 -0400
committer: John W. Linville <linville@tuxdriver.com> 2012-09-11 15:32:00 -0400
commit: 9aa49ea3f5999a6a36823bd259892088896af140 (patch)
tree: 29e6a5d5ff2a4afff6ef1d32eb060bc8ccda44ad /drivers/net/wireless/ath/ath9k
parent: b7f597668657c9c9579dbdff9692aea3e8e9bf5a (diff)
3 files changed, 51 insertions, 55 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a25299375bb4..b5659cb688fe 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3627,19 +3627,16 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                regval &= (~AR_ANT_DIV_CTRL_ALL);
                regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
                /* enable_lnadiv */
-                regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
+                regval &= (~AR_PHY_ANT_DIV_LNADIV);
-                regval |= ((value >> 6) & 0x1) <<
+                regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
-                                AR_PHY_9485_ANT_DIV_LNADIV_S;
                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
                /*enable fast_div */
                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
                regval &= (~AR_FAST_DIV_ENABLE);
-                regval |= ((value >> 7) & 0x1) <<
+                regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
-                                AR_FAST_DIV_ENABLE_S;
                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
-                ant_div_ctl1 =
+                ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
-                        ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /* check whether antenna diversity is enabled */
                if ((ant_div_ctl1 >> 0x6) == 0x3) {
                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
@@ -3647,15 +3644,15 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                         * clear bits 25-30 main_lnaconf, alt_lnaconf,
                         * main_tb, alt_tb
                         */
-                        regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                        regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
-                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                                     AR_PHY_ANT_DIV_ALT_LNACONF |
-                                        AR_PHY_9485_ANT_DIV_ALT_GAINTB |
+                                     AR_PHY_ANT_DIV_ALT_GAINTB |
-                                        AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
+                                     AR_PHY_ANT_DIV_MAIN_GAINTB));
                        /* by default use LNA1 for the main antenna */
-                        regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
+                        regval |= (AR_PHY_ANT_DIV_LNA1 <<
-                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
+                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
-                        regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
+                        regval |= (AR_PHY_ANT_DIV_LNA2 <<
-                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
+                                   AR_PHY_ANT_DIV_ALT_LNACONF_S);
                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
                }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 05d0ac0aca78..0d800c62e227 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1276,17 +1276,17 @@ static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
 }
 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
-                                   struct ath_hw_antcomb_conf *antconf)
+                                           struct ath_hw_antcomb_conf *antconf)
 {
        u32 regval;
        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
-        antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
+        antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
-                                  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
+                                  AR_PHY_ANT_DIV_MAIN_LNACONF_S;
-        antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
+        antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
-                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
+                                 AR_PHY_ANT_DIV_ALT_LNACONF_S;
-        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
+        antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
-                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
+                                  AR_PHY_ANT_FAST_DIV_BIAS_S;
        if (AR_SREV_9330_11(ah)) {
                antconf->lna1_lna2_delta = -9;
@@ -1306,22 +1306,21 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
        u32 regval;
        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
-        regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+        regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
-                    AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                    AR_PHY_ANT_DIV_ALT_LNACONF |
-                    AR_PHY_9485_ANT_FAST_DIV_BIAS |
+                    AR_PHY_ANT_FAST_DIV_BIAS |
-                    AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
+                    AR_PHY_ANT_DIV_MAIN_GAINTB |
-                    AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+                    AR_PHY_ANT_DIV_ALT_GAINTB);
-        regval |= ((antconf->main_lna_conf <<
+        regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
-                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
+                   & AR_PHY_ANT_DIV_MAIN_LNACONF);
-                   & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
+        regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
-        regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
+                   & AR_PHY_ANT_DIV_ALT_LNACONF);
-                   & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
+        regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
-        regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
+                   & AR_PHY_ANT_FAST_DIV_BIAS);
-                   & AR_PHY_9485_ANT_FAST_DIV_BIAS);
+        regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
-        regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
+                   & AR_PHY_ANT_DIV_MAIN_GAINTB);
-                   & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
+        regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
-        regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
+                   & AR_PHY_ANT_DIV_ALT_GAINTB);
-                   & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index ca532f5c20b6..fdabc9a28a96 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -280,23 +280,23 @@
 #define AR_ANT_DIV_ENABLE_S     24
-#define AR_PHY_9485_ANT_FAST_DIV_BIAS                   0x00007e00
+#define AR_PHY_ANT_FAST_DIV_BIAS                0x00007e00
-#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9
+#define AR_PHY_ANT_FAST_DIV_BIAS_S              9
-#define AR_PHY_9485_ANT_DIV_LNADIV                      0x01000000
+#define AR_PHY_ANT_DIV_LNADIV                   0x01000000
-#define AR_PHY_9485_ANT_DIV_LNADIV_S                    24
+#define AR_PHY_ANT_DIV_LNADIV_S                 24
-#define AR_PHY_9485_ANT_DIV_ALT_LNACONF                 0x06000000
+#define AR_PHY_ANT_DIV_ALT_LNACONF              0x06000000
-#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S               25
+#define AR_PHY_ANT_DIV_ALT_LNACONF_S            25
-#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF                0x18000000
+#define AR_PHY_ANT_DIV_MAIN_LNACONF             0x18000000
-#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S              27
+#define AR_PHY_ANT_DIV_MAIN_LNACONF_S           27
-#define AR_PHY_9485_ANT_DIV_ALT_GAINTB                  0x20000000
+#define AR_PHY_ANT_DIV_ALT_GAINTB               0x20000000
-#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S                29
+#define AR_PHY_ANT_DIV_ALT_GAINTB_S             29
-#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB                 0x40000000
+#define AR_PHY_ANT_DIV_MAIN_GAINTB              0x40000000
-#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S               30
+#define AR_PHY_ANT_DIV_MAIN_GAINTB_S            30
-#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2             0x0
+#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2          0x0
-#define AR_PHY_9485_ANT_DIV_LNA2                        0x1
+#define AR_PHY_ANT_DIV_LNA2                     0x1
-#define AR_PHY_9485_ANT_DIV_LNA1                        0x2
+#define AR_PHY_ANT_DIV_LNA1                     0x2
-#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2              0x3
+#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2           0x3
 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
author	Sujith Manoharan <c_manoha@qualcomm.com>	2012-09-11 01:16:38 -0400
committer	John W. Linville <linville@tuxdriver.com>	2012-09-11 15:32:00 -0400
commit	9aa49ea3f5999a6a36823bd259892088896af140 (patch)
tree	29e6a5d5ff2a4afff6ef1d32eb060bc8ccda44ad /drivers/net/wireless/ath/ath9k
parent	b7f597668657c9c9579dbdff9692aea3e8e9bf5a (diff)

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index a25299375bb4..b5659cb688fe 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3627,19 +3627,16 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3627	regval &= (~AR_ANT_DIV_CTRL_ALL);	3627	regval &= (~AR_ANT_DIV_CTRL_ALL);
3628	regval \|= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;	3628	regval \|= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3629	/* enable_lnadiv */	3629	/* enable_lnadiv */
3630	regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);	3630	regval &= (~AR_PHY_ANT_DIV_LNADIV);
3631	regval \|= ((value >> 6) & 0x1) <<	3631	regval \|= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
3632	AR_PHY_9485_ANT_DIV_LNADIV_S;
3633	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);	3632	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3634		3633
3635	/enable fast_div /	3634	/enable fast_div /
3636	regval = REG_READ(ah, AR_PHY_CCK_DETECT);	3635	regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3637	regval &= (~AR_FAST_DIV_ENABLE);	3636	regval &= (~AR_FAST_DIV_ENABLE);
3638	regval \|= ((value >> 7) & 0x1) <<	3637	regval \|= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
3639	AR_FAST_DIV_ENABLE_S;
3640	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);	3638	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3641	ant_div_ctl1 =	3639	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3642	ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3643	/* check whether antenna diversity is enabled */	3640	/* check whether antenna diversity is enabled */
3644	if ((ant_div_ctl1 >> 0x6) == 0x3) {	3641	if ((ant_div_ctl1 >> 0x6) == 0x3) {
3645	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);	3642	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
@@ -3647,15 +3644,15 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3647	* clear bits 25-30 main_lnaconf, alt_lnaconf,	3644	* clear bits 25-30 main_lnaconf, alt_lnaconf,
3648	* main_tb, alt_tb	3645	* main_tb, alt_tb
3649	*/	3646	*/
3650	regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF \|	3647	regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF \|
3651	AR_PHY_9485_ANT_DIV_ALT_LNACONF \|	3648	AR_PHY_ANT_DIV_ALT_LNACONF \|
3652	AR_PHY_9485_ANT_DIV_ALT_GAINTB \|	3649	AR_PHY_ANT_DIV_ALT_GAINTB \|
3653	AR_PHY_9485_ANT_DIV_MAIN_GAINTB));	3650	AR_PHY_ANT_DIV_MAIN_GAINTB));
3654	/* by default use LNA1 for the main antenna */	3651	/* by default use LNA1 for the main antenna */
3655	regval \|= (AR_PHY_9485_ANT_DIV_LNA1 <<	3652	regval \|= (AR_PHY_ANT_DIV_LNA1 <<
3656	AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);	3653	AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3657	regval \|= (AR_PHY_9485_ANT_DIV_LNA2 <<	3654	regval \|= (AR_PHY_ANT_DIV_LNA2 <<
3658	AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);	3655	AR_PHY_ANT_DIV_ALT_LNACONF_S);
3659	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);	3656	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3660	}	3657	}
3661		3658


diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 05d0ac0aca78..0d800c62e227 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1276,17 +1276,17 @@ static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1276	}	1276	}
1277		1277
1278	static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,	1278	static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1279	struct ath_hw_antcomb_conf *antconf)	1279	struct ath_hw_antcomb_conf *antconf)
1280	{	1280	{
1281	u32 regval;	1281	u32 regval;
1282		1282
1283	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);	1283	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1284	antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>	1284	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1285	AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;	1285	AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1286	antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>	1286	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1287	AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;	1287	AR_PHY_ANT_DIV_ALT_LNACONF_S;
1288	antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>	1288	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1289	AR_PHY_9485_ANT_FAST_DIV_BIAS_S;	1289	AR_PHY_ANT_FAST_DIV_BIAS_S;
1290		1290
1291	if (AR_SREV_9330_11(ah)) {	1291	if (AR_SREV_9330_11(ah)) {
1292	antconf->lna1_lna2_delta = -9;	1292	antconf->lna1_lna2_delta = -9;
@@ -1306,22 +1306,21 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1306	u32 regval;	1306	u32 regval;
1307		1307
1308	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);	1308	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1309	regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF \|	1309	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF \|
1310	AR_PHY_9485_ANT_DIV_ALT_LNACONF \|	1310	AR_PHY_ANT_DIV_ALT_LNACONF \|
1311	AR_PHY_9485_ANT_FAST_DIV_BIAS \|	1311	AR_PHY_ANT_FAST_DIV_BIAS \|
1312	AR_PHY_9485_ANT_DIV_MAIN_GAINTB \|	1312	AR_PHY_ANT_DIV_MAIN_GAINTB \|
1313	AR_PHY_9485_ANT_DIV_ALT_GAINTB);	1313	AR_PHY_ANT_DIV_ALT_GAINTB);
1314	regval \|= ((antconf->main_lna_conf <<	1314	regval \|= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1315	AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)	1315	& AR_PHY_ANT_DIV_MAIN_LNACONF);
1316	& AR_PHY_9485_ANT_DIV_MAIN_LNACONF);	1316	regval \|= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1317	regval \|= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)	1317	& AR_PHY_ANT_DIV_ALT_LNACONF);
1318	& AR_PHY_9485_ANT_DIV_ALT_LNACONF);	1318	regval \|= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1319	regval \|= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)	1319	& AR_PHY_ANT_FAST_DIV_BIAS);
1320	& AR_PHY_9485_ANT_FAST_DIV_BIAS);	1320	regval \|= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1321	regval \|= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)	1321	& AR_PHY_ANT_DIV_MAIN_GAINTB);
1322	& AR_PHY_9485_ANT_DIV_MAIN_GAINTB);	1322	regval \|= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1323	regval \|= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)	1323	& AR_PHY_ANT_DIV_ALT_GAINTB);
1324	& AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1325		1324
1326	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);	1325	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1327	}	1326	}


diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index ca532f5c20b6..fdabc9a28a96 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -280,23 +280,23 @@
280	#define AR_ANT_DIV_ENABLE_S 24	280	#define AR_ANT_DIV_ENABLE_S 24
281		281
282		282
283	#define AR_PHY_9485_ANT_FAST_DIV_BIAS 0x00007e00	283	#define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00
284	#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S 9	284	#define AR_PHY_ANT_FAST_DIV_BIAS_S 9
285	#define AR_PHY_9485_ANT_DIV_LNADIV 0x01000000	285	#define AR_PHY_ANT_DIV_LNADIV 0x01000000
286	#define AR_PHY_9485_ANT_DIV_LNADIV_S 24	286	#define AR_PHY_ANT_DIV_LNADIV_S 24
287	#define AR_PHY_9485_ANT_DIV_ALT_LNACONF 0x06000000	287	#define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000
288	#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S 25	288	#define AR_PHY_ANT_DIV_ALT_LNACONF_S 25
289	#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF 0x18000000	289	#define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000
290	#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S 27	290	#define AR_PHY_ANT_DIV_MAIN_LNACONF_S 27
291	#define AR_PHY_9485_ANT_DIV_ALT_GAINTB 0x20000000	291	#define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000
292	#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S 29	292	#define AR_PHY_ANT_DIV_ALT_GAINTB_S 29
293	#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB 0x40000000	293	#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
294	#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S 30	294	#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30
295		295
296	#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2 0x0	296	#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2 0x0
297	#define AR_PHY_9485_ANT_DIV_LNA2 0x1	297	#define AR_PHY_ANT_DIV_LNA2 0x1
298	#define AR_PHY_9485_ANT_DIV_LNA1 0x2	298	#define AR_PHY_ANT_DIV_LNA1 0x2
299	#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2 0x3	299	#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2 0x3
300		300
301	#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)	301	#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
302	#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)	302	#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)