ath9k_hw: Update the PCI WAR register

This patch updates the PCI power save handling
code, fixing ASPM hangs and handling device state D3
properly.

The WAR register is programmed with the correct
values now.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index c9a009fab221..a7371a080491 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -700,6 +700,9 @@
 #define AR_RC_HOSTIF         0x00000100
 
 #define AR_WA                           0x4004
+#define AR_WA_BIT6                      (1 << 6)
+#define AR_WA_BIT7                      (1 << 7)
+#define AR_WA_BIT23                     (1 << 23)
 #define AR_WA_D3_L1_DISABLE             (1 << 14)
 #define AR9285_WA_DEFAULT               0x004a050b
 #define AR9280_WA_DEFAULT               0x0040073b