diff options
author | Felix Fietkau <nbd@openwrt.org> | 2011-03-23 15:57:27 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-03-30 14:15:19 -0400 |
commit | a9b6b2569cf107fe541381e82faa0a3c47a9a7fd (patch) | |
tree | ddd70da664996e96c554682e2348f60598a41c12 /drivers/net/wireless/ath/ath9k/phy.h | |
parent | ca7a4deb4a1a87dbdc6e7cab0d1022a535204226 (diff) |
ath9k_hw: turn a few big macros into functions
RF_BANK_SETUP, REG_WRITE_RF_ARRAY and REG_WRITE_ARRAY are way too big,
so they shouldn't be inlined at every single callsite, especially since they
can easily be turned into real functions.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/phy.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/phy.h | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h index e4029325c787..f50e2c29f71e 100644 --- a/drivers/net/wireless/ath/ath9k/phy.h +++ b/drivers/net/wireless/ath/ath9k/phy.h | |||
@@ -38,27 +38,11 @@ | |||
38 | #define AR_PHY_CLC_Q0 0x0000ffd0 | 38 | #define AR_PHY_CLC_Q0 0x0000ffd0 |
39 | #define AR_PHY_CLC_Q0_S 5 | 39 | #define AR_PHY_CLC_Q0_S 5 |
40 | 40 | ||
41 | #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ | ||
42 | int r; \ | ||
43 | ENABLE_REGWRITE_BUFFER(ah); \ | ||
44 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | ||
45 | REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ | ||
46 | DO_DELAY(regWr); \ | ||
47 | } \ | ||
48 | REGWRITE_BUFFER_FLUSH(ah); \ | ||
49 | } while (0) | ||
50 | |||
51 | #define ANTSWAP_AB 0x0001 | 41 | #define ANTSWAP_AB 0x0001 |
52 | #define REDUCE_CHAIN_0 0x00000050 | 42 | #define REDUCE_CHAIN_0 0x00000050 |
53 | #define REDUCE_CHAIN_1 0x00000051 | 43 | #define REDUCE_CHAIN_1 0x00000051 |
54 | #define AR_PHY_CHIP_ID 0x9818 | 44 | #define AR_PHY_CHIP_ID 0x9818 |
55 | 45 | ||
56 | #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ | ||
57 | int i; \ | ||
58 | for (i = 0; i < (_iniarray)->ia_rows; i++) \ | ||
59 | (_bank)[i] = INI_RA((_iniarray), i, _col);; \ | ||
60 | } while (0) | ||
61 | |||
62 | #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 | 46 | #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 |
63 | #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 | 47 | #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 |
64 | 48 | ||