diff options
author | Vivek Natarajan <vivek.natraj@gmail.com> | 2009-08-14 01:57:16 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-08-20 11:35:51 -0400 |
commit | db91f2e4d410bf3011b3649b9257e5b3c60b25ff (patch) | |
tree | 0a9ee7cd004198ae7b6a76fb8f5aa5671b61e716 /drivers/net/wireless/ath/ath9k/phy.h | |
parent | 1e711bee566e26f03e51d5a754e7c8a57e489f9f (diff) |
ath9k: Add open loop power control support for AR9287.
Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/phy.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/phy.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h index e83cd4ab87f0..dfda6f444648 100644 --- a/drivers/net/wireless/ath/ath9k/phy.h +++ b/drivers/net/wireless/ath/ath9k/phy.h | |||
@@ -490,11 +490,18 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, | |||
490 | #define AR_PHY_TX_PWRCTRL9 0xa27C | 490 | #define AR_PHY_TX_PWRCTRL9 0xa27C |
491 | #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 | 491 | #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 |
492 | #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 | 492 | #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 |
493 | #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 | ||
494 | #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 | ||
493 | 495 | ||
494 | #define AR_PHY_TX_GAIN_TBL1 0xa300 | 496 | #define AR_PHY_TX_GAIN_TBL1 0xa300 |
495 | #define AR_PHY_TX_GAIN 0x0007F000 | 497 | #define AR_PHY_TX_GAIN 0x0007F000 |
496 | #define AR_PHY_TX_GAIN_S 12 | 498 | #define AR_PHY_TX_GAIN_S 12 |
497 | 499 | ||
500 | #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 | ||
501 | #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 | ||
502 | #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 | ||
503 | #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 | ||
504 | |||
498 | #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 | 505 | #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 |
499 | #define AR_PHY_MASK2_M_31_45 0xa3a4 | 506 | #define AR_PHY_MASK2_M_31_45 0xa3a4 |
500 | #define AR_PHY_MASK2_M_16_30 0xa3a8 | 507 | #define AR_PHY_MASK2_M_16_30 0xa3a8 |