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authorSujith Manoharan <c_manoha@qca.qualcomm.com>2012-06-04 06:57:36 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-06-06 15:20:25 -0400
commit31604cf0a73ffd63929f3a646d5402d5901c6e4b (patch)
tree5c79f2725a78a5c63f701c18d32767be4b846181 /drivers/net/wireless/ath/ath9k/hw.c
parent5955b2b0ef208e03188ef1c2810c004bde493253 (diff)
ath9k_hw: Cleanup power mode API
The 'setChip' variable is unused, remove it and simplify the functions. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c175
1 files changed, 85 insertions, 90 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index a7231cadec40..9f0f5f74f17a 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2004,39 +2004,38 @@ EXPORT_SYMBOL(ath9k_hw_reset);
2004 * Notify Power Mgt is disabled in self-generated frames. 2004 * Notify Power Mgt is disabled in self-generated frames.
2005 * If requested, force chip to sleep. 2005 * If requested, force chip to sleep.
2006 */ 2006 */
2007static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2007static void ath9k_set_power_sleep(struct ath_hw *ah)
2008{ 2008{
2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2010 if (setChip) {
2011 if (AR_SREV_9462(ah)) {
2012 REG_WRITE(ah, AR_TIMER_MODE,
2013 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2014 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2015 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2016 REG_WRITE(ah, AR_SLP32_INC,
2017 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2018 /* xxx Required for WLAN only case ? */
2019 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2020 udelay(100);
2021 }
2022 2010
2023 /* 2011 if (AR_SREV_9462(ah)) {
2024 * Clear the RTC force wake bit to allow the 2012 REG_WRITE(ah, AR_TIMER_MODE,
2025 * mac to go to sleep. 2013 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2026 */ 2014 REG_WRITE(ah, AR_NDP2_TIMER_MODE,
2027 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2015 REG_READ(ah, AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2016 REG_WRITE(ah, AR_SLP32_INC,
2017 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2018 /* xxx Required for WLAN only case ? */
2019 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2020 udelay(100);
2021 }
2028 2022
2029 if (AR_SREV_9462(ah)) 2023 /*
2030 udelay(100); 2024 * Clear the RTC force wake bit to allow the
2025 * mac to go to sleep.
2026 */
2027 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2031 2028
2032 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2029 if (AR_SREV_9462(ah))
2033 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2030 udelay(100);
2034 2031
2035 /* Shutdown chip. Active low */ 2032 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2036 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2033 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2037 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2034
2038 udelay(2); 2035 /* Shutdown chip. Active low */
2039 } 2036 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2037 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2038 udelay(2);
2040 } 2039 }
2041 2040
2042 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2041 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
@@ -2049,44 +2048,42 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2049 * frames. If request, set power mode of chip to 2048 * frames. If request, set power mode of chip to
2050 * auto/normal. Duration in units of 128us (1/8 TU). 2049 * auto/normal. Duration in units of 128us (1/8 TU).
2051 */ 2050 */
2052static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2051static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2053{ 2052{
2053 struct ath9k_hw_capabilities *pCap = &ah->caps;
2054 u32 val; 2054 u32 val;
2055 2055
2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2057 if (setChip) {
2058 struct ath9k_hw_capabilities *pCap = &ah->caps;
2059 2057
2060 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2058 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2061 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2059 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2062 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2060 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2063 AR_RTC_FORCE_WAKE_ON_INT); 2061 AR_RTC_FORCE_WAKE_ON_INT);
2064 } else { 2062 } else {
2065 2063
2066 /* When chip goes into network sleep, it could be waken 2064 /* When chip goes into network sleep, it could be waken
2067 * up by MCI_INT interrupt caused by BT's HW messages 2065 * up by MCI_INT interrupt caused by BT's HW messages
2068 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2066 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2069 * rate (~100us). This will cause chip to leave and 2067 * rate (~100us). This will cause chip to leave and
2070 * re-enter network sleep mode frequently, which in 2068 * re-enter network sleep mode frequently, which in
2071 * consequence will have WLAN MCI HW to generate lots of 2069 * consequence will have WLAN MCI HW to generate lots of
2072 * SYS_WAKING and SYS_SLEEPING messages which will make 2070 * SYS_WAKING and SYS_SLEEPING messages which will make
2073 * BT CPU to busy to process. 2071 * BT CPU to busy to process.
2074 */ 2072 */
2075 if (AR_SREV_9462(ah)) { 2073 if (AR_SREV_9462(ah)) {
2076 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2074 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2077 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2075 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2078 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 2076 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2079 }
2080 /*
2081 * Clear the RTC force wake bit to allow the
2082 * mac to go to sleep.
2083 */
2084 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2085 AR_RTC_FORCE_WAKE_EN);
2086
2087 if (AR_SREV_9462(ah))
2088 udelay(30);
2089 } 2077 }
2078 /*
2079 * Clear the RTC force wake bit to allow the
2080 * mac to go to sleep.
2081 */
2082 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2083 AR_RTC_FORCE_WAKE_EN);
2084
2085 if (AR_SREV_9462(ah))
2086 udelay(30);
2090 } 2087 }
2091 2088
2092 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2089 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
@@ -2094,7 +2091,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2094 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2091 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2095} 2092}
2096 2093
2097static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2094static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2098{ 2095{
2099 u32 val; 2096 u32 val;
2100 int i; 2097 int i;
@@ -2105,37 +2102,35 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2105 udelay(10); 2102 udelay(10);
2106 } 2103 }
2107 2104
2108 if (setChip) { 2105 if ((REG_READ(ah, AR_RTC_STATUS) &
2109 if ((REG_READ(ah, AR_RTC_STATUS) & 2106 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2110 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2107 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2111 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2108 return false;
2112 return false;
2113 }
2114 if (!AR_SREV_9300_20_OR_LATER(ah))
2115 ath9k_hw_init_pll(ah, NULL);
2116 } 2109 }
2117 if (AR_SREV_9100(ah)) 2110 if (!AR_SREV_9300_20_OR_LATER(ah))
2118 REG_SET_BIT(ah, AR_RTC_RESET, 2111 ath9k_hw_init_pll(ah, NULL);
2119 AR_RTC_RESET_EN); 2112 }
2113 if (AR_SREV_9100(ah))
2114 REG_SET_BIT(ah, AR_RTC_RESET,
2115 AR_RTC_RESET_EN);
2120 2116
2117 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2118 AR_RTC_FORCE_WAKE_EN);
2119 udelay(50);
2120
2121 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2122 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2123 if (val == AR_RTC_STATUS_ON)
2124 break;
2125 udelay(50);
2121 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2126 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2122 AR_RTC_FORCE_WAKE_EN); 2127 AR_RTC_FORCE_WAKE_EN);
2123 udelay(50); 2128 }
2124 2129 if (i == 0) {
2125 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2130 ath_err(ath9k_hw_common(ah),
2126 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2131 "Failed to wakeup in %uus\n",
2127 if (val == AR_RTC_STATUS_ON) 2132 POWER_UP_TIME / 20);
2128 break; 2133 return false;
2129 udelay(50);
2130 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2131 AR_RTC_FORCE_WAKE_EN);
2132 }
2133 if (i == 0) {
2134 ath_err(ath9k_hw_common(ah),
2135 "Failed to wakeup in %uus\n",
2136 POWER_UP_TIME / 20);
2137 return false;
2138 }
2139 } 2134 }
2140 2135
2141 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2136 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
@@ -2146,7 +2141,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2146bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2141bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2147{ 2142{
2148 struct ath_common *common = ath9k_hw_common(ah); 2143 struct ath_common *common = ath9k_hw_common(ah);
2149 int status = true, setChip = true; 2144 int status = true;
2150 static const char *modes[] = { 2145 static const char *modes[] = {
2151 "AWAKE", 2146 "AWAKE",
2152 "FULL-SLEEP", 2147 "FULL-SLEEP",
@@ -2162,17 +2157,17 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2162 2157
2163 switch (mode) { 2158 switch (mode) {
2164 case ATH9K_PM_AWAKE: 2159 case ATH9K_PM_AWAKE:
2165 status = ath9k_hw_set_power_awake(ah, setChip); 2160 status = ath9k_hw_set_power_awake(ah);
2166 break; 2161 break;
2167 case ATH9K_PM_FULL_SLEEP: 2162 case ATH9K_PM_FULL_SLEEP:
2168 if (ath9k_hw_mci_is_enabled(ah)) 2163 if (ath9k_hw_mci_is_enabled(ah))
2169 ar9003_mci_set_full_sleep(ah); 2164 ar9003_mci_set_full_sleep(ah);
2170 2165
2171 ath9k_set_power_sleep(ah, setChip); 2166 ath9k_set_power_sleep(ah);
2172 ah->chip_fullsleep = true; 2167 ah->chip_fullsleep = true;
2173 break; 2168 break;
2174 case ATH9K_PM_NETWORK_SLEEP: 2169 case ATH9K_PM_NETWORK_SLEEP:
2175 ath9k_set_power_network_sleep(ah, setChip); 2170 ath9k_set_power_network_sleep(ah);
2176 break; 2171 break;
2177 default: 2172 default:
2178 ath_err(common, "Unknown power mode %u\n", mode); 2173 ath_err(common, "Unknown power mode %u\n", mode);