diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2009-04-29 07:01:58 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-05-06 15:14:52 -0400 |
commit | fb4a3d35a26aa8ef5049f10666e6a163b4c32855 (patch) | |
tree | 6222a7edae518828d92584e63a904de1c2dfe922 /drivers/net/wireless/ath/ath9k/hw.c | |
parent | 5cff20e6c5a6591a79d3b027af222870f52bb550 (diff) |
ath9k: uninline ath9k_io{read,write}32 routines
The spin_lock handling uses lots of instructions on some archs.
With this patch the size of the ath9k module will be significantly
smaller.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index ec2a7a40b00d..02f40154e831 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) | |||
84 | return ath9k_hw_mac_clks(ah, usecs); | 84 | return ath9k_hw_mac_clks(ah, usecs); |
85 | } | 85 | } |
86 | 86 | ||
87 | /* | ||
88 | * Read and write, they both share the same lock. We do this to serialize | ||
89 | * reads and writes on Atheros 802.11n PCI devices only. This is required | ||
90 | * as the FIFO on these devices can only accept sanely 2 requests. After | ||
91 | * that the device goes bananas. Serializing the reads/writes prevents this | ||
92 | * from happening. | ||
93 | */ | ||
94 | |||
95 | void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val) | ||
96 | { | ||
97 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | ||
98 | unsigned long flags; | ||
99 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | ||
100 | iowrite32(val, ah->ah_sc->mem + reg_offset); | ||
101 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | ||
102 | } else | ||
103 | iowrite32(val, ah->ah_sc->mem + reg_offset); | ||
104 | } | ||
105 | |||
106 | unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset) | ||
107 | { | ||
108 | u32 val; | ||
109 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | ||
110 | unsigned long flags; | ||
111 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | ||
112 | val = ioread32(ah->ah_sc->mem + reg_offset); | ||
113 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | ||
114 | } else | ||
115 | val = ioread32(ah->ah_sc->mem + reg_offset); | ||
116 | return val; | ||
117 | } | ||
118 | |||
87 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) | 119 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
88 | { | 120 | { |
89 | int i; | 121 | int i; |