diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2009-08-07 00:15:11 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-08-14 09:12:48 -0400 |
commit | c16c9d0657268daaf8a03e7895fb5c5f005285db (patch) | |
tree | a72ffc8d40b52e4eee85abf003e41048dfd8756f /drivers/net/wireless/ath/ath9k/eeprom.h | |
parent | 54e4cec69e70ba30aec68650fb95b3a7e1e6dc18 (diff) |
ath9k: Try to fix whitespace damage
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom.h | 193 |
1 files changed, 94 insertions, 99 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h index db77e90ed9ab..a6447096fd14 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.h +++ b/drivers/net/wireless/ath/ath9k/eeprom.h | |||
@@ -385,106 +385,103 @@ struct calDataPerFreqOpLoop { | |||
385 | } __packed; | 385 | } __packed; |
386 | 386 | ||
387 | struct modal_eep_4k_header { | 387 | struct modal_eep_4k_header { |
388 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; | 388 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; |
389 | u32 antCtrlCommon; | 389 | u32 antCtrlCommon; |
390 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; | 390 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
391 | u8 switchSettling; | 391 | u8 switchSettling; |
392 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; | 392 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; |
393 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; | 393 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; |
394 | u8 adcDesiredSize; | 394 | u8 adcDesiredSize; |
395 | u8 pgaDesiredSize; | 395 | u8 pgaDesiredSize; |
396 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; | 396 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
397 | u8 txEndToXpaOff; | 397 | u8 txEndToXpaOff; |
398 | u8 txEndToRxOn; | 398 | u8 txEndToRxOn; |
399 | u8 txFrameToXpaOn; | 399 | u8 txFrameToXpaOn; |
400 | u8 thresh62; | 400 | u8 thresh62; |
401 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; | 401 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; |
402 | u8 xpdGain; | 402 | u8 xpdGain; |
403 | u8 xpd; | 403 | u8 xpd; |
404 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; | 404 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; |
405 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; | 405 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; |
406 | u8 pdGainOverlap; | 406 | u8 pdGainOverlap; |
407 | u8 ob_01; | 407 | u8 ob_01; |
408 | u8 db1_01; | 408 | u8 db1_01; |
409 | u8 xpaBiasLvl; | 409 | u8 xpaBiasLvl; |
410 | u8 txFrameToDataStart; | 410 | u8 txFrameToDataStart; |
411 | u8 txFrameToPaOn; | 411 | u8 txFrameToPaOn; |
412 | u8 ht40PowerIncForPdadc; | 412 | u8 ht40PowerIncForPdadc; |
413 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; | 413 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; |
414 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; | 414 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; |
415 | u8 swSettleHt40; | 415 | u8 swSettleHt40; |
416 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; | 416 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; |
417 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; | 417 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; |
418 | u8 db2_01; | 418 | u8 db2_01; |
419 | u8 version; | 419 | u8 version; |
420 | u16 ob_234; | 420 | u16 ob_234; |
421 | u16 db1_234; | 421 | u16 db1_234; |
422 | u16 db2_234; | 422 | u16 db2_234; |
423 | u8 futureModal[4]; | 423 | u8 futureModal[4]; |
424 | |||
425 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | 424 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; |
426 | } __packed; | 425 | } __packed; |
427 | 426 | ||
428 | struct base_eep_ar9287_header { | 427 | struct base_eep_ar9287_header { |
429 | u16 length; | 428 | u16 length; |
430 | u16 checksum; | 429 | u16 checksum; |
431 | u16 version; | 430 | u16 version; |
432 | u8 opCapFlags; | 431 | u8 opCapFlags; |
433 | u8 eepMisc; | 432 | u8 eepMisc; |
434 | u16 regDmn[2]; | 433 | u16 regDmn[2]; |
435 | u8 macAddr[6]; | 434 | u8 macAddr[6]; |
436 | u8 rxMask; | 435 | u8 rxMask; |
437 | u8 txMask; | 436 | u8 txMask; |
438 | u16 rfSilent; | 437 | u16 rfSilent; |
439 | u16 blueToothOptions; | 438 | u16 blueToothOptions; |
440 | u16 deviceCap; | 439 | u16 deviceCap; |
441 | u32 binBuildNumber; | 440 | u32 binBuildNumber; |
442 | u8 deviceType; | 441 | u8 deviceType; |
443 | u8 openLoopPwrCntl; | 442 | u8 openLoopPwrCntl; |
444 | int8_t pwrTableOffset; | 443 | int8_t pwrTableOffset; |
445 | int8_t tempSensSlope; | 444 | int8_t tempSensSlope; |
446 | int8_t tempSensSlopePalOn; | 445 | int8_t tempSensSlopePalOn; |
447 | u8 futureBase[29]; | 446 | u8 futureBase[29]; |
448 | } __packed; | 447 | } __packed; |
449 | 448 | ||
450 | struct modal_eep_ar9287_header { | 449 | struct modal_eep_ar9287_header { |
451 | u32 antCtrlChain[AR9287_MAX_CHAINS]; | 450 | u32 antCtrlChain[AR9287_MAX_CHAINS]; |
452 | u32 antCtrlCommon; | 451 | u32 antCtrlCommon; |
453 | int8_t antennaGainCh[AR9287_MAX_CHAINS]; | 452 | int8_t antennaGainCh[AR9287_MAX_CHAINS]; |
454 | u8 switchSettling; | 453 | u8 switchSettling; |
455 | u8 txRxAttenCh[AR9287_MAX_CHAINS]; | 454 | u8 txRxAttenCh[AR9287_MAX_CHAINS]; |
456 | u8 rxTxMarginCh[AR9287_MAX_CHAINS]; | 455 | u8 rxTxMarginCh[AR9287_MAX_CHAINS]; |
457 | int8_t adcDesiredSize; | 456 | int8_t adcDesiredSize; |
458 | u8 txEndToXpaOff; | 457 | u8 txEndToXpaOff; |
459 | u8 txEndToRxOn; | 458 | u8 txEndToRxOn; |
460 | u8 txFrameToXpaOn; | 459 | u8 txFrameToXpaOn; |
461 | u8 thresh62; | 460 | u8 thresh62; |
462 | int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; | 461 | int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; |
463 | u8 xpdGain; | 462 | u8 xpdGain; |
464 | u8 xpd; | 463 | u8 xpd; |
465 | int8_t iqCalICh[AR9287_MAX_CHAINS]; | 464 | int8_t iqCalICh[AR9287_MAX_CHAINS]; |
466 | int8_t iqCalQCh[AR9287_MAX_CHAINS]; | 465 | int8_t iqCalQCh[AR9287_MAX_CHAINS]; |
467 | u8 pdGainOverlap; | 466 | u8 pdGainOverlap; |
468 | u8 xpaBiasLvl; | 467 | u8 xpaBiasLvl; |
469 | u8 txFrameToDataStart; | 468 | u8 txFrameToDataStart; |
470 | u8 txFrameToPaOn; | 469 | u8 txFrameToPaOn; |
471 | u8 ht40PowerIncForPdadc; | 470 | u8 ht40PowerIncForPdadc; |
472 | u8 bswAtten[AR9287_MAX_CHAINS]; | 471 | u8 bswAtten[AR9287_MAX_CHAINS]; |
473 | u8 bswMargin[AR9287_MAX_CHAINS]; | 472 | u8 bswMargin[AR9287_MAX_CHAINS]; |
474 | u8 swSettleHt40; | 473 | u8 swSettleHt40; |
475 | u8 version; | 474 | u8 version; |
476 | u8 db1; | 475 | u8 db1; |
477 | u8 db2; | 476 | u8 db2; |
478 | u8 ob_cck; | 477 | u8 ob_cck; |
479 | u8 ob_psk; | 478 | u8 ob_psk; |
480 | u8 ob_qam; | 479 | u8 ob_qam; |
481 | u8 ob_pal_off; | 480 | u8 ob_pal_off; |
482 | u8 futureModal[30]; | 481 | u8 futureModal[30]; |
483 | struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; | 482 | struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; |
484 | } __packed; | 483 | } __packed; |
485 | 484 | ||
486 | |||
487 | |||
488 | struct cal_data_per_freq { | 485 | struct cal_data_per_freq { |
489 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | 486 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
490 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | 487 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
@@ -525,7 +522,6 @@ struct cal_data_op_loop_ar9287 { | |||
525 | u8 empty[2][5]; | 522 | u8 empty[2][5]; |
526 | } __packed; | 523 | } __packed; |
527 | 524 | ||
528 | |||
529 | struct cal_data_per_freq_ar9287 { | 525 | struct cal_data_per_freq_ar9287 { |
530 | u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 526 | u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
531 | u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 527 | u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
@@ -601,26 +597,25 @@ struct ar5416_eeprom_4k { | |||
601 | } __packed; | 597 | } __packed; |
602 | 598 | ||
603 | struct ar9287_eeprom { | 599 | struct ar9287_eeprom { |
604 | struct base_eep_ar9287_header baseEepHeader; | 600 | struct base_eep_ar9287_header baseEepHeader; |
605 | u8 custData[AR9287_DATA_SZ]; | 601 | u8 custData[AR9287_DATA_SZ]; |
606 | struct modal_eep_ar9287_header modalHeader; | 602 | struct modal_eep_ar9287_header modalHeader; |
607 | u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; | 603 | u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; |
608 | union cal_data_per_freq_ar9287_u | 604 | union cal_data_per_freq_ar9287_u |
609 | calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; | 605 | calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; |
610 | struct cal_target_power_leg | 606 | struct cal_target_power_leg |
611 | calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; | 607 | calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; |
612 | struct cal_target_power_leg | 608 | struct cal_target_power_leg |
613 | calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; | 609 | calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; |
614 | struct cal_target_power_ht | 610 | struct cal_target_power_ht |
615 | calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; | 611 | calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; |
616 | struct cal_target_power_ht | 612 | struct cal_target_power_ht |
617 | calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; | 613 | calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; |
618 | u8 ctlIndex[AR9287_NUM_CTLS]; | 614 | u8 ctlIndex[AR9287_NUM_CTLS]; |
619 | struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; | 615 | struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; |
620 | u8 padding; | 616 | u8 padding; |
621 | } __packed; | 617 | } __packed; |
622 | 618 | ||
623 | |||
624 | enum reg_ext_bitmap { | 619 | enum reg_ext_bitmap { |
625 | REG_EXT_JAPAN_MIDBAND = 1, | 620 | REG_EXT_JAPAN_MIDBAND = 1, |
626 | REG_EXT_FCC_DFS_HT40 = 2, | 621 | REG_EXT_FCC_DFS_HT40 = 2, |