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authorVasanthakumar Thiagarajan <vasanth@atheros.com>2009-05-08 20:54:51 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-05-11 15:24:05 -0400
commit8fbff4b838c53945d6baeafe609c627000f85cd6 (patch)
tree933100908a181acf99aea104b13db17073303113 /drivers/net/wireless/ath/ath9k/eeprom.c
parent19eddca67628e5fb722e4ebbbba8c307a884d0e8 (diff)
ath9k: Cleanup ineffective return values
This patch makes the return type of some of the functions void as those functions always return true Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c51
1 files changed, 12 insertions, 39 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 44fee5ae8925..a2fda702b620 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -694,7 +694,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
694#undef TMP_VAL_VPD_TABLE 694#undef TMP_VAL_VPD_TABLE
695} 695}
696 696
697static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 697static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
698 struct ath9k_channel *chan, 698 struct ath9k_channel *chan,
699 int16_t *pTxPowerIndexOffset) 699 int16_t *pTxPowerIndexOffset)
700{ 700{
@@ -805,11 +805,9 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
805 } 805 }
806 806
807 *pTxPowerIndexOffset = 0; 807 *pTxPowerIndexOffset = 0;
808
809 return true;
810} 808}
811 809
812static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, 810static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
813 struct ath9k_channel *chan, 811 struct ath9k_channel *chan,
814 int16_t *ratesArray, 812 int16_t *ratesArray,
815 u16 cfgCtl, 813 u16 cfgCtl,
@@ -1041,10 +1039,9 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
1041 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 1039 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1042 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 1040 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1043 } 1041 }
1044 return true;
1045} 1042}
1046 1043
1047static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, 1044static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1048 struct ath9k_channel *chan, 1045 struct ath9k_channel *chan,
1049 u16 cfgCtl, 1046 u16 cfgCtl,
1050 u8 twiceAntennaReduction, 1047 u8 twiceAntennaReduction,
@@ -1065,22 +1062,13 @@ static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1065 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1062 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1066 } 1063 }
1067 1064
1068 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, 1065 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1069 &ratesArray[0], cfgCtl, 1066 &ratesArray[0], cfgCtl,
1070 twiceAntennaReduction, 1067 twiceAntennaReduction,
1071 twiceMaxRegulatoryPower, 1068 twiceMaxRegulatoryPower,
1072 powerLimit)) { 1069 powerLimit);
1073 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1074 "ath9k_hw_set_txpower: unable to set "
1075 "tx power per rate table\n");
1076 return -EIO;
1077 }
1078 1070
1079 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { 1071 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
1080 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1081 "ath9k_hw_set_txpower: unable to set power table\n");
1082 return -EIO;
1083 }
1084 1072
1085 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1073 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1086 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1074 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
@@ -1168,7 +1156,6 @@ static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1168 else 1156 else
1169 ah->regulatory.max_power_level = ratesArray[i]; 1157 ah->regulatory.max_power_level = ratesArray[i];
1170 1158
1171 return 0;
1172} 1159}
1173 1160
1174static void ath9k_hw_4k_set_addac(struct ath_hw *ah, 1161static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
@@ -2103,7 +2090,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
2103 return; 2090 return;
2104} 2091}
2105 2092
2106static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 2093static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2107 struct ath9k_channel *chan, 2094 struct ath9k_channel *chan,
2108 int16_t *pTxPowerIndexOffset) 2095 int16_t *pTxPowerIndexOffset)
2109{ 2096{
@@ -2255,13 +2242,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2255 } 2242 }
2256 2243
2257 *pTxPowerIndexOffset = 0; 2244 *pTxPowerIndexOffset = 0;
2258
2259 return true;
2260#undef SM_PD_GAIN 2245#undef SM_PD_GAIN
2261#undef SM_PDGAIN_B 2246#undef SM_PDGAIN_B
2262} 2247}
2263 2248
2264static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, 2249static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2265 struct ath9k_channel *chan, 2250 struct ath9k_channel *chan,
2266 int16_t *ratesArray, 2251 int16_t *ratesArray,
2267 u16 cfgCtl, 2252 u16 cfgCtl,
@@ -2549,10 +2534,9 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2549 targetPowerCckExt.tPow2x[0]; 2534 targetPowerCckExt.tPow2x[0];
2550 } 2535 }
2551 } 2536 }
2552 return true;
2553} 2537}
2554 2538
2555static int ath9k_hw_def_set_txpower(struct ath_hw *ah, 2539static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
2556 struct ath9k_channel *chan, 2540 struct ath9k_channel *chan,
2557 u16 cfgCtl, 2541 u16 cfgCtl,
2558 u8 twiceAntennaReduction, 2542 u8 twiceAntennaReduction,
@@ -2575,22 +2559,13 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2575 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 2559 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2576 } 2560 }
2577 2561
2578 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, 2562 ath9k_hw_set_def_power_per_rate_table(ah, chan,
2579 &ratesArray[0], cfgCtl, 2563 &ratesArray[0], cfgCtl,
2580 twiceAntennaReduction, 2564 twiceAntennaReduction,
2581 twiceMaxRegulatoryPower, 2565 twiceMaxRegulatoryPower,
2582 powerLimit)) { 2566 powerLimit);
2583 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2584 "ath9k_hw_set_txpower: unable to set "
2585 "tx power per rate table\n");
2586 return -EIO;
2587 }
2588 2567
2589 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { 2568 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
2590 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2591 "ath9k_hw_set_txpower: unable to set power table\n");
2592 return -EIO;
2593 }
2594 2569
2595 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 2570 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2596 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 2571 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
@@ -2717,8 +2692,6 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2717 "Invalid chainmask configuration\n"); 2692 "Invalid chainmask configuration\n");
2718 break; 2693 break;
2719 } 2694 }
2720
2721 return 0;
2722} 2695}
2723 2696
2724static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, 2697static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,