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authorLuis R. Rodriguez <lrodriguez@atheros.com>2009-09-09 17:52:02 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-10-07 16:39:22 -0400
commit766ec4a9a813ae262b61842020f150f865c1b10a (patch)
treed02074b1242ef41d0e144515a4bf9074f022e61c /drivers/net/wireless/ath/ath9k/btcoex.c
parent46289e1e5f2155ba1502b079e786e91755919823 (diff)
ath9k: rename ath_btcoex_info to ath_btcoex_hw
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/btcoex.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index aa0ec2c2f326..0b5a7d4a6d55 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -43,13 +43,13 @@ bool ath_btcoex_supported(u16 subsysid)
43 return false; 43 return false;
44} 44}
45 45
46void ath9k_hw_init_btcoex_hw_info(struct ath_hw *ah, int qnum) 46void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
47{ 47{
48 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 48 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
49 u32 i; 49 u32 i;
50 50
51 btcoex_info->bt_coex_mode = 51 btcoex_hw->bt_coex_mode =
52 (btcoex_info->bt_coex_mode & AR_BT_QCU_THRESH) | 52 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
53 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | 53 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
54 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 54 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
55 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 55 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
@@ -60,7 +60,7 @@ void ath9k_hw_init_btcoex_hw_info(struct ath_hw *ah, int qnum)
60 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | 60 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
61 SM(qnum, AR_BT_QCU_THRESH); 61 SM(qnum, AR_BT_QCU_THRESH);
62 62
63 btcoex_info->bt_coex_mode2 = 63 btcoex_hw->bt_coex_mode2 =
64 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | 64 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
65 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | 65 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
66 AR_BT_DISABLE_BT_ANT; 66 AR_BT_DISABLE_BT_ANT;
@@ -71,7 +71,7 @@ void ath9k_hw_init_btcoex_hw_info(struct ath_hw *ah, int qnum)
71 71
72void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah) 72void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
73{ 73{
74 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 74 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
75 75
76 /* connect bt_active to baseband */ 76 /* connect bt_active to baseband */
77 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 77 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -84,15 +84,15 @@ void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
84 /* Set input mux for bt_active to gpio pin */ 84 /* Set input mux for bt_active to gpio pin */
85 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 85 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
86 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 86 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
87 btcoex_info->btactive_gpio); 87 btcoex_hw->btactive_gpio);
88 88
89 /* Configure the desired gpio port for input */ 89 /* Configure the desired gpio port for input */
90 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio); 90 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
91} 91}
92 92
93void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah) 93void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
94{ 94{
95 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 95 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
96 96
97 /* btcoex 3-wire */ 97 /* btcoex 3-wire */
98 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 98 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -103,51 +103,51 @@ void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
103 * bt_active_async to GPIO pins */ 103 * bt_active_async to GPIO pins */
104 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 104 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
105 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 105 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
106 btcoex_info->btactive_gpio); 106 btcoex_hw->btactive_gpio);
107 107
108 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 108 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
109 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 109 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
110 btcoex_info->btpriority_gpio); 110 btcoex_hw->btpriority_gpio);
111 111
112 /* Configure the desired GPIO ports for input */ 112 /* Configure the desired GPIO ports for input */
113 113
114 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio); 114 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
115 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio); 115 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
116} 116}
117 117
118static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah) 118static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
119{ 119{
120 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 120 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
121 121
122 /* Configure the desired GPIO port for TX_FRAME output */ 122 /* Configure the desired GPIO port for TX_FRAME output */
123 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio, 123 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
124 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 124 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
125} 125}
126 126
127static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah) 127static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
128{ 128{
129 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 129 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
130 130
131 /* 131 /*
132 * Program coex mode and weight registers to 132 * Program coex mode and weight registers to
133 * enable coex 3-wire 133 * enable coex 3-wire
134 */ 134 */
135 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_info->bt_coex_mode); 135 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
136 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights); 136 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
137 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2); 137 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
138 138
139 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 139 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
140 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 140 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
141 141
142 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio, 142 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
143 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 143 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
144} 144}
145 145
146void ath9k_hw_btcoex_enable(struct ath_hw *ah) 146void ath9k_hw_btcoex_enable(struct ath_hw *ah)
147{ 147{
148 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 148 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
149 149
150 switch (btcoex_info->scheme) { 150 switch (btcoex_hw->scheme) {
151 case ATH_BTCOEX_CFG_NONE: 151 case ATH_BTCOEX_CFG_NONE:
152 break; 152 break;
153 case ATH_BTCOEX_CFG_2WIRE: 153 case ATH_BTCOEX_CFG_2WIRE:
@@ -159,26 +159,26 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah)
159 } 159 }
160 160
161 REG_RMW(ah, AR_GPIO_PDPU, 161 REG_RMW(ah, AR_GPIO_PDPU,
162 (0x2 << (btcoex_info->btactive_gpio * 2)), 162 (0x2 << (btcoex_hw->btactive_gpio * 2)),
163 (0x3 << (btcoex_info->btactive_gpio * 2))); 163 (0x3 << (btcoex_hw->btactive_gpio * 2)));
164 164
165 ah->btcoex_info.enabled = true; 165 ah->btcoex_hw.enabled = true;
166} 166}
167 167
168void ath9k_hw_btcoex_disable(struct ath_hw *ah) 168void ath9k_hw_btcoex_disable(struct ath_hw *ah)
169{ 169{
170 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 170 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
171 171
172 ath9k_hw_set_gpio(ah, btcoex_info->wlanactive_gpio, 0); 172 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
173 173
174 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio, 174 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
175 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 175 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
176 176
177 if (btcoex_info->scheme == ATH_BTCOEX_CFG_3WIRE) { 177 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
178 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 178 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
179 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0); 179 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
180 REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 180 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
181 } 181 }
182 182
183 ah->btcoex_info.enabled = false; 183 ah->btcoex_hw.enabled = false;
184} 184}