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authorSenthil Balasubramanian <senthilkumar@atheros.com>2009-07-14 20:17:09 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-07-24 15:05:18 -0400
commit164ace38536849966ffa377b1b1132993a5a375d (patch)
tree91819800dcfaab603a7d44c148ccf32c13640fd8 /drivers/net/wireless/ath/ath9k/ath9k.h
parentdd8b15b027d96f7097ae9dbaebd822a114a03c34 (diff)
ath9k: Fix TX hang issue with Atheros chipsets
The hardware doesn't generate interrupts in some cases and so work around this by monitoring the TX status periodically and reset the chip if required. This behavior of the hardware not generating the TX interrupts can be noticed through ath9k debugfs interrupt statistics when heavy traffic is being sent from STA to AP. One can easily see this behavior when the STA is transmitting at a higher rates. The interrupt statistics in the debugfs interface clearly shows that only RX interrupts alone being generated and TX being stuck. TX should be monitored through a timer and reset the chip only when frames are queued to the hardware but TX interrupts are not generated for the same even after one second. Also, we shouldn't remove holding descriptor from AC queue if it happens to be the only descriptor and schedule TX aggregation regarless of queue depth as it improves scheduling of AMPDUs from software to hardware queue. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ath9k.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 544599b826c1..20bf4a7f896d 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -225,6 +225,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
225#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) 225#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
226#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 226#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
227 227
228#define ATH_TX_COMPLETE_POLL_INT 1000
229
228enum ATH_AGGR_STATUS { 230enum ATH_AGGR_STATUS {
229 ATH_AGGR_DONE, 231 ATH_AGGR_DONE,
230 ATH_AGGR_BAW_CLOSED, 232 ATH_AGGR_BAW_CLOSED,
@@ -240,6 +242,7 @@ struct ath_txq {
240 u8 axq_aggr_depth; 242 u8 axq_aggr_depth;
241 u32 axq_totalqueued; 243 u32 axq_totalqueued;
242 bool stopped; 244 bool stopped;
245 bool axq_tx_inprogress;
243 struct ath_buf *axq_linkbuf; 246 struct ath_buf *axq_linkbuf;
244 247
245 /* first desc of the last descriptor that contains CTS */ 248 /* first desc of the last descriptor that contains CTS */
@@ -605,6 +608,7 @@ struct ath_softc {
605#endif 608#endif
606 struct ath_bus_ops *bus_ops; 609 struct ath_bus_ops *bus_ops;
607 struct ath_beacon_config cur_beacon_conf; 610 struct ath_beacon_config cur_beacon_conf;
611 struct delayed_work tx_complete_work;
608}; 612};
609 613
610struct ath_wiphy { 614struct ath_wiphy {