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authorDavid S. Miller <davem@davemloft.net>2010-03-22 21:15:15 -0400
committerDavid S. Miller <davem@davemloft.net>2010-03-22 21:15:15 -0400
commit33e2bf6aa16061bae1253514e7c32af27d2b4b31 (patch)
tree652d13b4feea9a8f562186e7badae72d2e22fe1f /drivers/net/wireless/ath/ath5k
parente880eb6c5c9d98e389ffc0d8947f75d70785361a (diff)
parent819bfecc4fc6b6e5a793f719a45b7146ce423b79 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Conflicts: Documentation/feature-removal-schedule.txt drivers/net/wireless/ath/ath5k/phy.c
Diffstat (limited to 'drivers/net/wireless/ath/ath5k')
-rw-r--r--drivers/net/wireless/ath/ath5k/ath5k.h257
-rw-r--r--drivers/net/wireless/ath/ath5k/attach.c5
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c150
-rw-r--r--drivers/net/wireless/ath/ath5k/base.h20
-rw-r--r--drivers/net/wireless/ath/ath5k/caps.c3
-rw-r--r--drivers/net/wireless/ath/ath5k/debug.c212
-rw-r--r--drivers/net/wireless/ath/ath5k/debug.h2
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.c18
-rw-r--r--drivers/net/wireless/ath/ath5k/eeprom.c4
-rw-r--r--drivers/net/wireless/ath/ath5k/eeprom.h88
-rw-r--r--drivers/net/wireless/ath/ath5k/pcu.c306
-rw-r--r--drivers/net/wireless/ath/ath5k/phy.c38
-rw-r--r--drivers/net/wireless/ath/ath5k/qcu.c17
-rw-r--r--drivers/net/wireless/ath/ath5k/reg.h2
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c38
15 files changed, 568 insertions, 592 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index ac67f02e26d8..1d7491c85460 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -202,7 +202,6 @@
202#define AR5K_TUNE_MAX_TXPOWER 63 202#define AR5K_TUNE_MAX_TXPOWER 63
203#define AR5K_TUNE_DEFAULT_TXPOWER 25 203#define AR5K_TUNE_DEFAULT_TXPOWER 25
204#define AR5K_TUNE_TPC_TXPOWER false 204#define AR5K_TUNE_TPC_TXPOWER false
205#define AR5K_TUNE_HWTXTRIES 4
206 205
207#define AR5K_INIT_CARR_SENSE_EN 1 206#define AR5K_INIT_CARR_SENSE_EN 1
208 207
@@ -614,28 +613,6 @@ struct ath5k_rx_status {
614#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 613#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
615#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 614#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
616 615
617#if 0
618/**
619 * struct ath5k_beacon_state - Per-station beacon timer state.
620 * @bs_interval: in TU's, can also include the above flags
621 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
622 * Point Coordination Function capable AP
623 */
624struct ath5k_beacon_state {
625 u32 bs_next_beacon;
626 u32 bs_next_dtim;
627 u32 bs_interval;
628 u8 bs_dtim_period;
629 u8 bs_cfp_period;
630 u16 bs_cfp_max_duration;
631 u16 bs_cfp_du_remain;
632 u16 bs_tim_offset;
633 u16 bs_sleep_duration;
634 u16 bs_bmiss_threshold;
635 u32 bs_cfp_next;
636};
637#endif
638
639 616
640/* 617/*
641 * TSF to TU conversion: 618 * TSF to TU conversion:
@@ -1028,7 +1005,6 @@ struct ath5k_nfcal_hist
1028 1005
1029/* TODO: Clean up and merge with ath5k_softc */ 1006/* TODO: Clean up and merge with ath5k_softc */
1030struct ath5k_hw { 1007struct ath5k_hw {
1031 u32 ah_magic;
1032 struct ath_common common; 1008 struct ath_common common;
1033 1009
1034 struct ath5k_softc *ah_sc; 1010 struct ath5k_softc *ah_sc;
@@ -1036,7 +1012,6 @@ struct ath5k_hw {
1036 1012
1037 enum ath5k_int ah_imr; 1013 enum ath5k_int ah_imr;
1038 1014
1039 enum nl80211_iftype ah_op_mode;
1040 struct ieee80211_channel *ah_current_channel; 1015 struct ieee80211_channel *ah_current_channel;
1041 bool ah_turbo; 1016 bool ah_turbo;
1042 bool ah_calibration; 1017 bool ah_calibration;
@@ -1049,7 +1024,6 @@ struct ath5k_hw {
1049 u32 ah_phy; 1024 u32 ah_phy;
1050 u32 ah_mac_srev; 1025 u32 ah_mac_srev;
1051 u16 ah_mac_version; 1026 u16 ah_mac_version;
1052 u16 ah_mac_revision;
1053 u16 ah_phy_revision; 1027 u16 ah_phy_revision;
1054 u16 ah_radio_5ghz_revision; 1028 u16 ah_radio_5ghz_revision;
1055 u16 ah_radio_2ghz_revision; 1029 u16 ah_radio_2ghz_revision;
@@ -1071,8 +1045,6 @@ struct ath5k_hw {
1071 u8 ah_def_ant; 1045 u8 ah_def_ant;
1072 bool ah_software_retry; 1046 bool ah_software_retry;
1073 1047
1074 int ah_gpio_npins;
1075
1076 struct ath5k_capabilities ah_capabilities; 1048 struct ath5k_capabilities ah_capabilities;
1077 1049
1078 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1050 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
@@ -1141,9 +1113,9 @@ struct ath5k_hw {
1141 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc, 1113 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1142 u32 size, unsigned int flags); 1114 u32 size, unsigned int flags);
1143 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1115 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1144 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, 1116 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1145 unsigned int, unsigned int, unsigned int, unsigned int, 1117 unsigned int, unsigned int, unsigned int, unsigned int,
1146 unsigned int, unsigned int, unsigned int); 1118 unsigned int, unsigned int, unsigned int, unsigned int);
1147 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1119 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1148 unsigned int, unsigned int, unsigned int, unsigned int, 1120 unsigned int, unsigned int, unsigned int, unsigned int,
1149 unsigned int, unsigned int); 1121 unsigned int, unsigned int);
@@ -1158,158 +1130,147 @@ struct ath5k_hw {
1158 */ 1130 */
1159 1131
1160/* Attach/Detach Functions */ 1132/* Attach/Detach Functions */
1161extern int ath5k_hw_attach(struct ath5k_softc *sc); 1133int ath5k_hw_attach(struct ath5k_softc *sc);
1162extern void ath5k_hw_detach(struct ath5k_hw *ah); 1134void ath5k_hw_detach(struct ath5k_hw *ah);
1163 1135
1164/* LED functions */ 1136/* LED functions */
1165extern int ath5k_init_leds(struct ath5k_softc *sc); 1137int ath5k_init_leds(struct ath5k_softc *sc);
1166extern void ath5k_led_enable(struct ath5k_softc *sc); 1138void ath5k_led_enable(struct ath5k_softc *sc);
1167extern void ath5k_led_off(struct ath5k_softc *sc); 1139void ath5k_led_off(struct ath5k_softc *sc);
1168extern void ath5k_unregister_leds(struct ath5k_softc *sc); 1140void ath5k_unregister_leds(struct ath5k_softc *sc);
1169 1141
1170/* Reset Functions */ 1142/* Reset Functions */
1171extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1143int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1172extern int ath5k_hw_on_hold(struct ath5k_hw *ah); 1144int ath5k_hw_on_hold(struct ath5k_hw *ah);
1173extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel); 1145int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1146 struct ieee80211_channel *channel, bool change_channel);
1147int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1148 bool is_set);
1174/* Power management functions */ 1149/* Power management functions */
1175extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1176 1150
1177/* DMA Related Functions */ 1151/* DMA Related Functions */
1178extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1152void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1179extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); 1153int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1180extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1154u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1181extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1155void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1182extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1156int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1183extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1157int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1184extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1158u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1185extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1159int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1186 u32 phys_addr); 1160 u32 phys_addr);
1187extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1161int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1188/* Interrupt handling */ 1162/* Interrupt handling */
1189extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1163bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1190extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1164int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1191extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum 1165enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1192ath5k_int new_mask); 1166void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
1193extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats); 1167 struct ieee80211_low_level_stats *stats);
1194 1168
1195/* EEPROM access functions */ 1169/* EEPROM access functions */
1196extern int ath5k_eeprom_init(struct ath5k_hw *ah); 1170int ath5k_eeprom_init(struct ath5k_hw *ah);
1197extern void ath5k_eeprom_detach(struct ath5k_hw *ah); 1171void ath5k_eeprom_detach(struct ath5k_hw *ah);
1198extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1172int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1199extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
1200 1173
1201/* Protocol Control Unit Functions */ 1174/* Protocol Control Unit Functions */
1202extern int ath5k_hw_set_opmode(struct ath5k_hw *ah); 1175extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1203extern void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1176void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1204/* BSSID Functions */ 1177/* BSSID Functions */
1205extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1178int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1206extern void ath5k_hw_set_associd(struct ath5k_hw *ah); 1179void ath5k_hw_set_associd(struct ath5k_hw *ah);
1207extern void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1180void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1208/* Receive start/stop functions */ 1181/* Receive start/stop functions */
1209extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1182void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1210extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1183void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1211/* RX Filter functions */ 1184/* RX Filter functions */
1212extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1185void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1213extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1186u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1214extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1187void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1215extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1216extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1217/* Beacon control functions */ 1188/* Beacon control functions */
1218extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah); 1189u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1219extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1190void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1220extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1191void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1221extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1192void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1222extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1223#if 0
1224extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1225extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1226extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1227#endif
1228/* ACK bit rate */ 1193/* ACK bit rate */
1229void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1194void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1230/* ACK/CTS Timeouts */
1231extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1232extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1233extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1234extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1235/* Clock rate related functions */ 1195/* Clock rate related functions */
1236unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1196unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1237unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1197unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1238unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah); 1198unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
1239/* Key table (WEP) functions */ 1199/* Key table (WEP) functions */
1240extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry); 1200int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1241extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry); 1201int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
1242extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); 1202 const struct ieee80211_key_conf *key, const u8 *mac);
1243extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac); 1203int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1244 1204
1245/* Queue Control Unit, DFS Control Unit Functions */ 1205/* Queue Control Unit, DFS Control Unit Functions */
1246extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info); 1206int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1247extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1207 struct ath5k_txq_info *queue_info);
1248 const struct ath5k_txq_info *queue_info); 1208int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1249extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1209 const struct ath5k_txq_info *queue_info);
1250 enum ath5k_tx_queue queue_type, 1210int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1251 struct ath5k_txq_info *queue_info); 1211 enum ath5k_tx_queue queue_type,
1252extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1212 struct ath5k_txq_info *queue_info);
1253extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1213u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1254extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1214void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1255extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah); 1215int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1256extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1216int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1257 1217
1258/* Hardware Descriptor Functions */ 1218/* Hardware Descriptor Functions */
1259extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1219int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1260 1220
1261/* GPIO Functions */ 1221/* GPIO Functions */
1262extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1222void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1263extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1223int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1264extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1224int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1265extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1225u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1266extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1226int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1267extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); 1227void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1228 u32 interrupt_level);
1268 1229
1269/* rfkill Functions */ 1230/* rfkill Functions */
1270extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1231void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1271extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1232void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1272 1233
1273/* Misc functions */ 1234/* Misc functions */
1274int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1235int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1275extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); 1236int ath5k_hw_get_capability(struct ath5k_hw *ah,
1276extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1237 enum ath5k_capability_type cap_type, u32 capability,
1277extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1238 u32 *result);
1239int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1240int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1278 1241
1279/* Initial register settings functions */ 1242/* Initial register settings functions */
1280extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1243int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1281 1244
1282/* Initialize RF */ 1245/* Initialize RF */
1283extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 1246int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1284 struct ieee80211_channel *channel, 1247 struct ieee80211_channel *channel,
1285 unsigned int mode); 1248 unsigned int mode);
1286extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); 1249int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1287extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1250enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1288extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1251int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1289/* PHY/RF channel functions */ 1252/* PHY/RF channel functions */
1290extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1253bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1291extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1254int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1292/* PHY calibration */ 1255/* PHY calibration */
1293void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1256void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1294extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1257int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1295extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq); 1258 struct ieee80211_channel *channel);
1296extern s16 ath5k_hw_get_noise_floor(struct ath5k_hw *ah); 1259void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
1297extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
1298/* Spur mitigation */ 1260/* Spur mitigation */
1299bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1261bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1300 struct ieee80211_channel *channel); 1262 struct ieee80211_channel *channel);
1301void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1263void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1302 struct ieee80211_channel *channel); 1264 struct ieee80211_channel *channel);
1303/* Misc PHY functions */ 1265/* Misc PHY functions */
1304extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1266u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1305extern int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1267int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1306/* Antenna control */ 1268/* Antenna control */
1307extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1269void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1308extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
1309extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1310/* TX power setup */ 1270/* TX power setup */
1311extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower); 1271int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1312extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1272 u8 ee_mode, u8 txpower);
1273int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1313 1274
1314/* 1275/*
1315 * Functions used internaly 1276 * Functions used internaly
@@ -1335,29 +1296,6 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1335 iowrite32(val, ah->ah_iobase + reg); 1296 iowrite32(val, ah->ah_iobase + reg);
1336} 1297}
1337 1298
1338#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1339/*
1340 * Check if a register write has been completed
1341 */
1342static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1343 u32 val, bool is_set)
1344{
1345 int i;
1346 u32 data;
1347
1348 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1349 data = ath5k_hw_reg_read(ah, reg);
1350 if (is_set && (data & flag))
1351 break;
1352 else if ((data & flag) == val)
1353 break;
1354 udelay(15);
1355 }
1356
1357 return (i <= 0) ? -EAGAIN : 0;
1358}
1359#endif
1360
1361static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1299static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1362{ 1300{
1363 u32 retval = 0, bit, i; 1301 u32 retval = 0, bit, i;
@@ -1370,9 +1308,4 @@ static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1370 return retval; 1308 return retval;
1371} 1309}
1372 1310
1373static inline int ath5k_pad_size(int hdrlen)
1374{
1375 return (hdrlen < 24) ? 0 : hdrlen & 3;
1376}
1377
1378#endif 1311#endif
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index 42284445b75e..dd4099a2ff15 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -113,7 +113,6 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
113 /* 113 /*
114 * HW information 114 * HW information
115 */ 115 */
116 ah->ah_op_mode = NL80211_IFTYPE_STATION;
117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 116 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
118 ah->ah_turbo = false; 117 ah->ah_turbo = false;
119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 118 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
@@ -123,6 +122,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
123 ah->ah_cw_min = AR5K_TUNE_CWMIN; 122 ah->ah_cw_min = AR5K_TUNE_CWMIN;
124 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 123 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
125 ah->ah_software_retry = false; 124 ah->ah_software_retry = false;
125 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
126 126
127 /* 127 /*
128 * Find the mac version 128 * Find the mac version
@@ -148,7 +148,6 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
148 /* Get MAC, PHY and RADIO revisions */ 148 /* Get MAC, PHY and RADIO revisions */
149 ah->ah_mac_srev = srev; 149 ah->ah_mac_srev = srev;
150 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); 150 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
151 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
152 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & 151 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
153 0xffffffff; 152 0xffffffff;
154 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, 153 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
@@ -327,7 +326,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
327 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ 326 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
328 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN); 327 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
329 ath5k_hw_set_associd(ah); 328 ath5k_hw_set_associd(ah);
330 ath5k_hw_set_opmode(ah); 329 ath5k_hw_set_opmode(ah, sc->opmode);
331 330
332 ath5k_hw_rfgain_opt_init(ah); 331 ath5k_hw_rfgain_opt_init(ah);
333 332
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 8dce0077b023..b142a78ed1e5 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -198,7 +198,7 @@ static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198static int ath5k_pci_suspend(struct device *dev); 198static int ath5k_pci_suspend(struct device *dev);
199static int ath5k_pci_resume(struct device *dev); 199static int ath5k_pci_resume(struct device *dev);
200 200
201SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 201static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202#define ATH5K_PM_OPS (&ath5k_pm_ops) 202#define ATH5K_PM_OPS (&ath5k_pm_ops)
203#else 203#else
204#define ATH5K_PM_OPS NULL 204#define ATH5K_PM_OPS NULL
@@ -307,7 +307,7 @@ static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf); 307 struct ath5k_buf *bf);
308static int ath5k_txbuf_setup(struct ath5k_softc *sc, 308static int ath5k_txbuf_setup(struct ath5k_softc *sc,
309 struct ath5k_buf *bf, 309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq); 310 struct ath5k_txq *txq, int padsize);
311static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 311static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf) 312 struct ath5k_buf *bf)
313{ 313{
@@ -1137,8 +1137,6 @@ ath5k_mode_setup(struct ath5k_softc *sc)
1137 struct ath5k_hw *ah = sc->ah; 1137 struct ath5k_hw *ah = sc->ah;
1138 u32 rfilt; 1138 u32 rfilt;
1139 1139
1140 ah->ah_op_mode = sc->opmode;
1141
1142 /* configure rx filter */ 1140 /* configure rx filter */
1143 rfilt = sc->filter_flags; 1141 rfilt = sc->filter_flags;
1144 ath5k_hw_set_rx_filter(ah, rfilt); 1142 ath5k_hw_set_rx_filter(ah, rfilt);
@@ -1147,8 +1145,9 @@ ath5k_mode_setup(struct ath5k_softc *sc)
1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1145 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148 1146
1149 /* configure operational mode */ 1147 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah); 1148 ath5k_hw_set_opmode(ah, sc->opmode);
1151 1149
1150 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1151 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1153} 1152}
1154 1153
@@ -1271,7 +1270,7 @@ static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1271 1270
1272static int 1271static int
1273ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1272ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1274 struct ath5k_txq *txq) 1273 struct ath5k_txq *txq, int padsize)
1275{ 1274{
1276 struct ath5k_hw *ah = sc->ah; 1275 struct ath5k_hw *ah = sc->ah;
1277 struct ath5k_desc *ds = bf->desc; 1276 struct ath5k_desc *ds = bf->desc;
@@ -1323,7 +1322,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1323 sc->vif, pktlen, info)); 1322 sc->vif, pktlen, info));
1324 } 1323 }
1325 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1324 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1326 ieee80211_get_hdrlen_from_skb(skb), 1325 ieee80211_get_hdrlen_from_skb(skb), padsize,
1327 get_hw_packet_type(skb), 1326 get_hw_packet_type(skb),
1328 (sc->power_level * 2), 1327 (sc->power_level * 2),
1329 hw_rate, 1328 hw_rate,
@@ -1805,6 +1804,67 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1805 } 1804 }
1806} 1805}
1807 1806
1807/*
1808 * Compute padding position. skb must contains an IEEE 802.11 frame
1809 */
1810static int ath5k_common_padpos(struct sk_buff *skb)
1811{
1812 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1813 __le16 frame_control = hdr->frame_control;
1814 int padpos = 24;
1815
1816 if (ieee80211_has_a4(frame_control)) {
1817 padpos += ETH_ALEN;
1818 }
1819 if (ieee80211_is_data_qos(frame_control)) {
1820 padpos += IEEE80211_QOS_CTL_LEN;
1821 }
1822
1823 return padpos;
1824}
1825
1826/*
1827 * This function expects a 802.11 frame and returns the number of
1828 * bytes added, or -1 if we don't have enought header room.
1829 */
1830
1831static int ath5k_add_padding(struct sk_buff *skb)
1832{
1833 int padpos = ath5k_common_padpos(skb);
1834 int padsize = padpos & 3;
1835
1836 if (padsize && skb->len>padpos) {
1837
1838 if (skb_headroom(skb) < padsize)
1839 return -1;
1840
1841 skb_push(skb, padsize);
1842 memmove(skb->data, skb->data+padsize, padpos);
1843 return padsize;
1844 }
1845
1846 return 0;
1847}
1848
1849/*
1850 * This function expects a 802.11 frame and returns the number of
1851 * bytes removed
1852 */
1853
1854static int ath5k_remove_padding(struct sk_buff *skb)
1855{
1856 int padpos = ath5k_common_padpos(skb);
1857 int padsize = padpos & 3;
1858
1859 if (padsize && skb->len>=padpos+padsize) {
1860 memmove(skb->data + padsize, skb->data, padpos);
1861 skb_pull(skb, padsize);
1862 return padsize;
1863 }
1864
1865 return 0;
1866}
1867
1808static void 1868static void
1809ath5k_tasklet_rx(unsigned long data) 1869ath5k_tasklet_rx(unsigned long data)
1810{ 1870{
@@ -1818,8 +1878,6 @@ ath5k_tasklet_rx(unsigned long data)
1818 struct ath5k_buf *bf; 1878 struct ath5k_buf *bf;
1819 struct ath5k_desc *ds; 1879 struct ath5k_desc *ds;
1820 int ret; 1880 int ret;
1821 int hdrlen;
1822 int padsize;
1823 int rx_flag; 1881 int rx_flag;
1824 1882
1825 spin_lock(&sc->rxbuflock); 1883 spin_lock(&sc->rxbuflock);
@@ -1844,18 +1902,28 @@ ath5k_tasklet_rx(unsigned long data)
1844 break; 1902 break;
1845 else if (unlikely(ret)) { 1903 else if (unlikely(ret)) {
1846 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1904 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1905 sc->stats.rxerr_proc++;
1847 spin_unlock(&sc->rxbuflock); 1906 spin_unlock(&sc->rxbuflock);
1848 return; 1907 return;
1849 } 1908 }
1850 1909
1910 sc->stats.rx_all_count++;
1911
1851 if (unlikely(rs.rs_more)) { 1912 if (unlikely(rs.rs_more)) {
1852 ATH5K_WARN(sc, "unsupported jumbo\n"); 1913 ATH5K_WARN(sc, "unsupported jumbo\n");
1914 sc->stats.rxerr_jumbo++;
1853 goto next; 1915 goto next;
1854 } 1916 }
1855 1917
1856 if (unlikely(rs.rs_status)) { 1918 if (unlikely(rs.rs_status)) {
1857 if (rs.rs_status & AR5K_RXERR_PHY) 1919 if (rs.rs_status & AR5K_RXERR_CRC)
1920 sc->stats.rxerr_crc++;
1921 if (rs.rs_status & AR5K_RXERR_FIFO)
1922 sc->stats.rxerr_fifo++;
1923 if (rs.rs_status & AR5K_RXERR_PHY) {
1924 sc->stats.rxerr_phy++;
1858 goto next; 1925 goto next;
1926 }
1859 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1927 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1860 /* 1928 /*
1861 * Decrypt error. If the error occurred 1929 * Decrypt error. If the error occurred
@@ -1867,12 +1935,14 @@ ath5k_tasklet_rx(unsigned long data)
1867 * 1935 *
1868 * XXX do key cache faulting 1936 * XXX do key cache faulting
1869 */ 1937 */
1938 sc->stats.rxerr_decrypt++;
1870 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1939 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1871 !(rs.rs_status & AR5K_RXERR_CRC)) 1940 !(rs.rs_status & AR5K_RXERR_CRC))
1872 goto accept; 1941 goto accept;
1873 } 1942 }
1874 if (rs.rs_status & AR5K_RXERR_MIC) { 1943 if (rs.rs_status & AR5K_RXERR_MIC) {
1875 rx_flag |= RX_FLAG_MMIC_ERROR; 1944 rx_flag |= RX_FLAG_MMIC_ERROR;
1945 sc->stats.rxerr_mic++;
1876 goto accept; 1946 goto accept;
1877 } 1947 }
1878 1948
@@ -1904,12 +1974,8 @@ accept:
1904 * bytes and we can optimize this a bit. In addition, we must 1974 * bytes and we can optimize this a bit. In addition, we must
1905 * not try to remove padding from short control frames that do 1975 * not try to remove padding from short control frames that do
1906 * not have payload. */ 1976 * not have payload. */
1907 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1977 ath5k_remove_padding(skb);
1908 padsize = ath5k_pad_size(hdrlen); 1978
1909 if (padsize) {
1910 memmove(skb->data + padsize, skb->data, hdrlen);
1911 skb_pull(skb, padsize);
1912 }
1913 rxs = IEEE80211_SKB_RXCB(skb); 1979 rxs = IEEE80211_SKB_RXCB(skb);
1914 1980
1915 /* 1981 /*
@@ -1942,6 +2008,12 @@ accept:
1942 rxs->signal = rxs->noise + rs.rs_rssi; 2008 rxs->signal = rxs->noise + rs.rs_rssi;
1943 2009
1944 rxs->antenna = rs.rs_antenna; 2010 rxs->antenna = rs.rs_antenna;
2011
2012 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2013 sc->stats.antenna_rx[rs.rs_antenna]++;
2014 else
2015 sc->stats.antenna_rx[0]++; /* invalid */
2016
1945 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 2017 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1946 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 2018 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1947 2019
@@ -1996,6 +2068,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1996 break; 2068 break;
1997 } 2069 }
1998 2070
2071 sc->stats.tx_all_count++;
1999 skb = bf->skb; 2072 skb = bf->skb;
2000 info = IEEE80211_SKB_CB(skb); 2073 info = IEEE80211_SKB_CB(skb);
2001 bf->skb = NULL; 2074 bf->skb = NULL;
@@ -2022,13 +2095,30 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2022 2095
2023 if (unlikely(ts.ts_status)) { 2096 if (unlikely(ts.ts_status)) {
2024 sc->ll_stats.dot11ACKFailureCount++; 2097 sc->ll_stats.dot11ACKFailureCount++;
2025 if (ts.ts_status & AR5K_TXERR_FILT) 2098 if (ts.ts_status & AR5K_TXERR_FILT) {
2026 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2099 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2100 sc->stats.txerr_filt++;
2101 }
2102 if (ts.ts_status & AR5K_TXERR_XRETRY)
2103 sc->stats.txerr_retry++;
2104 if (ts.ts_status & AR5K_TXERR_FIFO)
2105 sc->stats.txerr_fifo++;
2027 } else { 2106 } else {
2028 info->flags |= IEEE80211_TX_STAT_ACK; 2107 info->flags |= IEEE80211_TX_STAT_ACK;
2029 info->status.ack_signal = ts.ts_rssi; 2108 info->status.ack_signal = ts.ts_rssi;
2030 } 2109 }
2031 2110
2111 /*
2112 * Remove MAC header padding before giving the frame
2113 * back to mac80211.
2114 */
2115 ath5k_remove_padding(skb);
2116
2117 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2118 sc->stats.antenna_tx[ts.ts_antenna]++;
2119 else
2120 sc->stats.antenna_tx[0]++; /* invalid */
2121
2032 ieee80211_tx_status(sc->hw, skb); 2122 ieee80211_tx_status(sc->hw, skb);
2033 2123
2034 spin_lock(&sc->txbuflock); 2124 spin_lock(&sc->txbuflock);
@@ -2072,6 +2162,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2072 int ret = 0; 2162 int ret = 0;
2073 u8 antenna; 2163 u8 antenna;
2074 u32 flags; 2164 u32 flags;
2165 const int padsize = 0;
2075 2166
2076 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2167 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2077 PCI_DMA_TODEVICE); 2168 PCI_DMA_TODEVICE);
@@ -2119,7 +2210,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2119 * from tx power (value is in dB units already) */ 2210 * from tx power (value is in dB units already) */
2120 ds->ds_data = bf->skbaddr; 2211 ds->ds_data = bf->skbaddr;
2121 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2212 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2122 ieee80211_get_hdrlen_from_skb(skb), 2213 ieee80211_get_hdrlen_from_skb(skb), padsize,
2123 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2214 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2124 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2215 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2125 1, AR5K_TXKEYIX_INVALID, 2216 1, AR5K_TXKEYIX_INVALID,
@@ -2679,7 +2770,6 @@ static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2679 struct ath5k_softc *sc = hw->priv; 2770 struct ath5k_softc *sc = hw->priv;
2680 struct ath5k_buf *bf; 2771 struct ath5k_buf *bf;
2681 unsigned long flags; 2772 unsigned long flags;
2682 int hdrlen;
2683 int padsize; 2773 int padsize;
2684 2774
2685 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2775 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
@@ -2691,17 +2781,11 @@ static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2691 * the hardware expects the header padded to 4 byte boundaries 2781 * the hardware expects the header padded to 4 byte boundaries
2692 * if this is not the case we add the padding after the header 2782 * if this is not the case we add the padding after the header
2693 */ 2783 */
2694 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 2784 padsize = ath5k_add_padding(skb);
2695 padsize = ath5k_pad_size(hdrlen); 2785 if (padsize < 0) {
2696 if (padsize) { 2786 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2697 2787 " headroom to pad");
2698 if (skb_headroom(skb) < padsize) { 2788 goto drop_packet;
2699 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2700 " headroom to pad %d\n", hdrlen, padsize);
2701 goto drop_packet;
2702 }
2703 skb_push(skb, padsize);
2704 memmove(skb->data, skb->data+padsize, hdrlen);
2705 } 2789 }
2706 2790
2707 spin_lock_irqsave(&sc->txbuflock, flags); 2791 spin_lock_irqsave(&sc->txbuflock, flags);
@@ -2720,7 +2804,7 @@ static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2720 2804
2721 bf->skb = skb; 2805 bf->skb = skb;
2722 2806
2723 if (ath5k_txbuf_setup(sc, bf, txq)) { 2807 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2724 bf->skb = NULL; 2808 bf->skb = NULL;
2725 spin_lock_irqsave(&sc->txbuflock, flags); 2809 spin_lock_irqsave(&sc->txbuflock, flags);
2726 list_add_tail(&bf->list, &sc->txbuf); 2810 list_add_tail(&bf->list, &sc->txbuf);
@@ -2835,6 +2919,8 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
2835 goto end; 2919 goto end;
2836 } 2920 }
2837 2921
2922 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2923
2838 ath5k_hw_set_lladdr(sc->ah, vif->addr); 2924 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2839 ath5k_mode_setup(sc); 2925 ath5k_mode_setup(sc);
2840 2926
@@ -2905,7 +2991,7 @@ ath5k_config(struct ieee80211_hw *hw, u32 changed)
2905 * then we must allow the user to set how many tx antennas we 2991 * then we must allow the user to set how many tx antennas we
2906 * have available 2992 * have available
2907 */ 2993 */
2908 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT); 2994 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
2909 2995
2910unlock: 2996unlock:
2911 mutex_unlock(&sc->lock); 2997 mutex_unlock(&sc->lock);
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h
index 7e1a88a5abdb..33f1d8b87ee1 100644
--- a/drivers/net/wireless/ath/ath5k/base.h
+++ b/drivers/net/wireless/ath/ath5k/base.h
@@ -105,6 +105,24 @@ struct ath5k_rfkill {
105 struct tasklet_struct toggleq; 105 struct tasklet_struct toggleq;
106}; 106};
107 107
108/* statistics (only used for debugging now) */
109struct ath5k_statistics {
110 unsigned int antenna_rx[5]; /* frames count per antenna RX */
111 unsigned int antenna_tx[5]; /* frames count per antenna TX */
112 unsigned int rx_all_count; /* all RX frames, including errors */
113 unsigned int tx_all_count; /* all TX frames, including errors */
114 unsigned int rxerr_crc;
115 unsigned int rxerr_phy;
116 unsigned int rxerr_fifo;
117 unsigned int rxerr_decrypt;
118 unsigned int rxerr_mic;
119 unsigned int rxerr_proc;
120 unsigned int rxerr_jumbo;
121 unsigned int txerr_retry;
122 unsigned int txerr_fifo;
123 unsigned int txerr_filt;
124};
125
108#if CHAN_DEBUG 126#if CHAN_DEBUG
109#define ATH_CHAN_MAX (26+26+26+200+200) 127#define ATH_CHAN_MAX (26+26+26+200+200)
110#else 128#else
@@ -191,6 +209,8 @@ struct ath5k_softc {
191 int power_level; /* Requested tx power in dbm */ 209 int power_level; /* Requested tx power in dbm */
192 bool assoc; /* associate state */ 210 bool assoc; /* associate state */
193 bool enable_beacon; /* true if beacons are on */ 211 bool enable_beacon; /* true if beacons are on */
212
213 struct ath5k_statistics stats;
194}; 214};
195 215
196#define ath5k_hw_hasbssidmask(_ah) \ 216#define ath5k_hw_hasbssidmask(_ah) \
diff --git a/drivers/net/wireless/ath/ath5k/caps.c b/drivers/net/wireless/ath/ath5k/caps.c
index 367a6c7d3cc7..e618e71b1ce6 100644
--- a/drivers/net/wireless/ath/ath5k/caps.c
+++ b/drivers/net/wireless/ath/ath5k/caps.c
@@ -102,9 +102,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
102 } 102 }
103 } 103 }
104 104
105 /* GPIO */
106 ah->ah_gpio_npins = AR5K_NUM_GPIO;
107
108 /* Set number of supported TX queues */ 105 /* Set number of supported TX queues */
109 if (ah->ah_version == AR5K_AR5210) 106 if (ah->ah_version == AR5K_AR5210)
110 ah->ah_capabilities.cap_queues.q_tx_num = 107 ah->ah_capabilities.cap_queues.q_tx_num =
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index 747508c15d34..bccd4a78027e 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -364,6 +364,207 @@ static const struct file_operations fops_debug = {
364}; 364};
365 365
366 366
367/* debugfs: antenna */
368
369static ssize_t read_file_antenna(struct file *file, char __user *user_buf,
370 size_t count, loff_t *ppos)
371{
372 struct ath5k_softc *sc = file->private_data;
373 char buf[700];
374 unsigned int len = 0;
375 unsigned int i;
376 unsigned int v;
377
378 len += snprintf(buf+len, sizeof(buf)-len, "antenna mode\t%d\n",
379 sc->ah->ah_ant_mode);
380 len += snprintf(buf+len, sizeof(buf)-len, "default antenna\t%d\n",
381 sc->ah->ah_def_ant);
382 len += snprintf(buf+len, sizeof(buf)-len, "tx antenna\t%d\n",
383 sc->ah->ah_tx_ant);
384
385 len += snprintf(buf+len, sizeof(buf)-len, "\nANTENNA\t\tRX\tTX\n");
386 for (i = 1; i < ARRAY_SIZE(sc->stats.antenna_rx); i++) {
387 len += snprintf(buf+len, sizeof(buf)-len,
388 "[antenna %d]\t%d\t%d\n",
389 i, sc->stats.antenna_rx[i], sc->stats.antenna_tx[i]);
390 }
391 len += snprintf(buf+len, sizeof(buf)-len, "[invalid]\t%d\t%d\n",
392 sc->stats.antenna_rx[0], sc->stats.antenna_tx[0]);
393
394 v = ath5k_hw_reg_read(sc->ah, AR5K_DEFAULT_ANTENNA);
395 len += snprintf(buf+len, sizeof(buf)-len,
396 "\nAR5K_DEFAULT_ANTENNA\t0x%08x\n", v);
397
398 v = ath5k_hw_reg_read(sc->ah, AR5K_STA_ID1);
399 len += snprintf(buf+len, sizeof(buf)-len,
400 "AR5K_STA_ID1_DEFAULT_ANTENNA\t%d\n",
401 (v & AR5K_STA_ID1_DEFAULT_ANTENNA) != 0);
402 len += snprintf(buf+len, sizeof(buf)-len,
403 "AR5K_STA_ID1_DESC_ANTENNA\t%d\n",
404 (v & AR5K_STA_ID1_DESC_ANTENNA) != 0);
405 len += snprintf(buf+len, sizeof(buf)-len,
406 "AR5K_STA_ID1_RTS_DEF_ANTENNA\t%d\n",
407 (v & AR5K_STA_ID1_RTS_DEF_ANTENNA) != 0);
408 len += snprintf(buf+len, sizeof(buf)-len,
409 "AR5K_STA_ID1_SELFGEN_DEF_ANT\t%d\n",
410 (v & AR5K_STA_ID1_SELFGEN_DEF_ANT) != 0);
411
412 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_AGCCTL);
413 len += snprintf(buf+len, sizeof(buf)-len,
414 "\nAR5K_PHY_AGCCTL_OFDM_DIV_DIS\t%d\n",
415 (v & AR5K_PHY_AGCCTL_OFDM_DIV_DIS) != 0);
416
417 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_RESTART);
418 len += snprintf(buf+len, sizeof(buf)-len,
419 "AR5K_PHY_RESTART_DIV_GC\t\t%x\n",
420 (v & AR5K_PHY_RESTART_DIV_GC) >> AR5K_PHY_RESTART_DIV_GC_S);
421
422 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_FAST_ANT_DIV);
423 len += snprintf(buf+len, sizeof(buf)-len,
424 "AR5K_PHY_FAST_ANT_DIV_EN\t%d\n",
425 (v & AR5K_PHY_FAST_ANT_DIV_EN) != 0);
426
427 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
428}
429
430static ssize_t write_file_antenna(struct file *file,
431 const char __user *userbuf,
432 size_t count, loff_t *ppos)
433{
434 struct ath5k_softc *sc = file->private_data;
435 unsigned int i;
436 char buf[20];
437
438 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
439 return -EFAULT;
440
441 if (strncmp(buf, "diversity", 9) == 0) {
442 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
443 printk(KERN_INFO "ath5k debug: enable diversity\n");
444 } else if (strncmp(buf, "fixed-a", 7) == 0) {
445 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
446 printk(KERN_INFO "ath5k debugfs: fixed antenna A\n");
447 } else if (strncmp(buf, "fixed-b", 7) == 0) {
448 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
449 printk(KERN_INFO "ath5k debug: fixed antenna B\n");
450 } else if (strncmp(buf, "clear", 5) == 0) {
451 for (i = 0; i < ARRAY_SIZE(sc->stats.antenna_rx); i++) {
452 sc->stats.antenna_rx[i] = 0;
453 sc->stats.antenna_tx[i] = 0;
454 }
455 printk(KERN_INFO "ath5k debug: cleared antenna stats\n");
456 }
457 return count;
458}
459
460static const struct file_operations fops_antenna = {
461 .read = read_file_antenna,
462 .write = write_file_antenna,
463 .open = ath5k_debugfs_open,
464 .owner = THIS_MODULE,
465};
466
467
468/* debugfs: frameerrors */
469
470static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
471 size_t count, loff_t *ppos)
472{
473 struct ath5k_softc *sc = file->private_data;
474 struct ath5k_statistics *st = &sc->stats;
475 char buf[700];
476 unsigned int len = 0;
477
478 len += snprintf(buf+len, sizeof(buf)-len,
479 "RX\n---------------------\n");
480 len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%d\t(%d%%)\n",
481 st->rxerr_crc,
482 st->rx_all_count > 0 ?
483 st->rxerr_crc*100/st->rx_all_count : 0);
484 len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%d\t(%d%%)\n",
485 st->rxerr_phy,
486 st->rx_all_count > 0 ?
487 st->rxerr_phy*100/st->rx_all_count : 0);
488 len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
489 st->rxerr_fifo,
490 st->rx_all_count > 0 ?
491 st->rxerr_fifo*100/st->rx_all_count : 0);
492 len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%d\t(%d%%)\n",
493 st->rxerr_decrypt,
494 st->rx_all_count > 0 ?
495 st->rxerr_decrypt*100/st->rx_all_count : 0);
496 len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%d\t(%d%%)\n",
497 st->rxerr_mic,
498 st->rx_all_count > 0 ?
499 st->rxerr_mic*100/st->rx_all_count : 0);
500 len += snprintf(buf+len, sizeof(buf)-len, "process\t%d\t(%d%%)\n",
501 st->rxerr_proc,
502 st->rx_all_count > 0 ?
503 st->rxerr_proc*100/st->rx_all_count : 0);
504 len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%d\t(%d%%)\n",
505 st->rxerr_jumbo,
506 st->rx_all_count > 0 ?
507 st->rxerr_jumbo*100/st->rx_all_count : 0);
508 len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%d]\n",
509 st->rx_all_count);
510
511 len += snprintf(buf+len, sizeof(buf)-len,
512 "\nTX\n---------------------\n");
513 len += snprintf(buf+len, sizeof(buf)-len, "retry\t%d\t(%d%%)\n",
514 st->txerr_retry,
515 st->tx_all_count > 0 ?
516 st->txerr_retry*100/st->tx_all_count : 0);
517 len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
518 st->txerr_fifo,
519 st->tx_all_count > 0 ?
520 st->txerr_fifo*100/st->tx_all_count : 0);
521 len += snprintf(buf+len, sizeof(buf)-len, "filter\t%d\t(%d%%)\n",
522 st->txerr_filt,
523 st->tx_all_count > 0 ?
524 st->txerr_filt*100/st->tx_all_count : 0);
525 len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%d]\n",
526 st->tx_all_count);
527
528 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
529}
530
531static ssize_t write_file_frameerrors(struct file *file,
532 const char __user *userbuf,
533 size_t count, loff_t *ppos)
534{
535 struct ath5k_softc *sc = file->private_data;
536 struct ath5k_statistics *st = &sc->stats;
537 char buf[20];
538
539 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
540 return -EFAULT;
541
542 if (strncmp(buf, "clear", 5) == 0) {
543 st->rxerr_crc = 0;
544 st->rxerr_phy = 0;
545 st->rxerr_fifo = 0;
546 st->rxerr_decrypt = 0;
547 st->rxerr_mic = 0;
548 st->rxerr_proc = 0;
549 st->rxerr_jumbo = 0;
550 st->rx_all_count = 0;
551 st->txerr_retry = 0;
552 st->txerr_fifo = 0;
553 st->txerr_filt = 0;
554 st->tx_all_count = 0;
555 printk(KERN_INFO "ath5k debug: cleared frameerrors stats\n");
556 }
557 return count;
558}
559
560static const struct file_operations fops_frameerrors = {
561 .read = read_file_frameerrors,
562 .write = write_file_frameerrors,
563 .open = ath5k_debugfs_open,
564 .owner = THIS_MODULE,
565};
566
567
367/* init */ 568/* init */
368 569
369void 570void
@@ -393,6 +594,15 @@ ath5k_debug_init_device(struct ath5k_softc *sc)
393 594
394 sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR, 595 sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR,
395 sc->debug.debugfs_phydir, sc, &fops_reset); 596 sc->debug.debugfs_phydir, sc, &fops_reset);
597
598 sc->debug.debugfs_antenna = debugfs_create_file("antenna",
599 S_IWUSR | S_IRUSR,
600 sc->debug.debugfs_phydir, sc, &fops_antenna);
601
602 sc->debug.debugfs_frameerrors = debugfs_create_file("frameerrors",
603 S_IWUSR | S_IRUSR,
604 sc->debug.debugfs_phydir, sc,
605 &fops_frameerrors);
396} 606}
397 607
398void 608void
@@ -408,6 +618,8 @@ ath5k_debug_finish_device(struct ath5k_softc *sc)
408 debugfs_remove(sc->debug.debugfs_registers); 618 debugfs_remove(sc->debug.debugfs_registers);
409 debugfs_remove(sc->debug.debugfs_beacon); 619 debugfs_remove(sc->debug.debugfs_beacon);
410 debugfs_remove(sc->debug.debugfs_reset); 620 debugfs_remove(sc->debug.debugfs_reset);
621 debugfs_remove(sc->debug.debugfs_antenna);
622 debugfs_remove(sc->debug.debugfs_frameerrors);
411 debugfs_remove(sc->debug.debugfs_phydir); 623 debugfs_remove(sc->debug.debugfs_phydir);
412} 624}
413 625
diff --git a/drivers/net/wireless/ath/ath5k/debug.h b/drivers/net/wireless/ath/ath5k/debug.h
index 66f69f04e55e..da24ff52e274 100644
--- a/drivers/net/wireless/ath/ath5k/debug.h
+++ b/drivers/net/wireless/ath/ath5k/debug.h
@@ -74,6 +74,8 @@ struct ath5k_dbg_info {
74 struct dentry *debugfs_registers; 74 struct dentry *debugfs_registers;
75 struct dentry *debugfs_beacon; 75 struct dentry *debugfs_beacon;
76 struct dentry *debugfs_reset; 76 struct dentry *debugfs_reset;
77 struct dentry *debugfs_antenna;
78 struct dentry *debugfs_frameerrors;
77}; 79};
78 80
79/** 81/**
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index dc30a2b70a6b..9d920fb14d5d 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -35,7 +35,8 @@
35 */ 35 */
36static int 36static int
37ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 37ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
38 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, 38 unsigned int pkt_len, unsigned int hdr_len, int padsize,
39 enum ath5k_pkt_type type,
39 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, 40 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
40 unsigned int key_index, unsigned int antenna_mode, unsigned int flags, 41 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
41 unsigned int rtscts_rate, unsigned int rtscts_duration) 42 unsigned int rtscts_rate, unsigned int rtscts_duration)
@@ -71,7 +72,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
71 /* Verify and set frame length */ 72 /* Verify and set frame length */
72 73
73 /* remove padding we might have added before */ 74 /* remove padding we might have added before */
74 frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN; 75 frame_len = pkt_len - padsize + FCS_LEN;
75 76
76 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN) 77 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
77 return -EINVAL; 78 return -EINVAL;
@@ -100,7 +101,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
100 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN); 101 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
101 } 102 }
102 103
103 /*Diferences between 5210-5211*/ 104 /*Differences between 5210-5211*/
104 if (ah->ah_version == AR5K_AR5210) { 105 if (ah->ah_version == AR5K_AR5210) {
105 switch (type) { 106 switch (type) {
106 case AR5K_PKT_TYPE_BEACON: 107 case AR5K_PKT_TYPE_BEACON:
@@ -165,6 +166,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
165 */ 166 */
166static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, 167static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
167 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len, 168 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
169 int padsize,
168 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, 170 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
169 unsigned int tx_tries0, unsigned int key_index, 171 unsigned int tx_tries0, unsigned int key_index,
170 unsigned int antenna_mode, unsigned int flags, 172 unsigned int antenna_mode, unsigned int flags,
@@ -206,7 +208,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
206 /* Verify and set frame length */ 208 /* Verify and set frame length */
207 209
208 /* remove padding we might have added before */ 210 /* remove padding we might have added before */
209 frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN; 211 frame_len = pkt_len - padsize + FCS_LEN;
210 212
211 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN) 213 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
212 return -EINVAL; 214 return -EINVAL;
@@ -229,7 +231,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
229 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); 231 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
230 tx_ctl->tx_control_1 |= AR5K_REG_SM(type, 232 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
231 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); 233 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
232 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, 234 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
233 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); 235 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
234 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; 236 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
235 237
@@ -668,12 +670,6 @@ int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
668 ah->ah_version != AR5K_AR5212) 670 ah->ah_version != AR5K_AR5212)
669 return -ENOTSUPP; 671 return -ENOTSUPP;
670 672
671 /* XXX: What is this magic value and where is it used ? */
672 if (ah->ah_version == AR5K_AR5212)
673 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
674 else if (ah->ah_version == AR5K_AR5211)
675 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
676
677 if (ah->ah_version == AR5K_AR5212) { 673 if (ah->ah_version == AR5K_AR5212) {
678 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc; 674 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
679 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; 675 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index 10b52262b232..a3cbfe4fc389 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -329,7 +329,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
329 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 329 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
330 ee->ee_xpd[mode] = val & 0x1; 330 ee->ee_xpd[mode] = val & 0x1;
331 331
332 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 332 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
333 mode != AR5K_EEPROM_MODE_11B)
333 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 334 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
334 335
335 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 336 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
@@ -339,6 +340,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
339 if (mode == AR5K_EEPROM_MODE_11A) 340 if (mode == AR5K_EEPROM_MODE_11A)
340 ee->ee_xr_power[mode] = val & 0x3f; 341 ee->ee_xr_power[mode] = val & 0x3f;
341 else { 342 else {
343 /* b_DB_11[bg] and b_OB_11[bg] */
342 ee->ee_ob[mode][0] = val & 0x7; 344 ee->ee_ob[mode][0] = val & 0x7;
343 ee->ee_db[mode][0] = (val >> 3) & 0x7; 345 ee->ee_db[mode][0] = (val >> 3) & 0x7;
344 } 346 }
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index 473a483bb9c3..c4a6d5f26af4 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -24,9 +24,6 @@
24 * SERDES infos are present */ 24 * SERDES infos are present */
25#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ 25#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
26#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ 26#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
27#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
28#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
29#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
30 27
31#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ 28#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
32 29
@@ -78,9 +75,9 @@
78#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) 75#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
79#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) 76#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
80#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) 77#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
81#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ 78#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz */
82#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ 79#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for < 2W power consumption */
83#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) 80#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
84#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ 81#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
85#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ 82#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */
86 83
@@ -101,7 +98,7 @@
101 98
102#define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) 99#define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
103#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) 100#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
104#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) 101#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) /* has 32KHz crystal for sleep mode */
105#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) 102#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
106 103
107#define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) 104#define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6)
@@ -114,26 +111,27 @@
114 111
115#define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) 112#define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8)
116#define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) 113#define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff)
117#define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) 114#define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2: A) */
118#define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) 115#define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) /* modes supported by radio 1 (bit 1: G, bit 2: A) */
119 116
120#define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) 117#define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9)
121#define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) 118#define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) /* disable compression */
122#define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) 119#define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) /* disable AES */
123#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) 120#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) /* disable fast frames */
124#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) 121#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) /* disable bursting */
125#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) 122#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */
126#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) 123#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) /* enable heayy clipping */
127#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) 124#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) /* key cache size. defaults to 128 */
128 125
129#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) 126#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
130#define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) 127#define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x7) /* MIMO chains disabled for TX bitmask */
131#define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) 128#define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x7) /* MIMO chains disabled for RX bitmask */
132#define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) 129#define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) /* 5.47-5.7GHz supported */
133#define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) 130#define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */
134#define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) 131#define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) /* Japan UNII2 band (5.25-5.35GHz) supported */
135#define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) 132#define AR5K_EEPROM_JAP_MID_EN (((_v) >> 9) & 0x1) /* Japan band from 5.47-5.7GHz supported */
136#define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) 133#define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 10) & 0x1) /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */
134#define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 11) & 0x1) /* Japan A mode enabled (using even channels) */
137 135
138/* calibration settings */ 136/* calibration settings */
139#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) 137#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
@@ -389,7 +387,49 @@ struct ath5k_edge_power {
389 bool flag; 387 bool flag;
390}; 388};
391 389
392/* EEPROM calibration data */ 390/**
391 * struct ath5k_eeprom_info - EEPROM calibration data
392 *
393 * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING
394 * flags
395 * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?]
396 * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for
397 * OFDM and CCK packets
398 * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK
399 * (11Mbps) rate in G mode. 0.1dB steps
400 * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution
401 *
402 * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path
403 * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path
404 * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control
405 * @ee_switch_settling: RX/TX Switch settling time
406 * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps
407 * @ee_ant_control: Antenna Control Settings
408 * @ee_ob: Bias current for Output stage of PA
409 * B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
410 * A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
411 * @ee_db: Bias current for Output stage of PA. see @ee_ob
412 * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame
413 * to when the external LNA is activated
414 * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame
415 * to when the external PA switch is deactivated
416 * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when
417 * external PA switch is activated
418 * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity
419 * (IEEE802.11a section 17.3.10.5 )
420 * @ee_xlna_gain: Total gain of the LNA (information only)
421 * @ee_xpd: Use external (1) or internal power detector
422 * @ee_x_gain: Gain for external power detector output (differences in EEMAP
423 * versions!)
424 * @ee_i_gain: Initial gain value after reset
425 * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used
426 *
427 * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals
428 * @ee_noise_floor_thr: Noise floor threshold in 1dB steps
429 * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps
430 * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps
431 * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)
432 */
393struct ath5k_eeprom_info { 433struct ath5k_eeprom_info {
394 434
395 /* Header information */ 435 /* Header information */
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index aefe84f9c04b..1b9fcb842167 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -39,16 +39,16 @@
39 * ath5k_hw_set_opmode - Set PCU operating mode 39 * ath5k_hw_set_opmode - Set PCU operating mode
40 * 40 *
41 * @ah: The &struct ath5k_hw 41 * @ah: The &struct ath5k_hw
42 * @op_mode: &enum nl80211_iftype operating mode
42 * 43 *
43 * Initialize PCU for the various operating modes (AP/STA etc) 44 * Initialize PCU for the various operating modes (AP/STA etc)
44 *
45 * NOTE: ah->ah_op_mode must be set before calling this.
46 */ 45 */
47int ath5k_hw_set_opmode(struct ath5k_hw *ah) 46int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48{ 47{
49 struct ath_common *common = ath5k_hw_common(ah); 48 struct ath_common *common = ath5k_hw_common(ah);
50 u32 pcu_reg, beacon_reg, low_id, high_id; 49 u32 pcu_reg, beacon_reg, low_id, high_id;
51 50
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
52 52
53 /* Preserve rest settings */ 53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
@@ -61,7 +61,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
61 61
62 ATH5K_TRACE(ah->ah_sc); 62 ATH5K_TRACE(ah->ah_sc);
63 63
64 switch (ah->ah_op_mode) { 64 switch (op_mode) {
65 case NL80211_IFTYPE_ADHOC: 65 case NL80211_IFTYPE_ADHOC:
66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
67 beacon_reg |= AR5K_BCR_ADHOC; 67 beacon_reg |= AR5K_BCR_ADHOC;
@@ -179,25 +179,12 @@ void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
179\******************/ 179\******************/
180 180
181/** 181/**
182 * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
183 *
184 * @ah: The &struct ath5k_hw
185 */
186unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
187{
188 ATH5K_TRACE(ah->ah_sc);
189
190 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah,
191 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK));
192}
193
194/**
195 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 182 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
196 * 183 *
197 * @ah: The &struct ath5k_hw 184 * @ah: The &struct ath5k_hw
198 * @timeout: Timeout in usec 185 * @timeout: Timeout in usec
199 */ 186 */
200int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 187static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
201{ 188{
202 ATH5K_TRACE(ah->ah_sc); 189 ATH5K_TRACE(ah->ah_sc);
203 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 190 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
@@ -211,24 +198,12 @@ int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
211} 198}
212 199
213/** 200/**
214 * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
215 *
216 * @ah: The &struct ath5k_hw
217 */
218unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
219{
220 ATH5K_TRACE(ah->ah_sc);
221 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah,
222 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS));
223}
224
225/**
226 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 201 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
227 * 202 *
228 * @ah: The &struct ath5k_hw 203 * @ah: The &struct ath5k_hw
229 * @timeout: Timeout in usec 204 * @timeout: Timeout in usec
230 */ 205 */
231int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 206static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
232{ 207{
233 ATH5K_TRACE(ah->ah_sc); 208 ATH5K_TRACE(ah->ah_sc);
234 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 209 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
@@ -290,7 +265,7 @@ unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
290 * 265 *
291 * @ah: The &struct ath5k_hw 266 * @ah: The &struct ath5k_hw
292 */ 267 */
293unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 268static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
294{ 269{
295 struct ieee80211_channel *channel = ah->ah_current_channel; 270 struct ieee80211_channel *channel = ah->ah_current_channel;
296 271
@@ -308,7 +283,7 @@ unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
308 * 283 *
309 * @ah: The &struct ath5k_hw 284 * @ah: The &struct ath5k_hw
310 */ 285 */
311unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 286static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
312{ 287{
313 struct ieee80211_channel *channel = ah->ah_current_channel; 288 struct ieee80211_channel *channel = ah->ah_current_channel;
314 289
@@ -451,42 +426,6 @@ void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
451 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 426 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
452} 427}
453 428
454/*
455 * Set multicast filter by index
456 */
457int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
458{
459
460 ATH5K_TRACE(ah->ah_sc);
461 if (index >= 64)
462 return -EINVAL;
463 else if (index >= 32)
464 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
465 (1 << (index - 32)));
466 else
467 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
468
469 return 0;
470}
471
472/*
473 * Clear Multicast filter by index
474 */
475int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
476{
477
478 ATH5K_TRACE(ah->ah_sc);
479 if (index >= 64)
480 return -EINVAL;
481 else if (index >= 32)
482 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
483 (1 << (index - 32)));
484 else
485 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
486
487 return 0;
488}
489
490/** 429/**
491 * ath5k_hw_get_rx_filter - Get current rx filter 430 * ath5k_hw_get_rx_filter - Get current rx filter
492 * 431 *
@@ -572,19 +511,6 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
572\****************/ 511\****************/
573 512
574/** 513/**
575 * ath5k_hw_get_tsf32 - Get a 32bit TSF
576 *
577 * @ah: The &struct ath5k_hw
578 *
579 * Returns lower 32 bits of current TSF
580 */
581u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
582{
583 ATH5K_TRACE(ah->ah_sc);
584 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
585}
586
587/**
588 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 514 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
589 * 515 *
590 * @ah: The &struct ath5k_hw 516 * @ah: The &struct ath5k_hw
@@ -651,7 +577,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
651 /* 577 /*
652 * Set the additional timers by mode 578 * Set the additional timers by mode
653 */ 579 */
654 switch (ah->ah_op_mode) { 580 switch (ah->ah_sc->opmode) {
655 case NL80211_IFTYPE_MONITOR: 581 case NL80211_IFTYPE_MONITOR:
656 case NL80211_IFTYPE_STATION: 582 case NL80211_IFTYPE_STATION:
657 /* In STA mode timer1 is used as next wakeup 583 /* In STA mode timer1 is used as next wakeup
@@ -688,8 +614,8 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
688 * Set the beacon register and enable all timers. 614 * Set the beacon register and enable all timers.
689 */ 615 */
690 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 616 /* When in AP or Mesh Point mode zero timer0 to start TSF */
691 if (ah->ah_op_mode == NL80211_IFTYPE_AP || 617 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
692 ah->ah_op_mode == NL80211_IFTYPE_MESH_POINT) 618 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
693 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 619 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
694 620
695 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 621 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
@@ -722,203 +648,6 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
722 648
723} 649}
724 650
725#if 0
726/*
727 * Set beacon timers
728 */
729int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
730 const struct ath5k_beacon_state *state)
731{
732 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
733
734 /*
735 * TODO: should be changed through *state
736 * review struct ath5k_beacon_state struct
737 *
738 * XXX: These are used for cfp period bellow, are they
739 * ok ? Is it O.K. for tsf here to be 0 or should we use
740 * get_tsf ?
741 */
742 u32 dtim_count = 0; /* XXX */
743 u32 cfp_count = 0; /* XXX */
744 u32 tsf = 0; /* XXX */
745
746 ATH5K_TRACE(ah->ah_sc);
747 /* Return on an invalid beacon state */
748 if (state->bs_interval < 1)
749 return -EINVAL;
750
751 interval = state->bs_interval;
752 dtim = state->bs_dtim_period;
753
754 /*
755 * PCF support?
756 */
757 if (state->bs_cfp_period > 0) {
758 /*
759 * Enable PCF mode and set the CFP
760 * (Contention Free Period) and timer registers
761 */
762 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
763 state->bs_interval;
764 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
765 state->bs_interval;
766
767 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
768 AR5K_STA_ID1_DEFAULT_ANTENNA |
769 AR5K_STA_ID1_PCF);
770 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
771 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
772 AR5K_CFP_DUR);
773 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
774 next_cfp)) << 3, AR5K_TIMER2);
775 } else {
776 /* Disable PCF mode */
777 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
778 AR5K_STA_ID1_DEFAULT_ANTENNA |
779 AR5K_STA_ID1_PCF);
780 }
781
782 /*
783 * Enable the beacon timer register
784 */
785 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
786
787 /*
788 * Start the beacon timers
789 */
790 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &
791 ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
792 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
793 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
794 AR5K_BEACON_PERIOD), AR5K_BEACON);
795
796 /*
797 * Write new beacon miss threshold, if it appears to be valid
798 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
799 * and return if its not in range. We can test this by reading value and
800 * setting value to a largest value and seeing which values register.
801 */
802
803 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
804 state->bs_bmiss_threshold);
805
806 /*
807 * Set sleep control register
808 * XXX: Didn't find this in 5210 code but since this register
809 * exists also in ar5k's 5210 headers i leave it as common code.
810 */
811 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
812 (state->bs_sleep_duration - 3) << 3);
813
814 /*
815 * Set enhanced sleep registers on 5212
816 */
817 if (ah->ah_version == AR5K_AR5212) {
818 if (state->bs_sleep_duration > state->bs_interval &&
819 roundup(state->bs_sleep_duration, interval) ==
820 state->bs_sleep_duration)
821 interval = state->bs_sleep_duration;
822
823 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
824 roundup(state->bs_sleep_duration, dtim) ==
825 state->bs_sleep_duration))
826 dtim = state->bs_sleep_duration;
827
828 if (interval > dtim)
829 return -EINVAL;
830
831 next_beacon = interval == dtim ? state->bs_next_dtim :
832 state->bs_next_beacon;
833
834 ath5k_hw_reg_write(ah,
835 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
836 AR5K_SLEEP0_NEXT_DTIM) |
837 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
838 AR5K_SLEEP0_ENH_SLEEP_EN |
839 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
840
841 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
842 AR5K_SLEEP1_NEXT_TIM) |
843 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
844
845 ath5k_hw_reg_write(ah,
846 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
847 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
848 }
849
850 return 0;
851}
852
853/*
854 * Reset beacon timers
855 */
856void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
857{
858 ATH5K_TRACE(ah->ah_sc);
859 /*
860 * Disable beacon timer
861 */
862 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
863
864 /*
865 * Disable some beacon register values
866 */
867 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
868 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
869 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
870}
871
872/*
873 * Wait for beacon queue to finish
874 */
875int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
876{
877 unsigned int i;
878 int ret;
879
880 ATH5K_TRACE(ah->ah_sc);
881
882 /* 5210 doesn't have QCU*/
883 if (ah->ah_version == AR5K_AR5210) {
884 /*
885 * Wait for beaconn queue to finish by checking
886 * Control Register and Beacon Status Register.
887 */
888 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
889 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
890 ||
891 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
892 break;
893 udelay(10);
894 }
895
896 /* Timeout... */
897 if (i <= 0) {
898 /*
899 * Re-schedule the beacon queue
900 */
901 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
902 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
903 AR5K_BCR);
904
905 return -EIO;
906 }
907 ret = 0;
908 } else {
909 /*5211/5212*/
910 ret = ath5k_hw_register_timeout(ah,
911 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
912 AR5K_QCU_STS_FRMPENDCNT, 0, false);
913
914 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
915 return -EIO;
916 }
917
918 return ret;
919}
920#endif
921
922 651
923/*********************\ 652/*********************\
924* Key table functions * 653* Key table functions *
@@ -971,19 +700,6 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
971 return 0; 700 return 0;
972} 701}
973 702
974/*
975 * Check if a table entry is valid
976 */
977int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
978{
979 ATH5K_TRACE(ah->ah_sc);
980 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
981
982 /* Check the validation flag at the end of the entry */
983 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
984 AR5K_KEYTABLE_VALID;
985}
986
987static 703static
988int ath5k_keycache_type(const struct ieee80211_key_conf *key) 704int ath5k_keycache_type(const struct ieee80211_key_conf *key)
989{ 705{
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index eff3323efb4b..a8adca62e527 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -20,8 +20,6 @@
20 * 20 *
21 */ 21 */
22 22
23#define _ATH5K_PHY
24
25#include <linux/delay.h> 23#include <linux/delay.h>
26 24
27#include "ath5k.h" 25#include "ath5k.h"
@@ -1190,7 +1188,7 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1190 * The median of the values in the history is then loaded into the 1188 * The median of the values in the history is then loaded into the
1191 * hardware for its own use for RSSI and CCA measurements. 1189 * hardware for its own use for RSSI and CCA measurements.
1192 */ 1190 */
1193void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1191static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1194{ 1192{
1195 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1193 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1196 u32 val; 1194 u32 val;
@@ -1399,7 +1397,11 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1399 } 1397 }
1400 1398
1401 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1399 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1402 q_coffd = q_pwr >> 7; 1400
1401 if (ah->ah_version == AR5K_AR5211)
1402 q_coffd = q_pwr >> 6;
1403 else
1404 q_coffd = q_pwr >> 7;
1403 1405
1404 /* protect against divide by 0 and loss of sign bits */ 1406 /* protect against divide by 0 and loss of sign bits */
1405 if (i_coffd == 0 || q_coffd < 2) 1407 if (i_coffd == 0 || q_coffd < 2)
@@ -1768,7 +1770,7 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1768* Antenna control * 1770* Antenna control *
1769\*****************/ 1771\*****************/
1770 1772
1771void /*TODO:Boundary check*/ 1773static void /*TODO:Boundary check*/
1772ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1774ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1773{ 1775{
1774 ATH5K_TRACE(ah->ah_sc); 1776 ATH5K_TRACE(ah->ah_sc);
@@ -1777,16 +1779,6 @@ ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1777 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1779 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1778} 1780}
1779 1781
1780unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1781{
1782 ATH5K_TRACE(ah->ah_sc);
1783
1784 if (ah->ah_version != AR5K_AR5210)
1785 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7;
1786
1787 return false; /*XXX: What do we return for 5210 ?*/
1788}
1789
1790/* 1782/*
1791 * Enable/disable fast rx antenna diversity 1783 * Enable/disable fast rx antenna diversity
1792 */ 1784 */
@@ -1930,6 +1922,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1930 1922
1931 ah->ah_tx_ant = tx_ant; 1923 ah->ah_tx_ant = tx_ant;
1932 ah->ah_ant_mode = ant_mode; 1924 ah->ah_ant_mode = ant_mode;
1925 ah->ah_def_ant = def_ant;
1933 1926
1934 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 1927 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1935 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 1928 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
@@ -2440,19 +2433,6 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2440 pcdac_tmp = pcdac_high_pwr; 2433 pcdac_tmp = pcdac_high_pwr;
2441 2434
2442 edge_flag = 0x40; 2435 edge_flag = 0x40;
2443#if 0
2444 /* If both min and max power limits are in lower
2445 * power curve's range, only use the low power curve.
2446 * TODO: min/max levels are related to target
2447 * power values requested from driver/user
2448 * XXX: Is this really needed ? */
2449 if (min_pwr < table_max[1] &&
2450 max_pwr < table_max[1]) {
2451 edge_flag = 0;
2452 pcdac_tmp = pcdac_low_pwr;
2453 max_pwr_idx = (table_max[1] - table_min[1])/2;
2454 }
2455#endif
2456 } else { 2436 } else {
2457 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2437 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2458 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2438 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
@@ -3143,5 +3123,3 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3143 3123
3144 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3124 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3145} 3125}
3146
3147#undef _ATH5K_PHY
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 9122a8556f45..f5831da33f7b 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -517,23 +517,6 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
517} 517}
518 518
519/* 519/*
520 * Get slot time from DCU
521 */
522unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
523{
524 unsigned int slot_time_clock;
525
526 ATH5K_TRACE(ah->ah_sc);
527
528 if (ah->ah_version == AR5K_AR5210)
529 slot_time_clock = ath5k_hw_reg_read(ah, AR5K_SLOT_TIME);
530 else
531 slot_time_clock = ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT);
532
533 return ath5k_hw_clocktoh(ah, slot_time_clock & 0xffff);
534}
535
536/*
537 * Set slot time on DCU 520 * Set slot time on DCU
538 */ 521 */
539int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time) 522int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 1464f89b249c..47f04932ab8b 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -1974,7 +1974,7 @@
1974#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1974#define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1975#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ 1975#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
1976#define AR5K_PHY_SETTLING_AGC_S 0 1976#define AR5K_PHY_SETTLING_AGC_S 0
1977#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ 1977#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */
1978#define AR5K_PHY_SETTLING_SWITCH_S 7 1978#define AR5K_PHY_SETTLING_SWITCH_S 7
1979 1979
1980/* 1980/*
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index cbf28e379843..44bbbf2a6edd 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -19,8 +19,6 @@
19 * 19 *
20 */ 20 */
21 21
22#define _ATH5K_RESET
23
24/*****************************\ 22/*****************************\
25 Reset functions and helpers 23 Reset functions and helpers
26\*****************************/ 24\*****************************/
@@ -34,6 +32,27 @@
34#include "base.h" 32#include "base.h"
35#include "debug.h" 33#include "debug.h"
36 34
35/*
36 * Check if a register write has been completed
37 */
38int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
39 bool is_set)
40{
41 int i;
42 u32 data;
43
44 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
45 data = ath5k_hw_reg_read(ah, reg);
46 if (is_set && (data & flag))
47 break;
48 else if ((data & flag) == val)
49 break;
50 udelay(15);
51 }
52
53 return (i <= 0) ? -EAGAIN : 0;
54}
55
37/** 56/**
38 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 57 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
39 * 58 *
@@ -221,8 +240,8 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
221/* 240/*
222 * Sleep control 241 * Sleep control
223 */ 242 */
224int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 243static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
225 bool set_chip, u16 sleep_duration) 244 bool set_chip, u16 sleep_duration)
226{ 245{
227 unsigned int i; 246 unsigned int i;
228 u32 staid, data; 247 u32 staid, data;
@@ -1017,11 +1036,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1017 if (ret) 1036 if (ret)
1018 return ret; 1037 return ret;
1019 1038
1020 /*
1021 * Initialize operating mode
1022 */
1023 ah->ah_op_mode = op_mode;
1024
1025 /* PHY access enable */ 1039 /* PHY access enable */
1026 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 1040 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1027 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1041 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
@@ -1192,7 +1206,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1192 ath5k_hw_set_associd(ah); 1206 ath5k_hw_set_associd(ah);
1193 1207
1194 /* Set PCU config */ 1208 /* Set PCU config */
1195 ath5k_hw_set_opmode(ah); 1209 ath5k_hw_set_opmode(ah, op_mode);
1196 1210
1197 /* Clear any pending interrupts 1211 /* Clear any pending interrupts
1198 * PISR/SISR Not available on 5210 */ 1212 * PISR/SISR Not available on 5210 */
@@ -1378,7 +1392,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1378 * external 32KHz crystal when sleeping if one 1392 * external 32KHz crystal when sleeping if one
1379 * exists */ 1393 * exists */
1380 if (ah->ah_version == AR5K_AR5212 && 1394 if (ah->ah_version == AR5K_AR5212 &&
1381 ah->ah_op_mode != NL80211_IFTYPE_AP) 1395 op_mode != NL80211_IFTYPE_AP)
1382 ath5k_hw_set_sleep_clock(ah, true); 1396 ath5k_hw_set_sleep_clock(ah, true);
1383 1397
1384 /* 1398 /*
@@ -1388,5 +1402,3 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1388 ath5k_hw_reset_tsf(ah); 1402 ath5k_hw_reset_tsf(ah);
1389 return 0; 1403 return 0;
1390} 1404}
1391
1392#undef _ATH5K_RESET
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 06:00:30 -0400