diff options
author | David S. Miller <davem@davemloft.net> | 2010-03-22 21:15:15 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-03-22 21:15:15 -0400 |
commit | 33e2bf6aa16061bae1253514e7c32af27d2b4b31 (patch) | |
tree | 652d13b4feea9a8f562186e7badae72d2e22fe1f /drivers/net/wireless/ath/ath5k/reset.c | |
parent | e880eb6c5c9d98e389ffc0d8947f75d70785361a (diff) | |
parent | 819bfecc4fc6b6e5a793f719a45b7146ce423b79 (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Conflicts:
Documentation/feature-removal-schedule.txt
drivers/net/wireless/ath/ath5k/phy.c
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/reset.c')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/reset.c | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index cbf28e379843..44bbbf2a6edd 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c | |||
@@ -19,8 +19,6 @@ | |||
19 | * | 19 | * |
20 | */ | 20 | */ |
21 | 21 | ||
22 | #define _ATH5K_RESET | ||
23 | |||
24 | /*****************************\ | 22 | /*****************************\ |
25 | Reset functions and helpers | 23 | Reset functions and helpers |
26 | \*****************************/ | 24 | \*****************************/ |
@@ -34,6 +32,27 @@ | |||
34 | #include "base.h" | 32 | #include "base.h" |
35 | #include "debug.h" | 33 | #include "debug.h" |
36 | 34 | ||
35 | /* | ||
36 | * Check if a register write has been completed | ||
37 | */ | ||
38 | int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, | ||
39 | bool is_set) | ||
40 | { | ||
41 | int i; | ||
42 | u32 data; | ||
43 | |||
44 | for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { | ||
45 | data = ath5k_hw_reg_read(ah, reg); | ||
46 | if (is_set && (data & flag)) | ||
47 | break; | ||
48 | else if ((data & flag) == val) | ||
49 | break; | ||
50 | udelay(15); | ||
51 | } | ||
52 | |||
53 | return (i <= 0) ? -EAGAIN : 0; | ||
54 | } | ||
55 | |||
37 | /** | 56 | /** |
38 | * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 | 57 | * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 |
39 | * | 58 | * |
@@ -221,8 +240,8 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) | |||
221 | /* | 240 | /* |
222 | * Sleep control | 241 | * Sleep control |
223 | */ | 242 | */ |
224 | int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, | 243 | static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, |
225 | bool set_chip, u16 sleep_duration) | 244 | bool set_chip, u16 sleep_duration) |
226 | { | 245 | { |
227 | unsigned int i; | 246 | unsigned int i; |
228 | u32 staid, data; | 247 | u32 staid, data; |
@@ -1017,11 +1036,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
1017 | if (ret) | 1036 | if (ret) |
1018 | return ret; | 1037 | return ret; |
1019 | 1038 | ||
1020 | /* | ||
1021 | * Initialize operating mode | ||
1022 | */ | ||
1023 | ah->ah_op_mode = op_mode; | ||
1024 | |||
1025 | /* PHY access enable */ | 1039 | /* PHY access enable */ |
1026 | if (ah->ah_mac_srev >= AR5K_SREV_AR5211) | 1040 | if (ah->ah_mac_srev >= AR5K_SREV_AR5211) |
1027 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); | 1041 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
@@ -1192,7 +1206,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
1192 | ath5k_hw_set_associd(ah); | 1206 | ath5k_hw_set_associd(ah); |
1193 | 1207 | ||
1194 | /* Set PCU config */ | 1208 | /* Set PCU config */ |
1195 | ath5k_hw_set_opmode(ah); | 1209 | ath5k_hw_set_opmode(ah, op_mode); |
1196 | 1210 | ||
1197 | /* Clear any pending interrupts | 1211 | /* Clear any pending interrupts |
1198 | * PISR/SISR Not available on 5210 */ | 1212 | * PISR/SISR Not available on 5210 */ |
@@ -1378,7 +1392,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
1378 | * external 32KHz crystal when sleeping if one | 1392 | * external 32KHz crystal when sleeping if one |
1379 | * exists */ | 1393 | * exists */ |
1380 | if (ah->ah_version == AR5K_AR5212 && | 1394 | if (ah->ah_version == AR5K_AR5212 && |
1381 | ah->ah_op_mode != NL80211_IFTYPE_AP) | 1395 | op_mode != NL80211_IFTYPE_AP) |
1382 | ath5k_hw_set_sleep_clock(ah, true); | 1396 | ath5k_hw_set_sleep_clock(ah, true); |
1383 | 1397 | ||
1384 | /* | 1398 | /* |
@@ -1388,5 +1402,3 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
1388 | ath5k_hw_reset_tsf(ah); | 1402 | ath5k_hw_reset_tsf(ah); |
1389 | return 0; | 1403 | return 0; |
1390 | } | 1404 | } |
1391 | |||
1392 | #undef _ATH5K_RESET | ||