diff options
author | Felix Fietkau <nbd@openwrt.org> | 2010-12-02 04:27:01 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-12-02 15:17:50 -0500 |
commit | 4aa5d783c9e1c72e4950ff34f388077ccecac74a (patch) | |
tree | 13e54573b8e38fa8f012d55dbbadddd503683e6e /drivers/net/wireless/ath/ath5k/pci.c | |
parent | e5b046d86fac609f636d127a38de94a175c7e83b (diff) |
ath5k: Use generic eeprom read from common ath_bus_opts struct.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/pci.c')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/pci.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c index 9f7d3ca6ea21..3f26cf200196 100644 --- a/drivers/net/wireless/ath/ath5k/pci.c +++ b/drivers/net/wireless/ath/ath5k/pci.c | |||
@@ -65,10 +65,46 @@ static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) | |||
65 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ | 65 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ |
66 | } | 66 | } |
67 | 67 | ||
68 | /* | ||
69 | * Read from eeprom | ||
70 | */ | ||
71 | bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) | ||
72 | { | ||
73 | struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; | ||
74 | u32 status, timeout; | ||
75 | |||
76 | /* | ||
77 | * Initialize EEPROM access | ||
78 | */ | ||
79 | if (ah->ah_version == AR5K_AR5210) { | ||
80 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); | ||
81 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); | ||
82 | } else { | ||
83 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); | ||
84 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, | ||
85 | AR5K_EEPROM_CMD_READ); | ||
86 | } | ||
87 | |||
88 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { | ||
89 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); | ||
90 | if (status & AR5K_EEPROM_STAT_RDDONE) { | ||
91 | if (status & AR5K_EEPROM_STAT_RDERR) | ||
92 | return -EIO; | ||
93 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & | ||
94 | 0xffff); | ||
95 | return 0; | ||
96 | } | ||
97 | udelay(15); | ||
98 | } | ||
99 | |||
100 | return -ETIMEDOUT; | ||
101 | } | ||
102 | |||
68 | /* Common ath_bus_opts structure */ | 103 | /* Common ath_bus_opts structure */ |
69 | static const struct ath_bus_ops ath_pci_bus_ops = { | 104 | static const struct ath_bus_ops ath_pci_bus_ops = { |
70 | .ath_bus_type = ATH_PCI, | 105 | .ath_bus_type = ATH_PCI, |
71 | .read_cachesize = ath5k_pci_read_cachesize, | 106 | .read_cachesize = ath5k_pci_read_cachesize, |
107 | .eeprom_read = ath5k_pci_eeprom_read, | ||
72 | }; | 108 | }; |
73 | 109 | ||
74 | /********************\ | 110 | /********************\ |