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authorBruno Randolf <br1@einfach.org>2010-06-16 06:11:12 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-06-16 14:58:58 -0400
commit8d67a0310f7cba4796e5d5df99ed59408ac0b767 (patch)
treecf70379332ccbd220ed8cb80ce410d238839282a /drivers/net/wireless/ath/ath5k/base.c
parentc086abae5baa2df449ea5247011e8b7d52bb13f4 (diff)
ath5k: more debug prints for resets
Add a debug print for every case of reset. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/base.c')
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 9d37c1a43a9d..936afd7bae7e 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -1111,8 +1111,9 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
1111static int 1111static int
1112ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1112ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1113{ 1113{
1114 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1114 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1115 sc->curchan->center_freq, chan->center_freq); 1115 "channel set, resetting (%u -> %u MHz)\n",
1116 sc->curchan->center_freq, chan->center_freq);
1116 1117
1117 /* 1118 /*
1118 * To switch channels clear any pending DMA operations; 1119 * To switch channels clear any pending DMA operations;
@@ -2298,6 +2299,8 @@ ath5k_beacon_send(struct ath5k_softc *sc)
2298 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2299 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2299 "stuck beacon time (%u missed)\n", 2300 "stuck beacon time (%u missed)\n",
2300 sc->bmisscount); 2301 sc->bmisscount);
2302 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2303 "stuck beacon, resetting\n");
2301 tasklet_schedule(&sc->restq); 2304 tasklet_schedule(&sc->restq);
2302 } 2305 }
2303 return; 2306 return;
@@ -2705,6 +2708,8 @@ ath5k_intr(int irq, void *dev_id)
2705 * Fatal errors are unrecoverable. 2708 * Fatal errors are unrecoverable.
2706 * Typically these are caused by DMA errors. 2709 * Typically these are caused by DMA errors.
2707 */ 2710 */
2711 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2712 "fatal int, resetting\n");
2708 tasklet_schedule(&sc->restq); 2713 tasklet_schedule(&sc->restq);
2709 } else if (unlikely(status & AR5K_INT_RXORN)) { 2714 } else if (unlikely(status & AR5K_INT_RXORN)) {
2710 /* 2715 /*
@@ -2717,8 +2722,11 @@ ath5k_intr(int irq, void *dev_id)
2717 * this guess is copied from the HAL. 2722 * this guess is copied from the HAL.
2718 */ 2723 */
2719 sc->stats.rxorn_intr++; 2724 sc->stats.rxorn_intr++;
2720 if (ah->ah_mac_srev < AR5K_SREV_AR5212) 2725 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2726 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2727 "rx overrun, resetting\n");
2721 tasklet_schedule(&sc->restq); 2728 tasklet_schedule(&sc->restq);
2729 }
2722 else 2730 else
2723 tasklet_schedule(&sc->rxtq); 2731 tasklet_schedule(&sc->rxtq);
2724 } else { 2732 } else {