ath5k: use bit shift operators for cache line size

This matches ath9k, providing consistency when reading both drivers.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 63c2b5714d2f..2b3cf39dd4b1 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -471,7 +471,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
                  * DMA to work so force a reasonable value here if it
                  * comes up zero.
                  */
-                csz = L1_CACHE_BYTES / sizeof(u32);
+                csz = L1_CACHE_BYTES >> 2;
                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
         }
         /*
@@ -544,7 +544,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
         __set_bit(ATH_STAT_INVALID, sc->status);
 
         sc->iobase = mem; /* So we can unmap it on detach */
-        sc->common.cachelsz = csz * sizeof(u32); /* convert to bytes */
+        sc->common.cachelsz = csz << 2; /* convert to bytes */
         sc->opmode = NL80211_IFTYPE_STATION;
         sc->bintval = 1000;
         mutex_init(&sc->lock);