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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/wan/dscc4.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/wan/dscc4.c')
-rw-r--r--drivers/net/wan/dscc4.c2074
1 files changed, 2074 insertions, 0 deletions
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c
new file mode 100644
index 000000000000..520a77a798e2
--- /dev/null
+++ b/drivers/net/wan/dscc4.c
@@ -0,0 +1,2074 @@
1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83#include <linux/module.h>
84#include <linux/types.h>
85#include <linux/errno.h>
86#include <linux/list.h>
87#include <linux/ioport.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/mm.h>
91
92#include <asm/system.h>
93#include <asm/cache.h>
94#include <asm/byteorder.h>
95#include <asm/uaccess.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98
99#include <linux/init.h>
100#include <linux/string.h>
101
102#include <linux/if_arp.h>
103#include <linux/netdevice.h>
104#include <linux/skbuff.h>
105#include <linux/delay.h>
106#include <net/syncppp.h>
107#include <linux/hdlc.h>
108
109/* Version */
110static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
111static int debug;
112static int quartz;
113
114#ifdef CONFIG_DSCC4_PCI_RST
115static DECLARE_MUTEX(dscc4_sem);
116static u32 dscc4_pci_config_store[16];
117#endif
118
119#define DRV_NAME "dscc4"
120
121#undef DSCC4_POLLING
122
123/* Module parameters */
124
125MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127MODULE_LICENSE("GPL");
128module_param(debug, int, 0);
129MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130module_param(quartz, int, 0);
131MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
132
133/* Structures */
134
135struct thingie {
136 int define;
137 u32 bits;
138};
139
140struct TxFD {
141 u32 state;
142 u32 next;
143 u32 data;
144 u32 complete;
145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
146};
147
148struct RxFD {
149 u32 state1;
150 u32 next;
151 u32 data;
152 u32 state2;
153 u32 end;
154};
155
156#define DUMMY_SKB_SIZE 64
157#define TX_LOW 8
158#define TX_RING_SIZE 32
159#define RX_RING_SIZE 32
160#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
161#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
162#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
163#define TX_TIMEOUT (HZ/10)
164#define DSCC4_HZ_MAX 33000000
165#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
166#define dev_per_card 4
167#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
168
169#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
170#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
171
172/*
173 * Given the operating range of Linux HDLC, the 2 defines below could be
174 * made simpler. However they are a fine reminder for the limitations of
175 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
176 */
177#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
178#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
179#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
180#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
181
182struct dscc4_pci_priv {
183 u32 *iqcfg;
184 int cfg_cur;
185 spinlock_t lock;
186 struct pci_dev *pdev;
187
188 struct dscc4_dev_priv *root;
189 dma_addr_t iqcfg_dma;
190 u32 xtal_hz;
191};
192
193struct dscc4_dev_priv {
194 struct sk_buff *rx_skbuff[RX_RING_SIZE];
195 struct sk_buff *tx_skbuff[TX_RING_SIZE];
196
197 struct RxFD *rx_fd;
198 struct TxFD *tx_fd;
199 u32 *iqrx;
200 u32 *iqtx;
201
202 /* FIXME: check all the volatile are required */
203 volatile u32 tx_current;
204 u32 rx_current;
205 u32 iqtx_current;
206 u32 iqrx_current;
207
208 volatile u32 tx_dirty;
209 volatile u32 ltda;
210 u32 rx_dirty;
211 u32 lrda;
212
213 dma_addr_t tx_fd_dma;
214 dma_addr_t rx_fd_dma;
215 dma_addr_t iqtx_dma;
216 dma_addr_t iqrx_dma;
217
218 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
219
220 struct timer_list timer;
221
222 struct dscc4_pci_priv *pci_priv;
223 spinlock_t lock;
224
225 int dev_id;
226 volatile u32 flags;
227 u32 timer_help;
228
229 unsigned short encoding;
230 unsigned short parity;
231 struct net_device *dev;
232 sync_serial_settings settings;
233 void __iomem *base_addr;
234 u32 __pad __attribute__ ((aligned (4)));
235};
236
237/* GLOBAL registers definitions */
238#define GCMDR 0x00
239#define GSTAR 0x04
240#define GMODE 0x08
241#define IQLENR0 0x0C
242#define IQLENR1 0x10
243#define IQRX0 0x14
244#define IQTX0 0x24
245#define IQCFG 0x3c
246#define FIFOCR1 0x44
247#define FIFOCR2 0x48
248#define FIFOCR3 0x4c
249#define FIFOCR4 0x34
250#define CH0CFG 0x50
251#define CH0BRDA 0x54
252#define CH0BTDA 0x58
253#define CH0FRDA 0x98
254#define CH0FTDA 0xb0
255#define CH0LRDA 0xc8
256#define CH0LTDA 0xe0
257
258/* SCC registers definitions */
259#define SCC_START 0x0100
260#define SCC_OFFSET 0x80
261#define CMDR 0x00
262#define STAR 0x04
263#define CCR0 0x08
264#define CCR1 0x0c
265#define CCR2 0x10
266#define BRR 0x2C
267#define RLCR 0x40
268#define IMR 0x54
269#define ISR 0x58
270
271#define GPDIR 0x0400
272#define GPDATA 0x0404
273#define GPIM 0x0408
274
275/* Bit masks */
276#define EncodingMask 0x00700000
277#define CrcMask 0x00000003
278
279#define IntRxScc0 0x10000000
280#define IntTxScc0 0x01000000
281
282#define TxPollCmd 0x00000400
283#define RxActivate 0x08000000
284#define MTFi 0x04000000
285#define Rdr 0x00400000
286#define Rdt 0x00200000
287#define Idr 0x00100000
288#define Idt 0x00080000
289#define TxSccRes 0x01000000
290#define RxSccRes 0x00010000
291#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
292#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
293
294#define Ccr0ClockMask 0x0000003f
295#define Ccr1LoopMask 0x00000200
296#define IsrMask 0x000fffff
297#define BrrExpMask 0x00000f00
298#define BrrMultMask 0x0000003f
299#define EncodingMask 0x00700000
300#define Hold 0x40000000
301#define SccBusy 0x10000000
302#define PowerUp 0x80000000
303#define Vis 0x00001000
304#define FrameOk (FrameVfr | FrameCrc)
305#define FrameVfr 0x80
306#define FrameRdo 0x40
307#define FrameCrc 0x20
308#define FrameRab 0x10
309#define FrameAborted 0x00000200
310#define FrameEnd 0x80000000
311#define DataComplete 0x40000000
312#define LengthCheck 0x00008000
313#define SccEvt 0x02000000
314#define NoAck 0x00000200
315#define Action 0x00000001
316#define HiDesc 0x20000000
317
318/* SCC events */
319#define RxEvt 0xf0000000
320#define TxEvt 0x0f000000
321#define Alls 0x00040000
322#define Xdu 0x00010000
323#define Cts 0x00004000
324#define Xmr 0x00002000
325#define Xpr 0x00001000
326#define Rdo 0x00000080
327#define Rfs 0x00000040
328#define Cd 0x00000004
329#define Rfo 0x00000002
330#define Flex 0x00000001
331
332/* DMA core events */
333#define Cfg 0x00200000
334#define Hi 0x00040000
335#define Fi 0x00020000
336#define Err 0x00010000
337#define Arf 0x00000002
338#define ArAck 0x00000001
339
340/* State flags */
341#define Ready 0x00000000
342#define NeedIDR 0x00000001
343#define NeedIDT 0x00000002
344#define RdoSet 0x00000004
345#define FakeReset 0x00000008
346
347/* Don't mask RDO. Ever. */
348#ifdef DSCC4_POLLING
349#define EventsMask 0xfffeef7f
350#else
351#define EventsMask 0xfffa8f7a
352#endif
353
354/* Functions prototypes */
355static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
356static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
357static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
358static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
359static int dscc4_open(struct net_device *);
360static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
361static int dscc4_close(struct net_device *);
362static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
363static int dscc4_init_ring(struct net_device *);
364static void dscc4_release_ring(struct dscc4_dev_priv *);
365static void dscc4_timer(unsigned long);
366static void dscc4_tx_timeout(struct net_device *);
367static irqreturn_t dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs);
368static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
369static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
370#ifdef DSCC4_POLLING
371static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
372#endif
373
374static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
375{
376 return dev_to_hdlc(dev)->priv;
377}
378
379static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
380{
381 return p->dev;
382}
383
384static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
385 struct net_device *dev, int offset)
386{
387 u32 state;
388
389 /* Cf scc_writel for concern regarding thread-safety */
390 state = dpriv->scc_regs[offset >> 2];
391 state &= ~mask;
392 state |= value;
393 dpriv->scc_regs[offset >> 2] = state;
394 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
395}
396
397static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
398 struct net_device *dev, int offset)
399{
400 /*
401 * Thread-UNsafe.
402 * As of 2002/02/16, there are no thread racing for access.
403 */
404 dpriv->scc_regs[offset >> 2] = bits;
405 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
406}
407
408static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
409{
410 return dpriv->scc_regs[offset >> 2];
411}
412
413static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
414{
415 /* Cf errata DS5 p.4 */
416 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
417 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
418}
419
420static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
421 struct net_device *dev)
422{
423 dpriv->ltda = dpriv->tx_fd_dma +
424 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
425 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
426 /* Flush posted writes *NOW* */
427 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
428}
429
430static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
431 struct net_device *dev)
432{
433 dpriv->lrda = dpriv->rx_fd_dma +
434 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
435 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
436}
437
438static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
439{
440 return dpriv->tx_current == dpriv->tx_dirty;
441}
442
443static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
444 struct net_device *dev)
445{
446 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
447}
448
449int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev,
450 const char *msg)
451{
452 int ret = 0;
453
454 if (debug > 1) {
455 if (SOURCE_ID(state) != dpriv->dev_id) {
456 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
457 dev->name, msg, SOURCE_ID(state), state );
458 ret = -1;
459 }
460 if (state & 0x0df80c00) {
461 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
462 dev->name, msg, state);
463 ret = -1;
464 }
465 }
466 return ret;
467}
468
469void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv,
470 char *msg)
471{
472 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
473 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
474}
475
476static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
477{
478 struct pci_dev *pdev = dpriv->pci_priv->pdev;
479 struct TxFD *tx_fd = dpriv->tx_fd;
480 struct RxFD *rx_fd = dpriv->rx_fd;
481 struct sk_buff **skbuff;
482 int i;
483
484 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
485 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
486
487 skbuff = dpriv->tx_skbuff;
488 for (i = 0; i < TX_RING_SIZE; i++) {
489 if (*skbuff) {
490 pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len,
491 PCI_DMA_TODEVICE);
492 dev_kfree_skb(*skbuff);
493 }
494 skbuff++;
495 tx_fd++;
496 }
497
498 skbuff = dpriv->rx_skbuff;
499 for (i = 0; i < RX_RING_SIZE; i++) {
500 if (*skbuff) {
501 pci_unmap_single(pdev, rx_fd->data,
502 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
503 dev_kfree_skb(*skbuff);
504 }
505 skbuff++;
506 rx_fd++;
507 }
508}
509
510inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev)
511{
512 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
513 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
514 const int len = RX_MAX(HDLC_MAX_MRU);
515 struct sk_buff *skb;
516 int ret = 0;
517
518 skb = dev_alloc_skb(len);
519 dpriv->rx_skbuff[dirty] = skb;
520 if (skb) {
521 skb->protocol = hdlc_type_trans(skb, dev);
522 rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
523 len, PCI_DMA_FROMDEVICE);
524 } else {
525 rx_fd->data = (u32) NULL;
526 ret = -1;
527 }
528 return ret;
529}
530
531/*
532 * IRQ/thread/whatever safe
533 */
534static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
535 struct net_device *dev, char *msg)
536{
537 s8 i = 0;
538
539 do {
540 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
541 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
542 msg, i);
543 goto done;
544 }
545 set_current_state(TASK_UNINTERRUPTIBLE);
546 schedule_timeout(10);
547 rmb();
548 } while (++i > 0);
549 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
550done:
551 return (i >= 0) ? i : -EAGAIN;
552}
553
554static int dscc4_do_action(struct net_device *dev, char *msg)
555{
556 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
557 s16 i = 0;
558
559 writel(Action, ioaddr + GCMDR);
560 ioaddr += GSTAR;
561 do {
562 u32 state = readl(ioaddr);
563
564 if (state & ArAck) {
565 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
566 writel(ArAck, ioaddr);
567 goto done;
568 } else if (state & Arf) {
569 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
570 writel(Arf, ioaddr);
571 i = -1;
572 goto done;
573 }
574 rmb();
575 } while (++i > 0);
576 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
577done:
578 return i;
579}
580
581static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
582{
583 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
584 s8 i = 0;
585
586 do {
587 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
588 (dpriv->iqtx[cur] & Xpr))
589 break;
590 smp_rmb();
591 set_current_state(TASK_UNINTERRUPTIBLE);
592 schedule_timeout(10);
593 } while (++i > 0);
594
595 return (i >= 0 ) ? i : -EAGAIN;
596}
597
598#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
599static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
600{
601 unsigned long flags;
602
603 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
604 /* Cf errata DS5 p.6 */
605 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
606 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
607 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
608 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
609 writel(Action, dpriv->base_addr + GCMDR);
610 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
611}
612
613#endif
614
615#if 0
616static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
617{
618 u16 i = 0;
619
620 /* Cf errata DS5 p.7 */
621 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
622 scc_writel(0x00050000, dpriv, dev, CCR2);
623 /*
624 * Must be longer than the time required to fill the fifo.
625 */
626 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
627 udelay(1);
628 wmb();
629 }
630
631 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
632 if (dscc4_do_action(dev, "Rdt") < 0)
633 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
634}
635#endif
636
637/* TODO: (ab)use this function to refill a completely depleted RX ring. */
638static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
639 struct net_device *dev)
640{
641 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
642 struct net_device_stats *stats = hdlc_stats(dev);
643 struct pci_dev *pdev = dpriv->pci_priv->pdev;
644 struct sk_buff *skb;
645 int pkt_len;
646
647 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
648 if (!skb) {
649 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
650 goto refill;
651 }
652 pkt_len = TO_SIZE(rx_fd->state2);
653 pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
654 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
655 stats->rx_packets++;
656 stats->rx_bytes += pkt_len;
657 skb_put(skb, pkt_len);
658 if (netif_running(dev))
659 skb->protocol = hdlc_type_trans(skb, dev);
660 skb->dev->last_rx = jiffies;
661 netif_rx(skb);
662 } else {
663 if (skb->data[pkt_len] & FrameRdo)
664 stats->rx_fifo_errors++;
665 else if (!(skb->data[pkt_len] | ~FrameCrc))
666 stats->rx_crc_errors++;
667 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
668 stats->rx_length_errors++;
669 else
670 stats->rx_errors++;
671 dev_kfree_skb_irq(skb);
672 }
673refill:
674 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
675 if (try_get_rx_skb(dpriv, dev) < 0)
676 break;
677 dpriv->rx_dirty++;
678 }
679 dscc4_rx_update(dpriv, dev);
680 rx_fd->state2 = 0x00000000;
681 rx_fd->end = 0xbabeface;
682}
683
684static void dscc4_free1(struct pci_dev *pdev)
685{
686 struct dscc4_pci_priv *ppriv;
687 struct dscc4_dev_priv *root;
688 int i;
689
690 ppriv = pci_get_drvdata(pdev);
691 root = ppriv->root;
692
693 for (i = 0; i < dev_per_card; i++)
694 unregister_hdlc_device(dscc4_to_dev(root + i));
695
696 pci_set_drvdata(pdev, NULL);
697
698 for (i = 0; i < dev_per_card; i++)
699 free_netdev(root[i].dev);
700 kfree(root);
701 kfree(ppriv);
702}
703
704static int __devinit dscc4_init_one(struct pci_dev *pdev,
705 const struct pci_device_id *ent)
706{
707 struct dscc4_pci_priv *priv;
708 struct dscc4_dev_priv *dpriv;
709 void __iomem *ioaddr;
710 int i, rc;
711
712 printk(KERN_DEBUG "%s", version);
713
714 rc = pci_enable_device(pdev);
715 if (rc < 0)
716 goto out;
717
718 rc = pci_request_region(pdev, 0, "registers");
719 if (rc < 0) {
720 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
721 DRV_NAME);
722 goto err_disable_0;
723 }
724 rc = pci_request_region(pdev, 1, "LBI interface");
725 if (rc < 0) {
726 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
727 DRV_NAME);
728 goto err_free_mmio_region_1;
729 }
730
731 ioaddr = ioremap(pci_resource_start(pdev, 0),
732 pci_resource_len(pdev, 0));
733 if (!ioaddr) {
734 printk(KERN_ERR "%s: cannot remap MMIO region %lx @ %lx\n",
735 DRV_NAME, pci_resource_len(pdev, 0),
736 pci_resource_start(pdev, 0));
737 rc = -EIO;
738 goto err_free_mmio_regions_2;
739 }
740 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d\n",
741 pci_resource_start(pdev, 0),
742 pci_resource_start(pdev, 1), pdev->irq);
743
744 /* Cf errata DS5 p.2 */
745 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
746 pci_set_master(pdev);
747
748 rc = dscc4_found1(pdev, ioaddr);
749 if (rc < 0)
750 goto err_iounmap_3;
751
752 priv = pci_get_drvdata(pdev);
753
754 rc = request_irq(pdev->irq, dscc4_irq, SA_SHIRQ, DRV_NAME, priv->root);
755 if (rc < 0) {
756 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
757 goto err_release_4;
758 }
759
760 /* power up/little endian/dma core controlled via lrda/ltda */
761 writel(0x00000001, ioaddr + GMODE);
762 /* Shared interrupt queue */
763 {
764 u32 bits;
765
766 bits = (IRQ_RING_SIZE >> 5) - 1;
767 bits |= bits << 4;
768 bits |= bits << 8;
769 bits |= bits << 16;
770 writel(bits, ioaddr + IQLENR0);
771 }
772 /* Global interrupt queue */
773 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
774 priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
775 IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
776 if (!priv->iqcfg)
777 goto err_free_irq_5;
778 writel(priv->iqcfg_dma, ioaddr + IQCFG);
779
780 rc = -ENOMEM;
781
782 /*
783 * SCC 0-3 private rx/tx irq structures
784 * IQRX/TXi needs to be set soon. Learned it the hard way...
785 */
786 for (i = 0; i < dev_per_card; i++) {
787 dpriv = priv->root + i;
788 dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
789 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
790 if (!dpriv->iqtx)
791 goto err_free_iqtx_6;
792 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
793 }
794 for (i = 0; i < dev_per_card; i++) {
795 dpriv = priv->root + i;
796 dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
797 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
798 if (!dpriv->iqrx)
799 goto err_free_iqrx_7;
800 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
801 }
802
803 /* Cf application hint. Beware of hard-lock condition on threshold. */
804 writel(0x42104000, ioaddr + FIFOCR1);
805 //writel(0x9ce69800, ioaddr + FIFOCR2);
806 writel(0xdef6d800, ioaddr + FIFOCR2);
807 //writel(0x11111111, ioaddr + FIFOCR4);
808 writel(0x18181818, ioaddr + FIFOCR4);
809 // FIXME: should depend on the chipset revision
810 writel(0x0000000e, ioaddr + FIFOCR3);
811
812 writel(0xff200001, ioaddr + GCMDR);
813
814 rc = 0;
815out:
816 return rc;
817
818err_free_iqrx_7:
819 while (--i >= 0) {
820 dpriv = priv->root + i;
821 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
822 dpriv->iqrx, dpriv->iqrx_dma);
823 }
824 i = dev_per_card;
825err_free_iqtx_6:
826 while (--i >= 0) {
827 dpriv = priv->root + i;
828 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
829 dpriv->iqtx, dpriv->iqtx_dma);
830 }
831 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
832 priv->iqcfg_dma);
833err_free_irq_5:
834 free_irq(pdev->irq, priv->root);
835err_release_4:
836 dscc4_free1(pdev);
837err_iounmap_3:
838 iounmap (ioaddr);
839err_free_mmio_regions_2:
840 pci_release_region(pdev, 1);
841err_free_mmio_region_1:
842 pci_release_region(pdev, 0);
843err_disable_0:
844 pci_disable_device(pdev);
845 goto out;
846};
847
848/*
849 * Let's hope the default values are decent enough to protect my
850 * feet from the user's gun - Ueimor
851 */
852static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
853 struct net_device *dev)
854{
855 /* No interrupts, SCC core disabled. Let's relax */
856 scc_writel(0x00000000, dpriv, dev, CCR0);
857
858 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
859
860 /*
861 * No address recognition/crc-CCITT/cts enabled
862 * Shared flags transmission disabled - cf errata DS5 p.11
863 * Carrier detect disabled - cf errata p.14
864 * FIXME: carrier detection/polarity may be handled more gracefully.
865 */
866 scc_writel(0x02408000, dpriv, dev, CCR1);
867
868 /* crc not forwarded - Cf errata DS5 p.11 */
869 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
870 // crc forwarded
871 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
872}
873
874static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
875{
876 int ret = 0;
877
878 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
879 ret = -EOPNOTSUPP;
880 else
881 dpriv->pci_priv->xtal_hz = hz;
882
883 return ret;
884}
885
886static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
887{
888 struct dscc4_pci_priv *ppriv;
889 struct dscc4_dev_priv *root;
890 int i, ret = -ENOMEM;
891
892 root = kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL);
893 if (!root) {
894 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
895 goto err_out;
896 }
897 memset(root, 0, dev_per_card*sizeof(*root));
898
899 for (i = 0; i < dev_per_card; i++) {
900 root[i].dev = alloc_hdlcdev(root + i);
901 if (!root[i].dev)
902 goto err_free_dev;
903 }
904
905 ppriv = kmalloc(sizeof(*ppriv), GFP_KERNEL);
906 if (!ppriv) {
907 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
908 goto err_free_dev;
909 }
910 memset(ppriv, 0, sizeof(struct dscc4_pci_priv));
911
912 ppriv->root = root;
913 spin_lock_init(&ppriv->lock);
914
915 for (i = 0; i < dev_per_card; i++) {
916 struct dscc4_dev_priv *dpriv = root + i;
917 struct net_device *d = dscc4_to_dev(dpriv);
918 hdlc_device *hdlc = dev_to_hdlc(d);
919
920 d->base_addr = (unsigned long)ioaddr;
921 d->init = NULL;
922 d->irq = pdev->irq;
923 d->open = dscc4_open;
924 d->stop = dscc4_close;
925 d->set_multicast_list = NULL;
926 d->do_ioctl = dscc4_ioctl;
927 d->tx_timeout = dscc4_tx_timeout;
928 d->watchdog_timeo = TX_TIMEOUT;
929 SET_MODULE_OWNER(d);
930 SET_NETDEV_DEV(d, &pdev->dev);
931
932 dpriv->dev_id = i;
933 dpriv->pci_priv = ppriv;
934 dpriv->base_addr = ioaddr;
935 spin_lock_init(&dpriv->lock);
936
937 hdlc->xmit = dscc4_start_xmit;
938 hdlc->attach = dscc4_hdlc_attach;
939
940 dscc4_init_registers(dpriv, d);
941 dpriv->parity = PARITY_CRC16_PR0_CCITT;
942 dpriv->encoding = ENCODING_NRZ;
943
944 ret = dscc4_init_ring(d);
945 if (ret < 0)
946 goto err_unregister;
947
948 ret = register_hdlc_device(d);
949 if (ret < 0) {
950 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
951 dscc4_release_ring(dpriv);
952 goto err_unregister;
953 }
954 }
955
956 ret = dscc4_set_quartz(root, quartz);
957 if (ret < 0)
958 goto err_unregister;
959
960 pci_set_drvdata(pdev, ppriv);
961 return ret;
962
963err_unregister:
964 while (i-- > 0) {
965 dscc4_release_ring(root + i);
966 unregister_hdlc_device(dscc4_to_dev(root + i));
967 }
968 kfree(ppriv);
969 i = dev_per_card;
970err_free_dev:
971 while (i-- > 0)
972 free_netdev(root[i].dev);
973 kfree(root);
974err_out:
975 return ret;
976};
977
978/* FIXME: get rid of the unneeded code */
979static void dscc4_timer(unsigned long data)
980{
981 struct net_device *dev = (struct net_device *)data;
982 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
983// struct dscc4_pci_priv *ppriv;
984
985 goto done;
986done:
987 dpriv->timer.expires = jiffies + TX_TIMEOUT;
988 add_timer(&dpriv->timer);
989}
990
991static void dscc4_tx_timeout(struct net_device *dev)
992{
993 /* FIXME: something is missing there */
994}
995
996static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
997{
998 sync_serial_settings *settings = &dpriv->settings;
999
1000 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1001 struct net_device *dev = dscc4_to_dev(dpriv);
1002
1003 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1004 return -1;
1005 }
1006 return 0;
1007}
1008
1009#ifdef CONFIG_DSCC4_PCI_RST
1010/*
1011 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1012 * so as to provide a safe way to reset the asic while not the whole machine
1013 * rebooting.
1014 *
1015 * This code doesn't need to be efficient. Keep It Simple
1016 */
1017static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1018{
1019 int i;
1020
1021 down(&dscc4_sem);
1022 for (i = 0; i < 16; i++)
1023 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1024
1025 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1026 writel(0x001c0000, ioaddr + GMODE);
1027 /* Configure GPIO port as output */
1028 writel(0x0000ffff, ioaddr + GPDIR);
1029 /* Disable interruption */
1030 writel(0x0000ffff, ioaddr + GPIM);
1031
1032 writel(0x0000ffff, ioaddr + GPDATA);
1033 writel(0x00000000, ioaddr + GPDATA);
1034
1035 /* Flush posted writes */
1036 readl(ioaddr + GSTAR);
1037
1038 set_current_state(TASK_UNINTERRUPTIBLE);
1039 schedule_timeout(10);
1040
1041 for (i = 0; i < 16; i++)
1042 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1043 up(&dscc4_sem);
1044}
1045#else
1046#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1047#endif /* CONFIG_DSCC4_PCI_RST */
1048
1049static int dscc4_open(struct net_device *dev)
1050{
1051 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1052 struct dscc4_pci_priv *ppriv;
1053 int ret = -EAGAIN;
1054
1055 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1056 goto err;
1057
1058 if ((ret = hdlc_open(dev)))
1059 goto err;
1060
1061 ppriv = dpriv->pci_priv;
1062
1063 /*
1064 * Due to various bugs, there is no way to reliably reset a
1065 * specific port (manufacturer's dependant special PCI #RST wiring
1066 * apart: it affects all ports). Thus the device goes in the best
1067 * silent mode possible at dscc4_close() time and simply claims to
1068 * be up if it's opened again. It still isn't possible to change
1069 * the HDLC configuration without rebooting but at least the ports
1070 * can be up/down ifconfig'ed without killing the host.
1071 */
1072 if (dpriv->flags & FakeReset) {
1073 dpriv->flags &= ~FakeReset;
1074 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1075 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1076 scc_writel(EventsMask, dpriv, dev, IMR);
1077 printk(KERN_INFO "%s: up again.\n", dev->name);
1078 goto done;
1079 }
1080
1081 /* IDT+IDR during XPR */
1082 dpriv->flags = NeedIDR | NeedIDT;
1083
1084 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1085
1086 /*
1087 * The following is a bit paranoid...
1088 *
1089 * NB: the datasheet "...CEC will stay active if the SCC is in
1090 * power-down mode or..." and CCR2.RAC = 1 are two different
1091 * situations.
1092 */
1093 if (scc_readl_star(dpriv, dev) & SccBusy) {
1094 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1095 ret = -EAGAIN;
1096 goto err_out;
1097 } else
1098 printk(KERN_INFO "%s: available. Good\n", dev->name);
1099
1100 scc_writel(EventsMask, dpriv, dev, IMR);
1101
1102 /* Posted write is flushed in the wait_ack loop */
1103 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1104
1105 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1106 goto err_disable_scc_events;
1107
1108 /*
1109 * I would expect XPR near CE completion (before ? after ?).
1110 * At worst, this code won't see a late XPR and people
1111 * will have to re-issue an ifconfig (this is harmless).
1112 * WARNING, a really missing XPR usually means a hardware
1113 * reset is needed. Suggestions anyone ?
1114 */
1115 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1116 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1117 goto err_disable_scc_events;
1118 }
1119
1120 if (debug > 2)
1121 dscc4_tx_print(dev, dpriv, "Open");
1122
1123done:
1124 netif_start_queue(dev);
1125
1126 init_timer(&dpriv->timer);
1127 dpriv->timer.expires = jiffies + 10*HZ;
1128 dpriv->timer.data = (unsigned long)dev;
1129 dpriv->timer.function = &dscc4_timer;
1130 add_timer(&dpriv->timer);
1131 netif_carrier_on(dev);
1132
1133 return 0;
1134
1135err_disable_scc_events:
1136 scc_writel(0xffffffff, dpriv, dev, IMR);
1137 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138err_out:
1139 hdlc_close(dev);
1140err:
1141 return ret;
1142}
1143
1144#ifdef DSCC4_POLLING
1145static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1146{
1147 /* FIXME: it's gonna be easy (TM), for sure */
1148}
1149#endif /* DSCC4_POLLING */
1150
1151static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1152{
1153 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1154 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1155 struct TxFD *tx_fd;
1156 int next;
1157
1158 next = dpriv->tx_current%TX_RING_SIZE;
1159 dpriv->tx_skbuff[next] = skb;
1160 tx_fd = dpriv->tx_fd + next;
1161 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1162 tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
1163 PCI_DMA_TODEVICE);
1164 tx_fd->complete = 0x00000000;
1165 tx_fd->jiffies = jiffies;
1166 mb();
1167
1168#ifdef DSCC4_POLLING
1169 spin_lock(&dpriv->lock);
1170 while (dscc4_tx_poll(dpriv, dev));
1171 spin_unlock(&dpriv->lock);
1172#endif
1173
1174 dev->trans_start = jiffies;
1175
1176 if (debug > 2)
1177 dscc4_tx_print(dev, dpriv, "Xmit");
1178 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1179 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1180 netif_stop_queue(dev);
1181
1182 if (dscc4_tx_quiescent(dpriv, dev))
1183 dscc4_do_tx(dpriv, dev);
1184
1185 return 0;
1186}
1187
1188static int dscc4_close(struct net_device *dev)
1189{
1190 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1191
1192 del_timer_sync(&dpriv->timer);
1193 netif_stop_queue(dev);
1194
1195 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1196 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1197 scc_writel(0xffffffff, dpriv, dev, IMR);
1198
1199 dpriv->flags |= FakeReset;
1200
1201 hdlc_close(dev);
1202
1203 return 0;
1204}
1205
1206static inline int dscc4_check_clock_ability(int port)
1207{
1208 int ret = 0;
1209
1210#ifdef CONFIG_DSCC4_PCISYNC
1211 if (port >= 2)
1212 ret = -1;
1213#endif
1214 return ret;
1215}
1216
1217/*
1218 * DS1 p.137: "There are a total of 13 different clocking modes..."
1219 * ^^
1220 * Design choices:
1221 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1222 * Clock mode 3b _should_ work but the testing seems to make this point
1223 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1224 * This is supposed to provide least surprise "DTE like" behavior.
1225 * - if line rate is specified, clocks are assumed to be locally generated.
1226 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1227 * between these it automagically done according on the required frequency
1228 * scaling. Of course some rounding may take place.
1229 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1230 * appropriate external clocking device for testing.
1231 * - no time-slot/clock mode 5: shameless lazyness.
1232 *
1233 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1234 *
1235 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1236 * won't pass the init sequence. For example, straight back-to-back DTE without
1237 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1238 * called.
1239 *
1240 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1241 * DS0 for example)
1242 *
1243 * Clock mode related bits of CCR0:
1244 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1245 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1246 * | | +-------- High Speed: say 0
1247 * | | | +-+-+-- Clock Mode: 0..7
1248 * | | | | | |
1249 * -+-+-+-+-+-+-+-+
1250 * x|x|5|4|3|2|1|0| lower bits
1251 *
1252 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1253 * +-+-+-+------------------ M (0..15)
1254 * | | | | +-+-+-+-+-+-- N (0..63)
1255 * 0 0 0 0 | | | | 0 0 | | | | | |
1256 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1257 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1258 *
1259 */
1260static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1261{
1262 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1263 int ret = -1;
1264 u32 brr;
1265
1266 *state &= ~Ccr0ClockMask;
1267 if (*bps) { /* Clock generated - required for DCE */
1268 u32 n = 0, m = 0, divider;
1269 int xtal;
1270
1271 xtal = dpriv->pci_priv->xtal_hz;
1272 if (!xtal)
1273 goto done;
1274 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1275 goto done;
1276 divider = xtal / *bps;
1277 if (divider > BRR_DIVIDER_MAX) {
1278 divider >>= 4;
1279 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1280 } else
1281 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1282 if (divider >> 22) {
1283 n = 63;
1284 m = 15;
1285 } else if (divider) {
1286 /* Extraction of the 6 highest weighted bits */
1287 m = 0;
1288 while (0xffffffc0 & divider) {
1289 m++;
1290 divider >>= 1;
1291 }
1292 n = divider;
1293 }
1294 brr = (m << 8) | n;
1295 divider = n << m;
1296 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1297 divider <<= 4;
1298 *bps = xtal / divider;
1299 } else {
1300 /*
1301 * External clock - DTE
1302 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1303 * Nothing more to be done
1304 */
1305 brr = 0;
1306 }
1307 scc_writel(brr, dpriv, dev, BRR);
1308 ret = 0;
1309done:
1310 return ret;
1311}
1312
1313static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1314{
1315 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1316 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1317 const size_t size = sizeof(dpriv->settings);
1318 int ret = 0;
1319
1320 if (dev->flags & IFF_UP)
1321 return -EBUSY;
1322
1323 if (cmd != SIOCWANDEV)
1324 return -EOPNOTSUPP;
1325
1326 switch(ifr->ifr_settings.type) {
1327 case IF_GET_IFACE:
1328 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1329 if (ifr->ifr_settings.size < size) {
1330 ifr->ifr_settings.size = size; /* data size wanted */
1331 return -ENOBUFS;
1332 }
1333 if (copy_to_user(line, &dpriv->settings, size))
1334 return -EFAULT;
1335 break;
1336
1337 case IF_IFACE_SYNC_SERIAL:
1338 if (!capable(CAP_NET_ADMIN))
1339 return -EPERM;
1340
1341 if (dpriv->flags & FakeReset) {
1342 printk(KERN_INFO "%s: please reset the device"
1343 " before this command\n", dev->name);
1344 return -EPERM;
1345 }
1346 if (copy_from_user(&dpriv->settings, line, size))
1347 return -EFAULT;
1348 ret = dscc4_set_iface(dpriv, dev);
1349 break;
1350
1351 default:
1352 ret = hdlc_ioctl(dev, ifr, cmd);
1353 break;
1354 }
1355
1356 return ret;
1357}
1358
1359static int dscc4_match(struct thingie *p, int value)
1360{
1361 int i;
1362
1363 for (i = 0; p[i].define != -1; i++) {
1364 if (value == p[i].define)
1365 break;
1366 }
1367 if (p[i].define == -1)
1368 return -1;
1369 else
1370 return i;
1371}
1372
1373static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1374 struct net_device *dev)
1375{
1376 sync_serial_settings *settings = &dpriv->settings;
1377 int ret = -EOPNOTSUPP;
1378 u32 bps, state;
1379
1380 bps = settings->clock_rate;
1381 state = scc_readl(dpriv, CCR0);
1382 if (dscc4_set_clock(dev, &bps, &state) < 0)
1383 goto done;
1384 if (bps) { /* DCE */
1385 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1386 if (settings->clock_rate != bps) {
1387 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1388 dev->name, settings->clock_rate, bps);
1389 settings->clock_rate = bps;
1390 }
1391 } else { /* DTE */
1392 state |= PowerUp | Vis;
1393 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1394 }
1395 scc_writel(state, dpriv, dev, CCR0);
1396 ret = 0;
1397done:
1398 return ret;
1399}
1400
1401static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1402 struct net_device *dev)
1403{
1404 struct thingie encoding[] = {
1405 { ENCODING_NRZ, 0x00000000 },
1406 { ENCODING_NRZI, 0x00200000 },
1407 { ENCODING_FM_MARK, 0x00400000 },
1408 { ENCODING_FM_SPACE, 0x00500000 },
1409 { ENCODING_MANCHESTER, 0x00600000 },
1410 { -1, 0}
1411 };
1412 int i, ret = 0;
1413
1414 i = dscc4_match(encoding, dpriv->encoding);
1415 if (i >= 0)
1416 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1417 else
1418 ret = -EOPNOTSUPP;
1419 return ret;
1420}
1421
1422static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1423 struct net_device *dev)
1424{
1425 sync_serial_settings *settings = &dpriv->settings;
1426 u32 state;
1427
1428 state = scc_readl(dpriv, CCR1);
1429 if (settings->loopback) {
1430 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1431 state |= 0x00000100;
1432 } else {
1433 printk(KERN_DEBUG "%s: normal\n", dev->name);
1434 state &= ~0x00000100;
1435 }
1436 scc_writel(state, dpriv, dev, CCR1);
1437 return 0;
1438}
1439
1440static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1441 struct net_device *dev)
1442{
1443 struct thingie crc[] = {
1444 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1445 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1446 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1447 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1448 };
1449 int i, ret = 0;
1450
1451 i = dscc4_match(crc, dpriv->parity);
1452 if (i >= 0)
1453 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1454 else
1455 ret = -EOPNOTSUPP;
1456 return ret;
1457}
1458
1459static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1460{
1461 struct {
1462 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1463 } *p, do_setting[] = {
1464 { dscc4_encoding_setting },
1465 { dscc4_clock_setting },
1466 { dscc4_loopback_setting },
1467 { dscc4_crc_setting },
1468 { NULL }
1469 };
1470 int ret = 0;
1471
1472 for (p = do_setting; p->action; p++) {
1473 if ((ret = p->action(dpriv, dev)) < 0)
1474 break;
1475 }
1476 return ret;
1477}
1478
1479static irqreturn_t dscc4_irq(int irq, void *token, struct pt_regs *ptregs)
1480{
1481 struct dscc4_dev_priv *root = token;
1482 struct dscc4_pci_priv *priv;
1483 struct net_device *dev;
1484 void __iomem *ioaddr;
1485 u32 state;
1486 unsigned long flags;
1487 int i, handled = 1;
1488
1489 priv = root->pci_priv;
1490 dev = dscc4_to_dev(root);
1491
1492 spin_lock_irqsave(&priv->lock, flags);
1493
1494 ioaddr = root->base_addr;
1495
1496 state = readl(ioaddr + GSTAR);
1497 if (!state) {
1498 handled = 0;
1499 goto out;
1500 }
1501 if (debug > 3)
1502 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1503 writel(state, ioaddr + GSTAR);
1504
1505 if (state & Arf) {
1506 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1507 dev->name);
1508 goto out;
1509 }
1510 state &= ~ArAck;
1511 if (state & Cfg) {
1512 if (debug > 0)
1513 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1514 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
1515 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1516 if (!(state &= ~Cfg))
1517 goto out;
1518 }
1519 if (state & RxEvt) {
1520 i = dev_per_card - 1;
1521 do {
1522 dscc4_rx_irq(priv, root + i);
1523 } while (--i >= 0);
1524 state &= ~RxEvt;
1525 }
1526 if (state & TxEvt) {
1527 i = dev_per_card - 1;
1528 do {
1529 dscc4_tx_irq(priv, root + i);
1530 } while (--i >= 0);
1531 state &= ~TxEvt;
1532 }
1533out:
1534 spin_unlock_irqrestore(&priv->lock, flags);
1535 return IRQ_RETVAL(handled);
1536}
1537
1538static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1539 struct dscc4_dev_priv *dpriv)
1540{
1541 struct net_device *dev = dscc4_to_dev(dpriv);
1542 u32 state;
1543 int cur, loop = 0;
1544
1545try:
1546 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1547 state = dpriv->iqtx[cur];
1548 if (!state) {
1549 if (debug > 4)
1550 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1551 state);
1552 if ((debug > 1) && (loop > 1))
1553 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1554 if (loop && netif_queue_stopped(dev))
1555 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1556 netif_wake_queue(dev);
1557
1558 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1559 !dscc4_tx_done(dpriv))
1560 dscc4_do_tx(dpriv, dev);
1561 return;
1562 }
1563 loop++;
1564 dpriv->iqtx[cur] = 0;
1565 dpriv->iqtx_current++;
1566
1567 if (state_check(state, dpriv, dev, "Tx") < 0)
1568 return;
1569
1570 if (state & SccEvt) {
1571 if (state & Alls) {
1572 struct net_device_stats *stats = hdlc_stats(dev);
1573 struct sk_buff *skb;
1574 struct TxFD *tx_fd;
1575
1576 if (debug > 2)
1577 dscc4_tx_print(dev, dpriv, "Alls");
1578 /*
1579 * DataComplete can't be trusted for Tx completion.
1580 * Cf errata DS5 p.8
1581 */
1582 cur = dpriv->tx_dirty%TX_RING_SIZE;
1583 tx_fd = dpriv->tx_fd + cur;
1584 skb = dpriv->tx_skbuff[cur];
1585 if (skb) {
1586 pci_unmap_single(ppriv->pdev, tx_fd->data,
1587 skb->len, PCI_DMA_TODEVICE);
1588 if (tx_fd->state & FrameEnd) {
1589 stats->tx_packets++;
1590 stats->tx_bytes += skb->len;
1591 }
1592 dev_kfree_skb_irq(skb);
1593 dpriv->tx_skbuff[cur] = NULL;
1594 ++dpriv->tx_dirty;
1595 } else {
1596 if (debug > 1)
1597 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1598 dev->name, cur);
1599 }
1600 /*
1601 * If the driver ends sending crap on the wire, it
1602 * will be way easier to diagnose than the (not so)
1603 * random freeze induced by null sized tx frames.
1604 */
1605 tx_fd->data = tx_fd->next;
1606 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1607 tx_fd->complete = 0x00000000;
1608 tx_fd->jiffies = 0;
1609
1610 if (!(state &= ~Alls))
1611 goto try;
1612 }
1613 /*
1614 * Transmit Data Underrun
1615 */
1616 if (state & Xdu) {
1617 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1618 dpriv->flags = NeedIDT;
1619 /* Tx reset */
1620 writel(MTFi | Rdt,
1621 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1622 writel(Action, dpriv->base_addr + GCMDR);
1623 return;
1624 }
1625 if (state & Cts) {
1626 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1627 if (!(state &= ~Cts)) /* DEBUG */
1628 goto try;
1629 }
1630 if (state & Xmr) {
1631 /* Frame needs to be sent again - FIXME */
1632 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1633 if (!(state &= ~Xmr)) /* DEBUG */
1634 goto try;
1635 }
1636 if (state & Xpr) {
1637 void __iomem *scc_addr;
1638 unsigned long ring;
1639 int i;
1640
1641 /*
1642 * - the busy condition happens (sometimes);
1643 * - it doesn't seem to make the handler unreliable.
1644 */
1645 for (i = 1; i; i <<= 1) {
1646 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1647 break;
1648 }
1649 if (!i)
1650 printk(KERN_INFO "%s busy in irq\n", dev->name);
1651
1652 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1653 /* Keep this order: IDT before IDR */
1654 if (dpriv->flags & NeedIDT) {
1655 if (debug > 2)
1656 dscc4_tx_print(dev, dpriv, "Xpr");
1657 ring = dpriv->tx_fd_dma +
1658 (dpriv->tx_dirty%TX_RING_SIZE)*
1659 sizeof(struct TxFD);
1660 writel(ring, scc_addr + CH0BTDA);
1661 dscc4_do_tx(dpriv, dev);
1662 writel(MTFi | Idt, scc_addr + CH0CFG);
1663 if (dscc4_do_action(dev, "IDT") < 0)
1664 goto err_xpr;
1665 dpriv->flags &= ~NeedIDT;
1666 }
1667 if (dpriv->flags & NeedIDR) {
1668 ring = dpriv->rx_fd_dma +
1669 (dpriv->rx_current%RX_RING_SIZE)*
1670 sizeof(struct RxFD);
1671 writel(ring, scc_addr + CH0BRDA);
1672 dscc4_rx_update(dpriv, dev);
1673 writel(MTFi | Idr, scc_addr + CH0CFG);
1674 if (dscc4_do_action(dev, "IDR") < 0)
1675 goto err_xpr;
1676 dpriv->flags &= ~NeedIDR;
1677 smp_wmb();
1678 /* Activate receiver and misc */
1679 scc_writel(0x08050008, dpriv, dev, CCR2);
1680 }
1681 err_xpr:
1682 if (!(state &= ~Xpr))
1683 goto try;
1684 }
1685 if (state & Cd) {
1686 if (debug > 0)
1687 printk(KERN_INFO "%s: CD transition\n", dev->name);
1688 if (!(state &= ~Cd)) /* DEBUG */
1689 goto try;
1690 }
1691 } else { /* ! SccEvt */
1692 if (state & Hi) {
1693#ifdef DSCC4_POLLING
1694 while (!dscc4_tx_poll(dpriv, dev));
1695#endif
1696 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1697 state &= ~Hi;
1698 }
1699 if (state & Err) {
1700 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1701 hdlc_stats(dev)->tx_errors++;
1702 state &= ~Err;
1703 }
1704 }
1705 goto try;
1706}
1707
1708static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1709 struct dscc4_dev_priv *dpriv)
1710{
1711 struct net_device *dev = dscc4_to_dev(dpriv);
1712 u32 state;
1713 int cur;
1714
1715try:
1716 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1717 state = dpriv->iqrx[cur];
1718 if (!state)
1719 return;
1720 dpriv->iqrx[cur] = 0;
1721 dpriv->iqrx_current++;
1722
1723 if (state_check(state, dpriv, dev, "Rx") < 0)
1724 return;
1725
1726 if (!(state & SccEvt)){
1727 struct RxFD *rx_fd;
1728
1729 if (debug > 4)
1730 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1731 state);
1732 state &= 0x00ffffff;
1733 if (state & Err) { /* Hold or reset */
1734 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1735 cur = dpriv->rx_current%RX_RING_SIZE;
1736 rx_fd = dpriv->rx_fd + cur;
1737 /*
1738 * Presume we're not facing a DMAC receiver reset.
1739 * As We use the rx size-filtering feature of the
1740 * DSCC4, the beginning of a new frame is waiting in
1741 * the rx fifo. I bet a Receive Data Overflow will
1742 * happen most of time but let's try and avoid it.
1743 * Btw (as for RDO) if one experiences ERR whereas
1744 * the system looks rather idle, there may be a
1745 * problem with latency. In this case, increasing
1746 * RX_RING_SIZE may help.
1747 */
1748 //while (dpriv->rx_needs_refill) {
1749 while (!(rx_fd->state1 & Hold)) {
1750 rx_fd++;
1751 cur++;
1752 if (!(cur = cur%RX_RING_SIZE))
1753 rx_fd = dpriv->rx_fd;
1754 }
1755 //dpriv->rx_needs_refill--;
1756 try_get_rx_skb(dpriv, dev);
1757 if (!rx_fd->data)
1758 goto try;
1759 rx_fd->state1 &= ~Hold;
1760 rx_fd->state2 = 0x00000000;
1761 rx_fd->end = 0xbabeface;
1762 //}
1763 goto try;
1764 }
1765 if (state & Fi) {
1766 dscc4_rx_skb(dpriv, dev);
1767 goto try;
1768 }
1769 if (state & Hi ) { /* HI bit */
1770 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1771 state &= ~Hi;
1772 goto try;
1773 }
1774 } else { /* SccEvt */
1775 if (debug > 1) {
1776 //FIXME: verifier la presence de tous les evenements
1777 static struct {
1778 u32 mask;
1779 const char *irq_name;
1780 } evts[] = {
1781 { 0x00008000, "TIN"},
1782 { 0x00000020, "RSC"},
1783 { 0x00000010, "PCE"},
1784 { 0x00000008, "PLLA"},
1785 { 0, NULL}
1786 }, *evt;
1787
1788 for (evt = evts; evt->irq_name; evt++) {
1789 if (state & evt->mask) {
1790 printk(KERN_DEBUG "%s: %s\n",
1791 dev->name, evt->irq_name);
1792 if (!(state &= ~evt->mask))
1793 goto try;
1794 }
1795 }
1796 } else {
1797 if (!(state &= ~0x0000c03c))
1798 goto try;
1799 }
1800 if (state & Cts) {
1801 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1802 if (!(state &= ~Cts)) /* DEBUG */
1803 goto try;
1804 }
1805 /*
1806 * Receive Data Overflow (FIXME: fscked)
1807 */
1808 if (state & Rdo) {
1809 struct RxFD *rx_fd;
1810 void __iomem *scc_addr;
1811 int cur;
1812
1813 //if (debug)
1814 // dscc4_rx_dump(dpriv);
1815 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1816
1817 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1818 /*
1819 * This has no effect. Why ?
1820 * ORed with TxSccRes, one sees the CFG ack (for
1821 * the TX part only).
1822 */
1823 scc_writel(RxSccRes, dpriv, dev, CMDR);
1824 dpriv->flags |= RdoSet;
1825
1826 /*
1827 * Let's try and save something in the received data.
1828 * rx_current must be incremented at least once to
1829 * avoid HOLD in the BRDA-to-be-pointed desc.
1830 */
1831 do {
1832 cur = dpriv->rx_current++%RX_RING_SIZE;
1833 rx_fd = dpriv->rx_fd + cur;
1834 if (!(rx_fd->state2 & DataComplete))
1835 break;
1836 if (rx_fd->state2 & FrameAborted) {
1837 hdlc_stats(dev)->rx_over_errors++;
1838 rx_fd->state1 |= Hold;
1839 rx_fd->state2 = 0x00000000;
1840 rx_fd->end = 0xbabeface;
1841 } else
1842 dscc4_rx_skb(dpriv, dev);
1843 } while (1);
1844
1845 if (debug > 0) {
1846 if (dpriv->flags & RdoSet)
1847 printk(KERN_DEBUG
1848 "%s: no RDO in Rx data\n", DRV_NAME);
1849 }
1850#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1851 /*
1852 * FIXME: must the reset be this violent ?
1853 */
1854#warning "FIXME: CH0BRDA"
1855 writel(dpriv->rx_fd_dma +
1856 (dpriv->rx_current%RX_RING_SIZE)*
1857 sizeof(struct RxFD), scc_addr + CH0BRDA);
1858 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1859 if (dscc4_do_action(dev, "RDR") < 0) {
1860 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1861 dev->name, "RDR");
1862 goto rdo_end;
1863 }
1864 writel(MTFi|Idr, scc_addr + CH0CFG);
1865 if (dscc4_do_action(dev, "IDR") < 0) {
1866 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1867 dev->name, "IDR");
1868 goto rdo_end;
1869 }
1870 rdo_end:
1871#endif
1872 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1873 goto try;
1874 }
1875 if (state & Cd) {
1876 printk(KERN_INFO "%s: CD transition\n", dev->name);
1877 if (!(state &= ~Cd)) /* DEBUG */
1878 goto try;
1879 }
1880 if (state & Flex) {
1881 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1882 if (!(state &= ~Flex))
1883 goto try;
1884 }
1885 }
1886}
1887
1888/*
1889 * I had expected the following to work for the first descriptor
1890 * (tx_fd->state = 0xc0000000)
1891 * - Hold=1 (don't try and branch to the next descripto);
1892 * - No=0 (I want an empty data section, i.e. size=0);
1893 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1894 * It failed and locked solid. Thus the introduction of a dummy skb.
1895 * Problem is acknowledged in errata sheet DS5. Joy :o/
1896 */
1897struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1898{
1899 struct sk_buff *skb;
1900
1901 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1902 if (skb) {
1903 int last = dpriv->tx_dirty%TX_RING_SIZE;
1904 struct TxFD *tx_fd = dpriv->tx_fd + last;
1905
1906 skb->len = DUMMY_SKB_SIZE;
1907 memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE);
1908 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1909 tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
1910 DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
1911 dpriv->tx_skbuff[last] = skb;
1912 }
1913 return skb;
1914}
1915
1916static int dscc4_init_ring(struct net_device *dev)
1917{
1918 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1919 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1920 struct TxFD *tx_fd;
1921 struct RxFD *rx_fd;
1922 void *ring;
1923 int i;
1924
1925 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1926 if (!ring)
1927 goto err_out;
1928 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1929
1930 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1931 if (!ring)
1932 goto err_free_dma_rx;
1933 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1934
1935 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1936 dpriv->tx_dirty = 0xffffffff;
1937 i = dpriv->tx_current = 0;
1938 do {
1939 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1940 tx_fd->complete = 0x00000000;
1941 /* FIXME: NULL should be ok - to be tried */
1942 tx_fd->data = dpriv->tx_fd_dma;
1943 (tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
1944 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1945 } while (i < TX_RING_SIZE);
1946
1947 if (dscc4_init_dummy_skb(dpriv) < 0)
1948 goto err_free_dma_tx;
1949
1950 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1951 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1952 do {
1953 /* size set by the host. Multiple of 4 bytes please */
1954 rx_fd->state1 = HiDesc;
1955 rx_fd->state2 = 0x00000000;
1956 rx_fd->end = 0xbabeface;
1957 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1958 // FIXME: return value verifiee mais traitement suspect
1959 if (try_get_rx_skb(dpriv, dev) >= 0)
1960 dpriv->rx_dirty++;
1961 (rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
1962 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1963 } while (i < RX_RING_SIZE);
1964
1965 return 0;
1966
1967err_free_dma_tx:
1968 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1969err_free_dma_rx:
1970 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1971err_out:
1972 return -ENOMEM;
1973}
1974
1975static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1976{
1977 struct dscc4_pci_priv *ppriv;
1978 struct dscc4_dev_priv *root;
1979 void __iomem *ioaddr;
1980 int i;
1981
1982 ppriv = pci_get_drvdata(pdev);
1983 root = ppriv->root;
1984
1985 ioaddr = root->base_addr;
1986
1987 dscc4_pci_reset(pdev, ioaddr);
1988
1989 free_irq(pdev->irq, root);
1990 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1991 ppriv->iqcfg_dma);
1992 for (i = 0; i < dev_per_card; i++) {
1993 struct dscc4_dev_priv *dpriv = root + i;
1994
1995 dscc4_release_ring(dpriv);
1996 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1997 dpriv->iqrx, dpriv->iqrx_dma);
1998 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1999 dpriv->iqtx, dpriv->iqtx_dma);
2000 }
2001
2002 dscc4_free1(pdev);
2003
2004 iounmap(ioaddr);
2005
2006 pci_release_region(pdev, 1);
2007 pci_release_region(pdev, 0);
2008
2009 pci_disable_device(pdev);
2010}
2011
2012static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2013 unsigned short parity)
2014{
2015 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2016
2017 if (encoding != ENCODING_NRZ &&
2018 encoding != ENCODING_NRZI &&
2019 encoding != ENCODING_FM_MARK &&
2020 encoding != ENCODING_FM_SPACE &&
2021 encoding != ENCODING_MANCHESTER)
2022 return -EINVAL;
2023
2024 if (parity != PARITY_NONE &&
2025 parity != PARITY_CRC16_PR0_CCITT &&
2026 parity != PARITY_CRC16_PR1_CCITT &&
2027 parity != PARITY_CRC32_PR0_CCITT &&
2028 parity != PARITY_CRC32_PR1_CCITT)
2029 return -EINVAL;
2030
2031 dpriv->encoding = encoding;
2032 dpriv->parity = parity;
2033 return 0;
2034}
2035
2036#ifndef MODULE
2037static int __init dscc4_setup(char *str)
2038{
2039 int *args[] = { &debug, &quartz, NULL }, **p = args;
2040
2041 while (*p && (get_option(&str, *p) == 2))
2042 p++;
2043 return 1;
2044}
2045
2046__setup("dscc4.setup=", dscc4_setup);
2047#endif
2048
2049static struct pci_device_id dscc4_pci_tbl[] = {
2050 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2051 PCI_ANY_ID, PCI_ANY_ID, },
2052 { 0,}
2053};
2054MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2055
2056static struct pci_driver dscc4_driver = {
2057 .name = DRV_NAME,
2058 .id_table = dscc4_pci_tbl,
2059 .probe = dscc4_init_one,
2060 .remove = __devexit_p(dscc4_remove_one),
2061};
2062
2063static int __init dscc4_init_module(void)
2064{
2065 return pci_module_init(&dscc4_driver);
2066}
2067
2068static void __exit dscc4_cleanup_module(void)
2069{
2070 pci_unregister_driver(&dscc4_driver);
2071}
2072
2073module_init(dscc4_init_module);
2074module_exit(dscc4_cleanup_module);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-09 16:46:59 -0500