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authorSreenivasa Honnur <Sreenivasa.Honnur@neterion.com>2009-10-04 21:53:38 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-06 18:22:52 -0400
commit0f8f7d58eb4840ee8790e914a88b8a773aca9143 (patch)
tree05d2dfcce3a38a6f3ed489200cae504b75ae3671 /drivers/net/vxge
parent657205bdd7b276d95b3a5bac7e856e22c4001136 (diff)
vxge: Removed accessing non-supported registers.
- Removed accessing GENDMA_INT register - This allowed the firmware to perform a generic DMA write to host memory. This feature is not supported by the ASIC, this patch removes access to GENDMA_INT register. Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/vxge')
-rw-r--r--drivers/net/vxge/vxge-config.c2
-rw-r--r--drivers/net/vxge/vxge-reg.h4
2 files changed, 0 insertions, 6 deletions
diff --git a/drivers/net/vxge/vxge-config.c b/drivers/net/vxge/vxge-config.c
index 11cdb381681a..e51fac8d0ad0 100644
--- a/drivers/net/vxge/vxge-config.c
+++ b/drivers/net/vxge/vxge-config.c
@@ -4106,8 +4106,6 @@ __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4106 if (status != VXGE_HW_OK) 4106 if (status != VXGE_HW_OK)
4107 goto exit; 4107 goto exit;
4108 4108
4109 writeq(0, &vp_reg->gendma_int);
4110
4111 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl); 4109 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4112 4110
4113 /* Get MRRS value from device control */ 4111 /* Get MRRS value from device control */
diff --git a/drivers/net/vxge/vxge-reg.h b/drivers/net/vxge/vxge-reg.h
index 9a3b823e08d4..9a0cf8eaa328 100644
--- a/drivers/net/vxge/vxge-reg.h
+++ b/drivers/net/vxge/vxge-reg.h
@@ -4326,10 +4326,6 @@ struct vxge_hw_vpath_reg {
4326/*0x011e0*/ u64 umq_bwr_init_byte; 4326/*0x011e0*/ u64 umq_bwr_init_byte;
4327#define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) 4327#define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
4328/*0x011e8*/ u64 gendma_int; 4328/*0x011e8*/ u64 gendma_int;
4329#define VXGE_HW_GENDMA_INT_IMMED_ENABLE vxge_mBIT(6)
4330#define VXGE_HW_GENDMA_INT_EVENT_ENABLE vxge_mBIT(7)
4331#define VXGE_HW_GENDMA_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
4332#define VXGE_HW_GENDMA_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
4333/*0x011f0*/ u64 umqdmq_ir_init_notify; 4329/*0x011f0*/ u64 umqdmq_ir_init_notify;
4334#define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3) 4330#define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3)
4335/*0x011f8*/ u64 dmq_init_notify; 4331/*0x011f8*/ u64 dmq_init_notify;