vxge: Fixed MSIX interrupt configuration.

- Fixed MSIX interrupt configuration to support non contiguous vpaths in
  functions. Four msi-x vectors are reserved per vpath internal to the chip.
  In all, there are 68 msi-x vectors for the 17 vpaths in the chip. In the
  multi function configurations, non-contiguous vpaths are configured to
  represent a function. For instance vpaths 0 and 8 can be configured to
  represent function zero.

- If pci_enable_msix fails for the requested vectors, try with a lesser number
  vectors by reducing the vpath count.

Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
Signed-off-by: Ramkrishna Vepa <ram.vepa@neterion.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 12 insertions, 23 deletions

diff --git a/drivers/net/vxge/vxge-traffic.c b/drivers/net/vxge/vxge-traffic.c
index c8b3997e9eeb..f83e6aee3f6a 100644
--- a/drivers/net/vxge/vxge-traffic.c
+++ b/drivers/net/vxge/vxge-traffic.c
@@ -231,8 +231,7 @@ void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
 {
 
         __vxge_hw_pio_mem_write32_upper(
-                (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)),
-                        0, 32),
+                (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
                 &channel->common_reg->set_msix_mask_vect[msix_id%4]);
 
         return;
@@ -252,8 +251,7 @@ vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
 {
 
         __vxge_hw_pio_mem_write32_upper(
-                (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)),
-                        0, 32),
+                (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
                 &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
 
         return;
@@ -2220,29 +2218,24 @@ exit:
  * This API will associate a given MSIX vector numbers with the four TIM
  * interrupts and alarm interrupt.
  */
-enum vxge_hw_status
+void
 vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
                        int alarm_msix_id)
 {
         u64 val64;
         struct __vxge_hw_virtualpath *vpath = vp->vpath;
         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
-        u32 first_vp_id = vpath->hldev->first_vp_id;
+        u32 vp_id = vp->vpath->vp_id;
 
         val64 =  VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
-                  (first_vp_id * 4) + tim_msix_id[0]) |
+                  (vp_id * 4) + tim_msix_id[0]) |
                  VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
-                  (first_vp_id * 4) + tim_msix_id[1]) |
-                 VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
-                        (first_vp_id * 4) + tim_msix_id[2]);
-
-                val64 |= VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(
-                        (first_vp_id * 4) + tim_msix_id[3]);
+                  (vp_id * 4) + tim_msix_id[1]);
 
         writeq(val64, &vp_reg->interrupt_cfg0);
 
         writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
-                        (first_vp_id * 4) + alarm_msix_id),
+                        (vpath->hldev->first_vp_id * 4) + alarm_msix_id),
                         &vp_reg->interrupt_cfg2);
 
         if (vpath->hldev->config.intr_mode ==
@@ -2263,7 +2256,7 @@ vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
                                 0, 32), &vp_reg->one_shot_vect3_en);
         }
 
-        return VXGE_HW_OK;
+        return;
 }
 
 /**
@@ -2283,8 +2276,7 @@ vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
 {
         struct __vxge_hw_device *hldev = vp->vpath->hldev;
         __vxge_hw_pio_mem_write32_upper(
-                (u32) vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
-                        (msix_id  / 4)), 0, 32),
+                (u32) vxge_bVALn(vxge_mBIT(msix_id  >> 2), 0, 32),
                 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
 
         return;
@@ -2309,14 +2301,12 @@ vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
         if (hldev->config.intr_mode ==
                         VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
                 __vxge_hw_pio_mem_write32_upper(
-                        (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
-                                (msix_id/4)), 0, 32),
+                        (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
                                 &hldev->common_reg->
                                         clr_msix_one_shot_vec[msix_id%4]);
         } else {
                 __vxge_hw_pio_mem_write32_upper(
-                        (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
-                                (msix_id/4)), 0, 32),
+                        (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
                                 &hldev->common_reg->
                                         clear_msix_mask_vect[msix_id%4]);
         }
@@ -2341,8 +2331,7 @@ vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
 {
         struct __vxge_hw_device *hldev = vp->vpath->hldev;
         __vxge_hw_pio_mem_write32_upper(
-                        (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
-                        (msix_id/4)), 0, 32),
+                        (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
                         &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
 
         return;