diff options
author | françois romieu <romieu@fr.zoreil.com> | 2011-01-19 23:59:33 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-01-20 19:59:33 -0500 |
commit | 2ffa007eaa01cf5fedd6a71f7d43854339a831ee (patch) | |
tree | ba2f8df8dc438962a722062271c1fc8e69988d8d /drivers/net/via-velocity.h | |
parent | a2da570d62fcb9e8816f6920e1ec02c706b289fa (diff) |
via-velocity: fix the WOL bug on 1000M full duplex forced mode.
The VIA velocity card can't be waken up by WOL tool on 1000M full
duplex forced mode. This patch fixes the bug.
Signed-off-by: David Lv <DavidLv@viatech.com.cn>
Acked-by: Francois Romieu <romieu@fr.zoreil.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/via-velocity.h')
-rw-r--r-- | drivers/net/via-velocity.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h index aa2e69b9ff61..d7227539484e 100644 --- a/drivers/net/via-velocity.h +++ b/drivers/net/via-velocity.h | |||
@@ -361,7 +361,7 @@ enum velocity_owner { | |||
361 | #define MAC_REG_CHIPGSR 0x9C | 361 | #define MAC_REG_CHIPGSR 0x9C |
362 | #define MAC_REG_TESTCFG 0x9D | 362 | #define MAC_REG_TESTCFG 0x9D |
363 | #define MAC_REG_DEBUG 0x9E | 363 | #define MAC_REG_DEBUG 0x9E |
364 | #define MAC_REG_CHIPGCR 0x9F | 364 | #define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */ |
365 | #define MAC_REG_WOLCR0_SET 0xA0 | 365 | #define MAC_REG_WOLCR0_SET 0xA0 |
366 | #define MAC_REG_WOLCR1_SET 0xA1 | 366 | #define MAC_REG_WOLCR1_SET 0xA1 |
367 | #define MAC_REG_PWCFG_SET 0xA2 | 367 | #define MAC_REG_PWCFG_SET 0xA2 |
@@ -848,10 +848,10 @@ enum velocity_owner { | |||
848 | * Bits in CHIPGCR register | 848 | * Bits in CHIPGCR register |
849 | */ | 849 | */ |
850 | 850 | ||
851 | #define CHIPGCR_FCGMII 0x80 /* enable GMII mode */ | 851 | #define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */ |
852 | #define CHIPGCR_FCFDX 0x40 | 852 | #define CHIPGCR_FCFDX 0x40 /* force full duplex */ |
853 | #define CHIPGCR_FCRESV 0x20 | 853 | #define CHIPGCR_FCRESV 0x20 |
854 | #define CHIPGCR_FCMODE 0x10 | 854 | #define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */ |
855 | #define CHIPGCR_LPSOPT 0x08 | 855 | #define CHIPGCR_LPSOPT 0x08 |
856 | #define CHIPGCR_TM1US 0x04 | 856 | #define CHIPGCR_TM1US 0x04 |
857 | #define CHIPGCR_TM0US 0x02 | 857 | #define CHIPGCR_TM0US 0x02 |