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authorGrant Likely <grant.likely@secretlab.ca>2009-06-17 09:16:04 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-17 21:46:43 -0400
commitf3a32500ba8f3ec9ee0c12836fcfd315f1256db4 (patch)
treefecc1148c135213d6f82130de46e6196e57a59a8 /drivers/net/ucc_geth.h
parent603a8bbe62e54108055fca46ecdd611c10c6cd0a (diff)
Revert "net/ucc_geth: Add SGMII support for UEC GETH driver"
This reverts commit 047584ce94108012288554a5f84585d792cc7f8f. This patch meshes badly with "net: Rework ucc_geth driver to use of_mdio infrastructure" (0b9da337dca972e7a4144e298ec3adb8f244d4a4). Since most of the patch needs to be reworked, it is clearer to revert the patch and then apply the corrected version Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ucc_geth.h')
-rw-r--r--drivers/net/ucc_geth.h28
1 files changed, 1 insertions, 27 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index deb962bb68ef..dca628a922ba 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved. 2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 * 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com> 4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * 5 *
@@ -193,31 +193,6 @@ struct ucc_geth {
193#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ 193#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
194#define ENET_TBI_MII_TBICON 0x11 /* TBI control */ 194#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
195 195
196/* TBI MDIO register bit fields*/
197#define TBISR_LSTATUS 0x0004
198#define TBICON_CLK_SELECT 0x0020
199#define TBIANA_ASYMMETRIC_PAUSE 0x0100
200#define TBIANA_SYMMETRIC_PAUSE 0x0080
201#define TBIANA_HALF_DUPLEX 0x0040
202#define TBIANA_FULL_DUPLEX 0x0020
203#define TBICR_PHY_RESET 0x8000
204#define TBICR_ANEG_ENABLE 0x1000
205#define TBICR_RESTART_ANEG 0x0200
206#define TBICR_FULL_DUPLEX 0x0100
207#define TBICR_SPEED1_SET 0x0040
208
209#define TBIANA_SETTINGS ( \
210 TBIANA_ASYMMETRIC_PAUSE \
211 | TBIANA_SYMMETRIC_PAUSE \
212 | TBIANA_FULL_DUPLEX \
213 )
214#define TBICR_SETTINGS ( \
215 TBICR_PHY_RESET \
216 | TBICR_ANEG_ENABLE \
217 | TBICR_FULL_DUPLEX \
218 | TBICR_SPEED1_SET \
219 )
220
221/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 196/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
222#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control 197#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
223 Rx */ 198 Rx */
@@ -1213,7 +1188,6 @@ struct ucc_geth_private {
1213 1188
1214 struct ugeth_mii_info *mii_info; 1189 struct ugeth_mii_info *mii_info;
1215 struct phy_device *phydev; 1190 struct phy_device *phydev;
1216 struct phy_device *tbiphy;
1217 phy_interface_t phy_interface; 1191 phy_interface_t phy_interface;
1218 int max_speed; 1192 int max_speed;
1219 uint32_t msg_enable; 1193 uint32_t msg_enable;