diff options
author | Kim Phillips <kim.phillips@freescale.com> | 2007-04-13 02:26:03 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-04-28 11:01:04 -0400 |
commit | 728de4c927a3544b6d3da331b634035d4c75ca17 (patch) | |
tree | 5f05e0b318de9c1d517bd7bbca5964249c7cc885 /drivers/net/ucc_geth.h | |
parent | a999589ccaae16472531e0616f23826ad097aa40 (diff) |
ucc_geth: migrate ucc_geth to phylib
migrate ucc_geth to use the common phylib code.
There are several side effects from doing this:
o deprecate 'interface' property specification present
in some old device tree source files in
favour of a split 'max-speed' and 'interface-type'
description to appropriately match definitions
in include/linux/phy.h. Note that 'interface' property
is still honoured if max-speed or interface-type
are not present (backward compatible).
o compile-time CONFIG_UGETH_HAS_GIGA is eliminated
in favour of probe time speed derivation logic.
o adjust_link streamlined to only operate on maccfg2
and upsmr.r10m, instead of reapplying static initial
values related to the interface-type.
o Addition of UEC MDIO of_platform driver requires
platform code add 'mdio' type to id list
prior to calling of_platform_bus_probe (separate patch).
o ucc_struct_init introduced to reduce ucc_geth_startup
complexity.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/ucc_geth.h')
-rw-r--r-- | drivers/net/ucc_geth.h | 108 |
1 files changed, 8 insertions, 100 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index a66561253593..6e97c20b92aa 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h | |||
@@ -28,6 +28,8 @@ | |||
28 | #include <asm/ucc.h> | 28 | #include <asm/ucc.h> |
29 | #include <asm/ucc_fast.h> | 29 | #include <asm/ucc_fast.h> |
30 | 30 | ||
31 | #include "ucc_geth_mii.h" | ||
32 | |||
31 | #define NUM_TX_QUEUES 8 | 33 | #define NUM_TX_QUEUES 8 |
32 | #define NUM_RX_QUEUES 8 | 34 | #define NUM_RX_QUEUES 8 |
33 | #define NUM_BDS_IN_PREFETCHED_BDS 4 | 35 | #define NUM_BDS_IN_PREFETCHED_BDS 4 |
@@ -36,15 +38,6 @@ | |||
36 | #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 | 38 | #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 |
37 | #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 | 39 | #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 |
38 | 40 | ||
39 | struct ucc_mii_mng { | ||
40 | u32 miimcfg; /* MII management configuration reg */ | ||
41 | u32 miimcom; /* MII management command reg */ | ||
42 | u32 miimadd; /* MII management address reg */ | ||
43 | u32 miimcon; /* MII management control reg */ | ||
44 | u32 miimstat; /* MII management status reg */ | ||
45 | u32 miimind; /* MII management indication reg */ | ||
46 | } __attribute__ ((packed)); | ||
47 | |||
48 | struct ucc_geth { | 41 | struct ucc_geth { |
49 | struct ucc_fast uccf; | 42 | struct ucc_fast uccf; |
50 | 43 | ||
@@ -53,7 +46,7 @@ struct ucc_geth { | |||
53 | u32 ipgifg; /* interframe gap reg. */ | 46 | u32 ipgifg; /* interframe gap reg. */ |
54 | u32 hafdup; /* half-duplex reg. */ | 47 | u32 hafdup; /* half-duplex reg. */ |
55 | u8 res1[0x10]; | 48 | u8 res1[0x10]; |
56 | struct ucc_mii_mng miimng; /* MII management structure */ | 49 | u8 miimng[0x18]; /* MII management structure moved to _mii.h */ |
57 | u32 ifctl; /* interface control reg */ | 50 | u32 ifctl; /* interface control reg */ |
58 | u32 ifstat; /* interface statux reg */ | 51 | u32 ifstat; /* interface statux reg */ |
59 | u32 macstnaddr1; /* mac station address part 1 reg */ | 52 | u32 macstnaddr1; /* mac station address part 1 reg */ |
@@ -381,66 +374,6 @@ struct ucc_geth { | |||
381 | #define UCCS_MPD 0x01 /* Magic Packet | 374 | #define UCCS_MPD 0x01 /* Magic Packet |
382 | Detected */ | 375 | Detected */ |
383 | 376 | ||
384 | /* UCC GETH MIIMCFG (MII Management Configuration Register) */ | ||
385 | #define MIIMCFG_RESET_MANAGEMENT 0x80000000 /* Reset | ||
386 | management */ | ||
387 | #define MIIMCFG_NO_PREAMBLE 0x00000010 /* Preamble | ||
388 | suppress */ | ||
389 | #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) /* clock divide | ||
390 | << shift */ | ||
391 | #define MIIMCFG_CLOCK_DIVIDE_MAX 0xf /* clock divide max val | ||
392 | */ | ||
393 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2 0x00000000 /* divide by 2 */ | ||
394 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 /* divide by 4 */ | ||
395 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 /* divide by 6 */ | ||
396 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 /* divide by 8 */ | ||
397 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 /* divide by 10 | ||
398 | */ | ||
399 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 /* divide by 14 | ||
400 | */ | ||
401 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16 0x00000008 /* divide by 16 | ||
402 | */ | ||
403 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 /* divide by 20 | ||
404 | */ | ||
405 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 /* divide by 28 | ||
406 | */ | ||
407 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32 0x00000009 /* divide by 32 | ||
408 | */ | ||
409 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48 0x0000000a /* divide by 48 | ||
410 | */ | ||
411 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64 0x0000000b /* divide by 64 | ||
412 | */ | ||
413 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80 0x0000000c /* divide by 80 | ||
414 | */ | ||
415 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112 0x0000000d /* divide by | ||
416 | 112 */ | ||
417 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160 0x0000000e /* divide by | ||
418 | 160 */ | ||
419 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224 0x0000000f /* divide by | ||
420 | 224 */ | ||
421 | |||
422 | /* UCC GETH MIIMCOM (MII Management Command Register) */ | ||
423 | #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ | ||
424 | #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ | ||
425 | |||
426 | /* UCC GETH MIIMADD (MII Management Address Register) */ | ||
427 | #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) /* PHY Address | ||
428 | << shift */ | ||
429 | #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) /* PHY Register | ||
430 | << shift */ | ||
431 | |||
432 | /* UCC GETH MIIMCON (MII Management Control Register) */ | ||
433 | #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) /* PHY Control | ||
434 | << shift */ | ||
435 | #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) /* PHY Status | ||
436 | << shift */ | ||
437 | |||
438 | /* UCC GETH MIIMIND (MII Management Indicator Register) */ | ||
439 | #define MIIMIND_NOT_VALID 0x00000004 /* Not valid */ | ||
440 | #define MIIMIND_SCAN 0x00000002 /* Scan in | ||
441 | progress */ | ||
442 | #define MIIMIND_BUSY 0x00000001 | ||
443 | |||
444 | /* UCC GETH IFSTAT (Interface Status Register) */ | 377 | /* UCC GETH IFSTAT (Interface Status Register) */ |
445 | #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive | 378 | #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive |
446 | transmission | 379 | transmission |
@@ -1009,15 +942,6 @@ struct ucc_geth_hardware_statistics { | |||
1009 | register */ | 942 | register */ |
1010 | #define UCC_GETH_MACCFG1_INIT 0 | 943 | #define UCC_GETH_MACCFG1_INIT 0 |
1011 | #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) | 944 | #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) |
1012 | #define UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT \ | ||
1013 | (MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112) | ||
1014 | |||
1015 | /* Ethernet speed */ | ||
1016 | enum enet_speed { | ||
1017 | ENET_SPEED_10BT, /* 10 Base T */ | ||
1018 | ENET_SPEED_100BT, /* 100 Base T */ | ||
1019 | ENET_SPEED_1000BT /* 1000 Base T */ | ||
1020 | }; | ||
1021 | 945 | ||
1022 | /* Ethernet Address Type. */ | 946 | /* Ethernet Address Type. */ |
1023 | enum enet_addr_type { | 947 | enum enet_addr_type { |
@@ -1026,22 +950,6 @@ enum enet_addr_type { | |||
1026 | ENET_ADDR_TYPE_BROADCAST | 950 | ENET_ADDR_TYPE_BROADCAST |
1027 | }; | 951 | }; |
1028 | 952 | ||
1029 | /* TBI / MII Set Register */ | ||
1030 | enum enet_tbi_mii_reg { | ||
1031 | ENET_TBI_MII_CR = 0x00, /* Control (CR ) */ | ||
1032 | ENET_TBI_MII_SR = 0x01, /* Status (SR ) */ | ||
1033 | ENET_TBI_MII_ANA = 0x04, /* AN advertisement (ANA ) */ | ||
1034 | ENET_TBI_MII_ANLPBPA = 0x05, /* AN link partner base page ability | ||
1035 | (ANLPBPA) */ | ||
1036 | ENET_TBI_MII_ANEX = 0x06, /* AN expansion (ANEX ) */ | ||
1037 | ENET_TBI_MII_ANNPT = 0x07, /* AN next page transmit (ANNPT ) */ | ||
1038 | ENET_TBI_MII_ANLPANP = 0x08, /* AN link partner ability next page | ||
1039 | (ANLPANP) */ | ||
1040 | ENET_TBI_MII_EXST = 0x0F, /* Extended status (EXST ) */ | ||
1041 | ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics (JD ) */ | ||
1042 | ENET_TBI_MII_TBICON = 0x11 /* TBI control (TBICON ) */ | ||
1043 | }; | ||
1044 | |||
1045 | /* UCC GETH 82xx Ethernet Address Recognition Location */ | 953 | /* UCC GETH 82xx Ethernet Address Recognition Location */ |
1046 | enum ucc_geth_enet_address_recognition_location { | 954 | enum ucc_geth_enet_address_recognition_location { |
1047 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station | 955 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station |
@@ -1239,8 +1147,7 @@ struct ucc_geth_info { | |||
1239 | u16 pausePeriod; | 1147 | u16 pausePeriod; |
1240 | u16 extensionField; | 1148 | u16 extensionField; |
1241 | u8 phy_address; | 1149 | u8 phy_address; |
1242 | u32 board_flags; | 1150 | u32 mdio_bus; |
1243 | u32 phy_interrupt; | ||
1244 | u8 weightfactor[NUM_TX_QUEUES]; | 1151 | u8 weightfactor[NUM_TX_QUEUES]; |
1245 | u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; | 1152 | u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; |
1246 | u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; | 1153 | u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; |
@@ -1249,7 +1156,6 @@ struct ucc_geth_info { | |||
1249 | u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; | 1156 | u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; |
1250 | u16 bdRingLenTx[NUM_TX_QUEUES]; | 1157 | u16 bdRingLenTx[NUM_TX_QUEUES]; |
1251 | u16 bdRingLenRx[NUM_RX_QUEUES]; | 1158 | u16 bdRingLenRx[NUM_RX_QUEUES]; |
1252 | enum enet_interface enet_interface; | ||
1253 | enum ucc_geth_num_of_station_addresses numStationAddresses; | 1159 | enum ucc_geth_num_of_station_addresses numStationAddresses; |
1254 | enum qe_fltr_largest_external_tbl_lookup_key_size | 1160 | enum qe_fltr_largest_external_tbl_lookup_key_size |
1255 | largestexternallookupkeysize; | 1161 | largestexternallookupkeysize; |
@@ -1326,9 +1232,11 @@ struct ucc_geth_private { | |||
1326 | /* index of the first skb which hasn't been transmitted yet. */ | 1232 | /* index of the first skb which hasn't been transmitted yet. */ |
1327 | u16 skb_dirtytx[NUM_TX_QUEUES]; | 1233 | u16 skb_dirtytx[NUM_TX_QUEUES]; |
1328 | 1234 | ||
1329 | struct work_struct tq; | ||
1330 | struct timer_list phy_info_timer; | ||
1331 | struct ugeth_mii_info *mii_info; | 1235 | struct ugeth_mii_info *mii_info; |
1236 | struct phy_device *phydev; | ||
1237 | phy_interface_t phy_interface; | ||
1238 | int max_speed; | ||
1239 | uint32_t msg_enable; | ||
1332 | int oldspeed; | 1240 | int oldspeed; |
1333 | int oldduplex; | 1241 | int oldduplex; |
1334 | int oldlink; | 1242 | int oldlink; |