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authorMaxim Levitsky <maximlevitsky@gmail.com>2007-03-06 05:41:51 -0500
committerJeff Garzik <jeff@garzik.org>2007-03-06 06:10:02 -0500
commitf67ba792fa10e3a65226d53dccc1232908d86c20 (patch)
treecd57f45066222940c2ed9eadf7d1d3c7400c2fe9 /drivers/net/tulip
parentead9bffb157a22c1f883beb8d20ba8bf7bc92a58 (diff)
dmfe: trivial/spelling fixes
Fix a typo, wrap lines on 80-th column, change KERN_ERR to KERN_INFO for link status message Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Cc: Valerie Henson <val_henson@linux.intel.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/tulip')
-rw-r--r--drivers/net/tulip/dmfe.c124
1 files changed, 88 insertions, 36 deletions
diff --git a/drivers/net/tulip/dmfe.c b/drivers/net/tulip/dmfe.c
index 4dd8a0bae860..fc4a2125b501 100644
--- a/drivers/net/tulip/dmfe.c
+++ b/drivers/net/tulip/dmfe.c
@@ -143,9 +143,16 @@
143#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */ 143#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
144#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */ 144#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
145 145
146#define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value)) 146#define DMFE_DBUG(dbug_now, msg, value) \
147 do { \
148 if (dmfe_debug || (dbug_now)) \
149 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
150 (msg), (long) (value)); \
151 } while (0)
147 152
148#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half"); 153#define SHOW_MEDIA_TYPE(mode) \
154 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
155 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
149 156
150 157
151/* CR9 definition: SROM/MII */ 158/* CR9 definition: SROM/MII */
@@ -163,10 +170,20 @@
163 170
164#define SROM_V41_CODE 0x14 171#define SROM_V41_CODE 0x14
165 172
166#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5); 173#define SROM_CLK_WRITE(data, ioaddr) \
174 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
175 udelay(5); \
176 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
179 udelay(5);
180
181#define __CHK_IO_SIZE(pci_id, dev_rev) \
182 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
183 DM9102A_IO_SIZE: DM9102_IO_SIZE)
167 184
168#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE 185#define CHK_IO_SIZE(pci_dev, dev_rev) \
169#define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev) 186 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
170 187
171/* Sten Check */ 188/* Sten Check */
172#define DEVICE net_device 189#define DEVICE net_device
@@ -329,7 +346,7 @@ static void dmfe_program_DM9802(struct dmfe_board_info *);
329static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * ); 346static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
330static void dmfe_set_phyxcer(struct dmfe_board_info *); 347static void dmfe_set_phyxcer(struct dmfe_board_info *);
331 348
332/* DM910X network baord routine ---------------------------- */ 349/* DM910X network board routine ---------------------------- */
333 350
334/* 351/*
335 * Search DM910X board ,allocate space and register it 352 * Search DM910X board ,allocate space and register it
@@ -356,7 +373,8 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
356 SET_NETDEV_DEV(dev, &pdev->dev); 373 SET_NETDEV_DEV(dev, &pdev->dev);
357 374
358 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { 375 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
359 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n"); 376 printk(KERN_WARNING DRV_NAME
377 ": 32-bit PCI DMA not available.\n");
360 err = -ENODEV; 378 err = -ENODEV;
361 goto err_out_free; 379 goto err_out_free;
362 } 380 }
@@ -400,8 +418,11 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
400 db = netdev_priv(dev); 418 db = netdev_priv(dev);
401 419
402 /* Allocate Tx/Rx descriptor memory */ 420 /* Allocate Tx/Rx descriptor memory */
403 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); 421 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
404 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); 422 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
423
424 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
425 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
405 426
406 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; 427 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
407 db->first_tx_desc_dma = db->desc_pool_dma_ptr; 428 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
@@ -437,7 +458,8 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
437 458
438 /* read 64 word srom data */ 459 /* read 64 word srom data */
439 for (i = 0; i < 64; i++) 460 for (i = 0; i < 64; i++)
440 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); 461 ((u16 *) db->srom)[i] =
462 cpu_to_le16(read_srom_word(db->ioaddr, i));
441 463
442 /* Set Node address */ 464 /* Set Node address */
443 for (i = 0; i < 6; i++) 465 for (i = 0; i < 6; i++)
@@ -506,7 +528,8 @@ static int dmfe_open(struct DEVICE *dev)
506 528
507 DMFE_DBUG(0, "dmfe_open", 0); 529 DMFE_DBUG(0, "dmfe_open", 0);
508 530
509 ret = request_irq(dev->irq, &dmfe_interrupt, IRQF_SHARED, dev->name, dev); 531 ret = request_irq(dev->irq, &dmfe_interrupt,
532 IRQF_SHARED, dev->name, dev);
510 if (ret) 533 if (ret)
511 return ret; 534 return ret;
512 535
@@ -647,7 +670,8 @@ static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
647 /* No Tx resource check, it never happen nromally */ 670 /* No Tx resource check, it never happen nromally */
648 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) { 671 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
649 spin_unlock_irqrestore(&db->lock, flags); 672 spin_unlock_irqrestore(&db->lock, flags);
650 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt); 673 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
674 db->tx_queue_cnt);
651 return 1; 675 return 1;
652 } 676 }
653 677
@@ -719,7 +743,8 @@ static int dmfe_stop(struct DEVICE *dev)
719 743
720#if 0 744#if 0
721 /* show statistic counter */ 745 /* show statistic counter */
722 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n", 746 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
747 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
723 db->tx_fifo_underrun, db->tx_excessive_collision, 748 db->tx_fifo_underrun, db->tx_excessive_collision,
724 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, 749 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
725 db->tx_jabber_timeout, db->reset_count, db->reset_cr8, 750 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
@@ -916,7 +941,9 @@ static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
916 db->rx_avail_cnt--; 941 db->rx_avail_cnt--;
917 db->interval_rx_cnt++; 942 db->interval_rx_cnt++;
918 943
919 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 944 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
945 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
946
920 if ( (rdes0 & 0x300) != 0x300) { 947 if ( (rdes0 & 0x300) != 0x300) {
921 /* A packet without First/Last flag */ 948 /* A packet without First/Last flag */
922 /* reuse this SKB */ 949 /* reuse this SKB */
@@ -1074,7 +1101,8 @@ static void dmfe_timer(unsigned long data)
1074 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) { 1101 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1075 db->cr6_data &= ~0x40000; 1102 db->cr6_data &= ~0x40000;
1076 update_cr6(db->cr6_data, db->ioaddr); 1103 update_cr6(db->cr6_data, db->ioaddr);
1077 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); 1104 phy_write(db->ioaddr,
1105 db->phy_addr, 0, 0x1000, db->chip_id);
1078 db->cr6_data |= 0x40000; 1106 db->cr6_data |= 0x40000;
1079 update_cr6(db->cr6_data, db->ioaddr); 1107 update_cr6(db->cr6_data, db->ioaddr);
1080 db->timer.expires = DMFE_TIMER_WUT + HZ * 2; 1108 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
@@ -1148,7 +1176,8 @@ static void dmfe_timer(unsigned long data)
1148 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ 1176 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1149 /* AUTO or force 1M Homerun/Longrun don't need */ 1177 /* AUTO or force 1M Homerun/Longrun don't need */
1150 if ( !(db->media_mode & 0x38) ) 1178 if ( !(db->media_mode & 0x38) )
1151 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); 1179 phy_write(db->ioaddr, db->phy_addr,
1180 0, 0x1000, db->chip_id);
1152 1181
1153 /* AUTO mode, if INT phyxcer link failed, select EXT device */ 1182 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1154 if (db->media_mode & DMFE_AUTO) { 1183 if (db->media_mode & DMFE_AUTO) {
@@ -1252,7 +1281,8 @@ static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1252 1281
1253 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { 1282 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1254 rxptr->rx_skb_ptr = skb; 1283 rxptr->rx_skb_ptr = skb;
1255 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); 1284 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1285 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1256 wmb(); 1286 wmb();
1257 rxptr->rdes0 = cpu_to_le32(0x80000000); 1287 rxptr->rdes0 = cpu_to_le32(0x80000000);
1258 db->rx_avail_cnt++; 1288 db->rx_avail_cnt++;
@@ -1284,8 +1314,11 @@ static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioadd
1284 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ 1314 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1285 1315
1286 /* rx descriptor start pointer */ 1316 /* rx descriptor start pointer */
1287 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; 1317 db->first_rx_desc = (void *)db->first_tx_desc +
1288 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; 1318 sizeof(struct tx_desc) * TX_DESC_CNT;
1319
1320 db->first_rx_desc_dma = db->first_tx_desc_dma +
1321 sizeof(struct tx_desc) * TX_DESC_CNT;
1289 db->rx_insert_ptr = db->first_rx_desc; 1322 db->rx_insert_ptr = db->first_rx_desc;
1290 db->rx_ready_ptr = db->first_rx_desc; 1323 db->rx_ready_ptr = db->first_rx_desc;
1291 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ 1324 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
@@ -1463,7 +1496,8 @@ static void allocate_rx_buffer(struct dmfe_board_info *db)
1463 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) 1496 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1464 break; 1497 break;
1465 rxptr->rx_skb_ptr = skb; /* FIXME (?) */ 1498 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1466 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); 1499 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1500 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1467 wmb(); 1501 wmb();
1468 rxptr->rdes0 = cpu_to_le32(0x80000000); 1502 rxptr->rdes0 = cpu_to_le32(0x80000000);
1469 rxptr = rxptr->next_rx_desc; 1503 rxptr = rxptr->next_rx_desc;
@@ -1503,7 +1537,8 @@ static u16 read_srom_word(long ioaddr, int offset)
1503 for (i = 16; i > 0; i--) { 1537 for (i = 16; i > 0; i--) {
1504 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); 1538 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1505 udelay(5); 1539 udelay(5);
1506 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); 1540 srom_data = (srom_data << 1) |
1541 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1507 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 1542 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1508 udelay(5); 1543 udelay(5);
1509 } 1544 }
@@ -1530,9 +1565,11 @@ static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1530 1565
1531 if ( (phy_mode & 0x24) == 0x24 ) { 1566 if ( (phy_mode & 0x24) == 0x24 ) {
1532 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */ 1567 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1533 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000; 1568 phy_mode = phy_read(db->ioaddr,
1569 db->phy_addr, 7, db->chip_id) & 0xf000;
1534 else /* DM9102/DM9102A */ 1570 else /* DM9102/DM9102A */
1535 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000; 1571 phy_mode = phy_read(db->ioaddr,
1572 db->phy_addr, 17, db->chip_id) & 0xf000;
1536 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ 1573 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1537 switch (phy_mode) { 1574 switch (phy_mode) {
1538 case 0x1000: db->op_mode = DMFE_10MHF; break; 1575 case 0x1000: db->op_mode = DMFE_10MHF; break;
@@ -1569,8 +1606,11 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1569 1606
1570 /* DM9009 Chip: Phyxcer reg18 bit12=0 */ 1607 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1571 if (db->chip_id == PCI_DM9009_ID) { 1608 if (db->chip_id == PCI_DM9009_ID) {
1572 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000; 1609 phy_reg = phy_read(db->ioaddr,
1573 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id); 1610 db->phy_addr, 18, db->chip_id) & ~0x1000;
1611
1612 phy_write(db->ioaddr,
1613 db->phy_addr, 18, phy_reg, db->chip_id);
1574 } 1614 }
1575 1615
1576 /* Phyxcer capability setting */ 1616 /* Phyxcer capability setting */
@@ -1643,10 +1683,12 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
1643 case DMFE_100MHF: phy_reg = 0x2000; break; 1683 case DMFE_100MHF: phy_reg = 0x2000; break;
1644 case DMFE_100MFD: phy_reg = 0x2100; break; 1684 case DMFE_100MFD: phy_reg = 0x2100; break;
1645 } 1685 }
1646 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); 1686 phy_write(db->ioaddr,
1687 db->phy_addr, 0, phy_reg, db->chip_id);
1647 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) 1688 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1648 mdelay(20); 1689 mdelay(20);
1649 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); 1690 phy_write(db->ioaddr,
1691 db->phy_addr, 0, phy_reg, db->chip_id);
1650 } 1692 }
1651 } 1693 }
1652} 1694}
@@ -1656,7 +1698,8 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
1656 * Write a word to Phy register 1698 * Write a word to Phy register
1657 */ 1699 */
1658 1700
1659static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) 1701static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1702 u16 phy_data, u32 chip_id)
1660{ 1703{
1661 u16 i; 1704 u16 i;
1662 unsigned long ioaddr; 1705 unsigned long ioaddr;
@@ -1682,11 +1725,13 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data
1682 1725
1683 /* Send Phy address */ 1726 /* Send Phy address */
1684 for (i = 0x10; i > 0; i = i >> 1) 1727 for (i = 0x10; i > 0; i = i >> 1)
1685 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1728 phy_write_1bit(ioaddr,
1729 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1686 1730
1687 /* Send register address */ 1731 /* Send register address */
1688 for (i = 0x10; i > 0; i = i >> 1) 1732 for (i = 0x10; i > 0; i = i >> 1)
1689 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0); 1733 phy_write_1bit(ioaddr,
1734 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1690 1735
1691 /* written trasnition */ 1736 /* written trasnition */
1692 phy_write_1bit(ioaddr, PHY_DATA_1); 1737 phy_write_1bit(ioaddr, PHY_DATA_1);
@@ -1694,7 +1739,8 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data
1694 1739
1695 /* Write a word data to PHY controller */ 1740 /* Write a word data to PHY controller */
1696 for ( i = 0x8000; i > 0; i >>= 1) 1741 for ( i = 0x8000; i > 0; i >>= 1)
1697 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1742 phy_write_1bit(ioaddr,
1743 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1698 } 1744 }
1699} 1745}
1700 1746
@@ -1731,11 +1777,13 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1731 1777
1732 /* Send Phy address */ 1778 /* Send Phy address */
1733 for (i = 0x10; i > 0; i = i >> 1) 1779 for (i = 0x10; i > 0; i = i >> 1)
1734 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1780 phy_write_1bit(ioaddr,
1781 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1735 1782
1736 /* Send register address */ 1783 /* Send register address */
1737 for (i = 0x10; i > 0; i = i >> 1) 1784 for (i = 0x10; i > 0; i = i >> 1)
1738 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0); 1785 phy_write_1bit(ioaddr,
1786 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1739 1787
1740 /* Skip transition state */ 1788 /* Skip transition state */
1741 phy_read_1bit(ioaddr); 1789 phy_read_1bit(ioaddr);
@@ -1956,7 +2004,8 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1956 2004
1957 /* Check remote device status match our setting ot not */ 2005 /* Check remote device status match our setting ot not */
1958 if ( phy_reg != (db->HPNA_command & 0x0f00) ) { 2006 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1959 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); 2007 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2008 db->chip_id);
1960 db->HPNA_timer=8; 2009 db->HPNA_timer=8;
1961 } else 2010 } else
1962 db->HPNA_timer=600; /* Match, every 10 minutes, check */ 2011 db->HPNA_timer=600; /* Match, every 10 minutes, check */
@@ -1996,8 +2045,11 @@ module_param(HPNA_tx_cmd, byte, 0);
1996module_param(HPNA_NoiseFloor, byte, 0); 2045module_param(HPNA_NoiseFloor, byte, 0);
1997module_param(SF_mode, byte, 0); 2046module_param(SF_mode, byte, 0);
1998MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)"); 2047MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
1999MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); 2048MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2000MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)"); 2049 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2050
2051MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2052 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2001 2053
2002/* Description: 2054/* Description:
2003 * when user used insmod to add module, system invoked init_module() 2055 * when user used insmod to add module, system invoked init_module()