aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tulip
diff options
context:
space:
mode:
authorAdrian Bunk <bunk@kernel.org>2008-01-28 17:14:12 -0500
committerJeff Garzik <jeff@garzik.org>2008-03-17 07:49:23 -0400
commitfa6557aff47f25e5b6b92c930a9b60a12acd0b58 (patch)
tree64e130eaca955dcc895270a691670c690d394b18 /drivers/net/tulip
parent548c36e983f346621b5cb9ab031e4383e9996576 (diff)
remove the obsolete xircom_tulip_cb driver
The xircom_tulip_cb driver has been replaced the xircom_cb driver, and since it depended on BROKEN_ON_SMP it e.g. was no longer present in many distribution kernels. This patch therefore removes it. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/tulip')
-rw-r--r--drivers/net/tulip/Kconfig15
-rw-r--r--drivers/net/tulip/Makefile1
-rw-r--r--drivers/net/tulip/xircom_tulip_cb.c1726
3 files changed, 1 insertions, 1741 deletions
diff --git a/drivers/net/tulip/Kconfig b/drivers/net/tulip/Kconfig
index 20ac1503021e..d913405bc393 100644
--- a/drivers/net/tulip/Kconfig
+++ b/drivers/net/tulip/Kconfig
@@ -141,7 +141,7 @@ config ULI526X
141 be called uli526x. 141 be called uli526x.
142 142
143config PCMCIA_XIRCOM 143config PCMCIA_XIRCOM
144 tristate "Xircom CardBus support (new driver)" 144 tristate "Xircom CardBus support"
145 depends on CARDBUS 145 depends on CARDBUS
146 ---help--- 146 ---help---
147 This driver is for the Digital "Tulip" Ethernet CardBus adapters. 147 This driver is for the Digital "Tulip" Ethernet CardBus adapters.
@@ -152,17 +152,4 @@ config PCMCIA_XIRCOM
152 To compile this driver as a module, choose M here. The module will 152 To compile this driver as a module, choose M here. The module will
153 be called xircom_cb. If unsure, say N. 153 be called xircom_cb. If unsure, say N.
154 154
155config PCMCIA_XIRTULIP
156 tristate "Xircom Tulip-like CardBus support (old driver)"
157 depends on CARDBUS && BROKEN_ON_SMP
158 select CRC32
159 ---help---
160 This driver is for the Digital "Tulip" Ethernet CardBus adapters.
161 It should work with most DEC 21*4*-based chips/ethercards, as well
162 as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
163 ASIX.
164
165 To compile this driver as a module, choose M here. The module will
166 be called xircom_tulip_cb. If unsure, say N.
167
168endif # NET_TULIP 155endif # NET_TULIP
diff --git a/drivers/net/tulip/Makefile b/drivers/net/tulip/Makefile
index 451090d6fcca..200cbf7c815c 100644
--- a/drivers/net/tulip/Makefile
+++ b/drivers/net/tulip/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the Linux "Tulip" family network device drivers. 2# Makefile for the Linux "Tulip" family network device drivers.
3# 3#
4 4
5obj-$(CONFIG_PCMCIA_XIRTULIP) += xircom_tulip_cb.o
6obj-$(CONFIG_PCMCIA_XIRCOM) += xircom_cb.o 5obj-$(CONFIG_PCMCIA_XIRCOM) += xircom_cb.o
7obj-$(CONFIG_DM9102) += dmfe.o 6obj-$(CONFIG_DM9102) += dmfe.o
8obj-$(CONFIG_WINBOND_840) += winbond-840.o 7obj-$(CONFIG_WINBOND_840) += winbond-840.o
diff --git a/drivers/net/tulip/xircom_tulip_cb.c b/drivers/net/tulip/xircom_tulip_cb.c
deleted file mode 100644
index c3f8e303c6c7..000000000000
--- a/drivers/net/tulip/xircom_tulip_cb.c
+++ /dev/null
@@ -1,1726 +0,0 @@
1/* xircom_tulip_cb.c: A Xircom CBE-100 ethernet driver for Linux. */
2/*
3 Written/copyright 1994-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 The author may be reached as becker@scyld.com, or C/O
9 Scyld Computing Corporation
10 410 Severn Ave., Suite 210
11 Annapolis MD 21403
12
13*/
14
15#define DRV_NAME "xircom_tulip_cb"
16#define DRV_VERSION "0.92"
17#define DRV_RELDATE "June 27, 2006"
18
19/* A few user-configurable values. */
20
21#define xircom_debug debug
22#ifdef XIRCOM_DEBUG
23static int xircom_debug = XIRCOM_DEBUG;
24#else
25static int xircom_debug = 1;
26#endif
27
28/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
29static int max_interrupt_work = 25;
30
31#define MAX_UNITS 4
32/* Used to pass the full-duplex flag, etc. */
33static int full_duplex[MAX_UNITS];
34static int options[MAX_UNITS];
35static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
36
37/* Keep the ring sizes a power of two for efficiency.
38 Making the Tx ring too large decreases the effectiveness of channel
39 bonding and packet priority.
40 There are no ill effects from too-large receive rings. */
41#define TX_RING_SIZE 16
42#define RX_RING_SIZE 32
43
44/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
45#ifdef __alpha__
46static int rx_copybreak = 1518;
47#else
48static int rx_copybreak = 100;
49#endif
50
51/*
52 Set the bus performance register.
53 Typical: Set 16 longword cache alignment, no burst limit.
54 Cache alignment bits 15:14 Burst length 13:8
55 0000 No alignment 0x00000000 unlimited 0800 8 longwords
56 4000 8 longwords 0100 1 longword 1000 16 longwords
57 8000 16 longwords 0200 2 longwords 2000 32 longwords
58 C000 32 longwords 0400 4 longwords
59 Warning: many older 486 systems are broken and require setting 0x00A04800
60 8 longword cache alignment, 8 longword burst.
61 ToDo: Non-Intel setting could be better.
62*/
63
64#if defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
65static int csr0 = 0x01A00000 | 0xE000;
66#elif defined(__powerpc__)
67static int csr0 = 0x01B00000 | 0x8000;
68#elif defined(CONFIG_SPARC)
69static int csr0 = 0x01B00080 | 0x8000;
70#elif defined(__i386__)
71static int csr0 = 0x01A00000 | 0x8000;
72#else
73#warning Processor architecture undefined!
74static int csr0 = 0x00A00000 | 0x4800;
75#endif
76
77/* Operational parameters that usually are not changed. */
78/* Time in jiffies before concluding the transmitter is hung. */
79#define TX_TIMEOUT (4 * HZ)
80#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
81#define PKT_SETUP_SZ 192 /* Size of the setup frame */
82
83/* PCI registers */
84#define PCI_POWERMGMT 0x40
85
86#include <linux/module.h>
87#include <linux/moduleparam.h>
88#include <linux/kernel.h>
89#include <linux/pci.h>
90#include <linux/netdevice.h>
91#include <linux/etherdevice.h>
92#include <linux/delay.h>
93#include <linux/init.h>
94#include <linux/mii.h>
95#include <linux/ethtool.h>
96#include <linux/crc32.h>
97
98#include <asm/io.h>
99#include <asm/processor.h> /* Processor type for cache alignment. */
100#include <asm/uaccess.h>
101
102
103/* These identify the driver base version and may not be removed. */
104static char version[] __devinitdata =
105KERN_INFO DRV_NAME ".c derived from tulip.c:v0.91 4/14/99 becker@scyld.com\n"
106KERN_INFO " unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE "\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("Xircom CBE-100 ethernet driver");
110MODULE_LICENSE("GPL v2");
111MODULE_VERSION(DRV_VERSION);
112
113module_param(debug, int, 0);
114module_param(max_interrupt_work, int, 0);
115module_param(rx_copybreak, int, 0);
116module_param(csr0, int, 0);
117
118module_param_array(options, int, NULL, 0);
119module_param_array(full_duplex, int, NULL, 0);
120
121#define RUN_AT(x) (jiffies + (x))
122
123/*
124 Theory of Operation
125
126I. Board Compatibility
127
128This device driver was forked from the driver for the DECchip "Tulip",
129Digital's single-chip ethernet controllers for PCI. It supports Xircom's
130almost-Tulip-compatible CBE-100 CardBus adapters.
131
132II. Board-specific settings
133
134PCI bus devices are configured by the system at boot time, so no jumpers
135need to be set on the board. The system BIOS preferably should assign the
136PCI INTA signal to an otherwise unused system IRQ line.
137
138III. Driver operation
139
140IIIa. Ring buffers
141
142The Xircom can use either ring buffers or lists of Tx and Rx descriptors.
143This driver uses statically allocated rings of Rx and Tx descriptors, set at
144compile time by RX/TX_RING_SIZE. This version of the driver allocates skbuffs
145for the Rx ring buffers at open() time and passes the skb->data field to the
146Xircom as receive data buffers. When an incoming frame is less than
147RX_COPYBREAK bytes long, a fresh skbuff is allocated and the frame is
148copied to the new skbuff. When the incoming frame is larger, the skbuff is
149passed directly up the protocol stack and replaced by a newly allocated
150skbuff.
151
152The RX_COPYBREAK value is chosen to trade-off the memory wasted by
153using a full-sized skbuff for small frames vs. the copying costs of larger
154frames. For small frames the copying cost is negligible (esp. considering
155that we are pre-loading the cache with immediately useful header
156information). For large frames the copying cost is non-trivial, and the
157larger copy might flush the cache of useful data. A subtle aspect of this
158choice is that the Xircom only receives into longword aligned buffers, thus
159the IP header at offset 14 isn't longword aligned for further processing.
160Copied frames are put into the new skbuff at an offset of "+2", thus copying
161has the beneficial effect of aligning the IP header and preloading the
162cache.
163
164IIIC. Synchronization
165The driver runs as two independent, single-threaded flows of control. One
166is the send-packet routine, which enforces single-threaded use by the
167dev->tbusy flag. The other thread is the interrupt handler, which is single
168threaded by the hardware and other software.
169
170The send packet thread has partial control over the Tx ring and 'dev->tbusy'
171flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
172queue slot is empty, it clears the tbusy flag when finished otherwise it sets
173the 'tp->tx_full' flag.
174
175The interrupt handler has exclusive control over the Rx ring and records stats
176from the Tx ring. (The Tx-done interrupt can't be selectively turned off, so
177we can't avoid the interrupt overhead by having the Tx routine reap the Tx
178stats.) After reaping the stats, it marks the queue entry as empty by setting
179the 'base' to zero. Iff the 'tp->tx_full' flag is set, it clears both the
180tx_full and tbusy flags.
181
182IV. Notes
183
184IVb. References
185
186http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
187http://www.digital.com (search for current 21*4* datasheets and "21X4 SROM")
188http://www.national.com/pf/DP/DP83840A.html
189
190IVc. Errata
191
192*/
193
194/* A full-duplex map for media types. */
195enum MediaIs {
196 MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8,
197 MediaIs100=16};
198static const char media_cap[] =
199{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20 };
200
201/* Offsets to the Command and Status Registers, "CSRs". All accesses
202 must be longword instructions and quadword aligned. */
203enum xircom_offsets {
204 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
205 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
206 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x04, };
207
208/* The bits in the CSR5 status registers, mostly interrupt sources. */
209enum status_bits {
210 LinkChange=0x08000000,
211 NormalIntr=0x10000, NormalIntrMask=0x00014045,
212 AbnormalIntr=0x8000, AbnormalIntrMask=0x0a00a5a2,
213 ReservedIntrMask=0xe0001a18,
214 EarlyRxIntr=0x4000, BusErrorIntr=0x2000,
215 EarlyTxIntr=0x400, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,
216 TxFIFOUnderflow=0x20, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,
217};
218
219enum csr0_control_bits {
220 EnableMWI=0x01000000, EnableMRL=0x00800000,
221 EnableMRM=0x00200000, EqualBusPrio=0x02,
222 SoftwareReset=0x01,
223};
224
225enum csr6_control_bits {
226 ReceiveAllBit=0x40000000, AllMultiBit=0x80, PromiscBit=0x40,
227 HashFilterBit=0x01, FullDuplexBit=0x0200,
228 TxThresh10=0x400000, TxStoreForw=0x200000,
229 TxThreshMask=0xc000, TxThreshShift=14,
230 EnableTx=0x2000, EnableRx=0x02,
231 ReservedZeroMask=0x8d930134, ReservedOneMask=0x320c0000,
232 EnableTxRx=(EnableTx | EnableRx),
233};
234
235
236enum tbl_flag {
237 HAS_MII=1, HAS_ACPI=2,
238};
239static struct xircom_chip_table {
240 char *chip_name;
241 int valid_intrs; /* CSR7 interrupt enable settings */
242 int flags;
243} xircom_tbl[] = {
244 { "Xircom Cardbus Adapter",
245 LinkChange | NormalIntr | AbnormalIntr | BusErrorIntr |
246 RxDied | RxNoBuf | RxIntr | TxFIFOUnderflow | TxNoBuf | TxDied | TxIntr,
247 HAS_MII | HAS_ACPI, },
248 { NULL, },
249};
250/* This matches the table above. */
251enum chips {
252 X3201_3,
253};
254
255
256/* The Xircom Rx and Tx buffer descriptors. */
257struct xircom_rx_desc {
258 s32 status;
259 s32 length;
260 u32 buffer1, buffer2;
261};
262
263struct xircom_tx_desc {
264 s32 status;
265 s32 length;
266 u32 buffer1, buffer2; /* We use only buffer 1. */
267};
268
269enum tx_desc0_status_bits {
270 Tx0DescOwned=0x80000000, Tx0DescError=0x8000, Tx0NoCarrier=0x0800,
271 Tx0LateColl=0x0200, Tx0ManyColl=0x0100, Tx0Underflow=0x02,
272};
273enum tx_desc1_status_bits {
274 Tx1ComplIntr=0x80000000, Tx1LastSeg=0x40000000, Tx1FirstSeg=0x20000000,
275 Tx1SetupPkt=0x08000000, Tx1DisableCRC=0x04000000, Tx1RingWrap=0x02000000,
276 Tx1ChainDesc=0x01000000, Tx1NoPad=0x800000, Tx1HashSetup=0x400000,
277 Tx1WholePkt=(Tx1FirstSeg | Tx1LastSeg),
278};
279enum rx_desc0_status_bits {
280 Rx0DescOwned=0x80000000, Rx0DescError=0x8000, Rx0NoSpace=0x4000,
281 Rx0Runt=0x0800, Rx0McastPkt=0x0400, Rx0FirstSeg=0x0200, Rx0LastSeg=0x0100,
282 Rx0HugeFrame=0x80, Rx0CRCError=0x02,
283 Rx0WholePkt=(Rx0FirstSeg | Rx0LastSeg),
284};
285enum rx_desc1_status_bits {
286 Rx1RingWrap=0x02000000, Rx1ChainDesc=0x01000000,
287};
288
289struct xircom_private {
290 struct xircom_rx_desc rx_ring[RX_RING_SIZE];
291 struct xircom_tx_desc tx_ring[TX_RING_SIZE];
292 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
293 struct sk_buff* tx_skbuff[TX_RING_SIZE];
294
295 /* The X3201-3 requires 4-byte aligned tx bufs */
296 struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE];
297
298 /* The addresses of receive-in-place skbuffs. */
299 struct sk_buff* rx_skbuff[RX_RING_SIZE];
300 u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)]; /* Pseudo-Tx frame to init address table. */
301 int chip_id;
302 struct net_device_stats stats;
303 unsigned int cur_rx, cur_tx; /* The next free ring entry */
304 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
305 unsigned int tx_full:1; /* The Tx queue is full. */
306 unsigned int speed100:1;
307 unsigned int full_duplex:1; /* Full-duplex operation requested. */
308 unsigned int autoneg:1;
309 unsigned int default_port:4; /* Last dev->if_port value. */
310 unsigned int open:1;
311 unsigned int csr0; /* CSR0 setting. */
312 unsigned int csr6; /* Current CSR6 control settings. */
313 u16 to_advertise; /* NWay capabilities advertised. */
314 u16 advertising[4];
315 signed char phys[4], mii_cnt; /* MII device addresses. */
316 int saved_if_port;
317 struct pci_dev *pdev;
318 spinlock_t lock;
319};
320
321static int mdio_read(struct net_device *dev, int phy_id, int location);
322static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
323static void xircom_up(struct net_device *dev);
324static void xircom_down(struct net_device *dev);
325static int xircom_open(struct net_device *dev);
326static void xircom_tx_timeout(struct net_device *dev);
327static void xircom_init_ring(struct net_device *dev);
328static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev);
329static int xircom_rx(struct net_device *dev);
330static void xircom_media_change(struct net_device *dev);
331static irqreturn_t xircom_interrupt(int irq, void *dev_instance);
332static int xircom_close(struct net_device *dev);
333static struct net_device_stats *xircom_get_stats(struct net_device *dev);
334static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
335static void set_rx_mode(struct net_device *dev);
336static void check_duplex(struct net_device *dev);
337static const struct ethtool_ops ops;
338
339
340/* The Xircom cards are picky about when certain bits in CSR6 can be
341 manipulated. Keith Owens <kaos@ocs.com.au>. */
342static void outl_CSR6(u32 newcsr6, long ioaddr)
343{
344 const int strict_bits =
345 TxThresh10 | TxStoreForw | TxThreshMask | EnableTxRx | FullDuplexBit;
346 int csr5, csr5_22_20, csr5_19_17, currcsr6, attempts = 200;
347 unsigned long flags;
348 save_flags(flags);
349 cli();
350 /* mask out the reserved bits that always read 0 on the Xircom cards */
351 newcsr6 &= ~ReservedZeroMask;
352 /* or in the reserved bits that always read 1 */
353 newcsr6 |= ReservedOneMask;
354 currcsr6 = inl(ioaddr + CSR6);
355 if (((newcsr6 & strict_bits) == (currcsr6 & strict_bits)) ||
356 ((currcsr6 & ~EnableTxRx) == 0)) {
357 outl(newcsr6, ioaddr + CSR6); /* safe */
358 restore_flags(flags);
359 return;
360 }
361 /* make sure the transmitter and receiver are stopped first */
362 currcsr6 &= ~EnableTxRx;
363 while (1) {
364 csr5 = inl(ioaddr + CSR5);
365 if (csr5 == 0xffffffff)
366 break; /* cannot read csr5, card removed? */
367 csr5_22_20 = csr5 & 0x700000;
368 csr5_19_17 = csr5 & 0x0e0000;
369 if ((csr5_22_20 == 0 || csr5_22_20 == 0x600000) &&
370 (csr5_19_17 == 0 || csr5_19_17 == 0x80000 || csr5_19_17 == 0xc0000))
371 break; /* both are stopped or suspended */
372 if (!--attempts) {
373 printk(KERN_INFO DRV_NAME ": outl_CSR6 too many attempts,"
374 "csr5=0x%08x\n", csr5);
375 outl(newcsr6, ioaddr + CSR6); /* unsafe but do it anyway */
376 restore_flags(flags);
377 return;
378 }
379 outl(currcsr6, ioaddr + CSR6);
380 udelay(1);
381 }
382 /* now it is safe to change csr6 */
383 outl(newcsr6, ioaddr + CSR6);
384 restore_flags(flags);
385}
386
387
388static void __devinit read_mac_address(struct net_device *dev)
389{
390 long ioaddr = dev->base_addr;
391 int i, j;
392 unsigned char tuple, link, data_id, data_count;
393
394 /* Xircom has its address stored in the CIS;
395 * we access it through the boot rom interface for now
396 * this might not work, as the CIS is not parsed but I
397 * (danilo) use the offset I found on my card's CIS !!!
398 *
399 * Doug Ledford: I changed this routine around so that it
400 * walks the CIS memory space, parsing the config items, and
401 * finds the proper lan_node_id tuple and uses the data
402 * stored there.
403 */
404 outl(1 << 12, ioaddr + CSR9); /* enable boot rom access */
405 for (i = 0x100; i < 0x1f7; i += link+2) {
406 outl(i, ioaddr + CSR10);
407 tuple = inl(ioaddr + CSR9) & 0xff;
408 outl(i + 1, ioaddr + CSR10);
409 link = inl(ioaddr + CSR9) & 0xff;
410 outl(i + 2, ioaddr + CSR10);
411 data_id = inl(ioaddr + CSR9) & 0xff;
412 outl(i + 3, ioaddr + CSR10);
413 data_count = inl(ioaddr + CSR9) & 0xff;
414 if ( (tuple == 0x22) &&
415 (data_id == 0x04) && (data_count == 0x06) ) {
416 /*
417 * This is it. We have the data we want.
418 */
419 for (j = 0; j < 6; j++) {
420 outl(i + j + 4, ioaddr + CSR10);
421 dev->dev_addr[j] = inl(ioaddr + CSR9) & 0xff;
422 }
423 break;
424 } else if (link == 0) {
425 break;
426 }
427 }
428}
429
430
431/*
432 * locate the MII interfaces and initialize them.
433 * we disable full-duplex modes here,
434 * because we don't know how to handle them.
435 */
436static void find_mii_transceivers(struct net_device *dev)
437{
438 struct xircom_private *tp = netdev_priv(dev);
439 int phy, phy_idx;
440
441 if (media_cap[tp->default_port] & MediaIsMII) {
442 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
443 tp->to_advertise = media2advert[tp->default_port - 9];
444 } else
445 tp->to_advertise =
446 /*ADVERTISE_100BASE4 | ADVERTISE_100FULL |*/ ADVERTISE_100HALF |
447 /*ADVERTISE_10FULL |*/ ADVERTISE_10HALF | ADVERTISE_CSMA;
448
449 /* Find the connected MII xcvrs.
450 Doing this in open() would allow detecting external xcvrs later,
451 but takes much time. */
452 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
453 int mii_status = mdio_read(dev, phy, MII_BMSR);
454 if ((mii_status & (BMSR_100BASE4 | BMSR_100HALF | BMSR_10HALF)) == BMSR_100BASE4 ||
455 ((mii_status & BMSR_100BASE4) == 0 &&
456 (mii_status & (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | BMSR_10HALF)) != 0)) {
457 int mii_reg0 = mdio_read(dev, phy, MII_BMCR);
458 int mii_advert = mdio_read(dev, phy, MII_ADVERTISE);
459 int reg4 = ((mii_status >> 6) & tp->to_advertise) | ADVERTISE_CSMA;
460 tp->phys[phy_idx] = phy;
461 tp->advertising[phy_idx++] = reg4;
462 printk(KERN_INFO "%s: MII transceiver #%d "
463 "config %4.4x status %4.4x advertising %4.4x.\n",
464 dev->name, phy, mii_reg0, mii_status, mii_advert);
465 }
466 }
467 tp->mii_cnt = phy_idx;
468 if (phy_idx == 0) {
469 printk(KERN_INFO "%s: ***WARNING***: No MII transceiver found!\n",
470 dev->name);
471 tp->phys[0] = 0;
472 }
473}
474
475
476/*
477 * To quote Arjan van de Ven:
478 * transceiver_voodoo() enables the external UTP plug thingy.
479 * it's called voodoo as I stole this code and cannot cross-reference
480 * it with the specification.
481 * Actually it seems to go like this:
482 * - GPIO2 enables the MII itself so we can talk to it. The MII gets reset
483 * so any prior MII settings are lost.
484 * - GPIO0 enables the TP port so the MII can talk to the network.
485 * - a software reset will reset both GPIO pins.
486 * I also moved the software reset here, because doing it in xircom_up()
487 * required enabling the GPIO pins each time, which reset the MII each time.
488 * Thus we couldn't control the MII -- which sucks because we don't know
489 * how to handle full-duplex modes so we *must* disable them.
490 */
491static void transceiver_voodoo(struct net_device *dev)
492{
493 struct xircom_private *tp = netdev_priv(dev);
494 long ioaddr = dev->base_addr;
495
496 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
497 outl(SoftwareReset, ioaddr + CSR0);
498 udelay(2);
499
500 /* Deassert reset. */
501 outl(tp->csr0, ioaddr + CSR0);
502
503 /* Reset the xcvr interface and turn on heartbeat. */
504 outl(0x0008, ioaddr + CSR15);
505 udelay(5); /* The delays are Xircom-recommended to give the
506 * chipset time to reset the actual hardware
507 * on the PCMCIA card
508 */
509 outl(0xa8050000, ioaddr + CSR15);
510 udelay(5);
511 outl(0xa00f0000, ioaddr + CSR15);
512 udelay(5);
513
514 outl_CSR6(0, ioaddr);
515 //outl_CSR6(FullDuplexBit, ioaddr);
516}
517
518
519static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
520{
521 struct net_device *dev;
522 struct xircom_private *tp;
523 static int board_idx = -1;
524 int chip_idx = id->driver_data;
525 long ioaddr;
526 int i;
527
528/* when built into the kernel, we only print version if device is found */
529#ifndef MODULE
530 static int printed_version;
531 if (!printed_version++)
532 printk(version);
533#endif
534
535 //printk(KERN_INFO "xircom_init_one(%s)\n", pci_name(pdev));
536
537 board_idx++;
538
539 if (pci_enable_device(pdev))
540 return -ENODEV;
541
542 pci_set_master(pdev);
543
544 ioaddr = pci_resource_start(pdev, 0);
545 dev = alloc_etherdev(sizeof(*tp));
546 if (!dev) {
547 printk (KERN_ERR DRV_NAME "%d: cannot alloc etherdev, aborting\n", board_idx);
548 return -ENOMEM;
549 }
550 SET_NETDEV_DEV(dev, &pdev->dev);
551
552 dev->base_addr = ioaddr;
553 dev->irq = pdev->irq;
554
555 if (pci_request_regions(pdev, dev->name)) {
556 printk (KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", board_idx);
557 goto err_out_free_netdev;
558 }
559
560 /* Bring the chip out of sleep mode.
561 Caution: Snooze mode does not work with some boards! */
562 if (xircom_tbl[chip_idx].flags & HAS_ACPI)
563 pci_write_config_dword(pdev, PCI_POWERMGMT, 0);
564
565 /* Stop the chip's Tx and Rx processes. */
566 outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr);
567 /* Clear the missed-packet counter. */
568 (volatile int)inl(ioaddr + CSR8);
569
570 tp = netdev_priv(dev);
571
572 spin_lock_init(&tp->lock);
573 tp->pdev = pdev;
574 tp->chip_id = chip_idx;
575 /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles. */
576 /* XXX: is this necessary for Xircom? */
577 tp->csr0 = csr0 & ~EnableMWI;
578
579 pci_set_drvdata(pdev, dev);
580
581 /* The lower four bits are the media type. */
582 if (board_idx >= 0 && board_idx < MAX_UNITS) {
583 tp->default_port = options[board_idx] & 15;
584 if ((options[board_idx] & 0x90) || full_duplex[board_idx] > 0)
585 tp->full_duplex = 1;
586 if (mtu[board_idx] > 0)
587 dev->mtu = mtu[board_idx];
588 }
589 if (dev->mem_start)
590 tp->default_port = dev->mem_start;
591 if (tp->default_port) {
592 if (media_cap[tp->default_port] & MediaAlwaysFD)
593 tp->full_duplex = 1;
594 }
595 if (tp->full_duplex)
596 tp->autoneg = 0;
597 else
598 tp->autoneg = 1;
599 tp->speed100 = 1;
600
601 /* The Xircom-specific entries in the device structure. */
602 dev->open = &xircom_open;
603 dev->hard_start_xmit = &xircom_start_xmit;
604 dev->stop = &xircom_close;
605 dev->get_stats = &xircom_get_stats;
606 dev->do_ioctl = &xircom_ioctl;
607#ifdef HAVE_MULTICAST
608 dev->set_multicast_list = &set_rx_mode;
609#endif
610 dev->tx_timeout = xircom_tx_timeout;
611 dev->watchdog_timeo = TX_TIMEOUT;
612 SET_ETHTOOL_OPS(dev, &ops);
613
614 transceiver_voodoo(dev);
615
616 read_mac_address(dev);
617
618 if (register_netdev(dev))
619 goto err_out_cleardev;
620
621 printk(KERN_INFO "%s: %s rev %d at %#3lx,",
622 dev->name, xircom_tbl[chip_idx].chip_name, pdev->revision, ioaddr);
623 for (i = 0; i < 6; i++)
624 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
625 printk(", IRQ %d.\n", dev->irq);
626
627 if (xircom_tbl[chip_idx].flags & HAS_MII) {
628 find_mii_transceivers(dev);
629 check_duplex(dev);
630 }
631
632 return 0;
633
634err_out_cleardev:
635 pci_set_drvdata(pdev, NULL);
636 pci_release_regions(pdev);
637err_out_free_netdev:
638 free_netdev(dev);
639 return -ENODEV;
640}
641
642
643/* MII transceiver control section.
644 Read and write the MII registers using software-generated serial
645 MDIO protocol. See the MII specifications or DP83840A data sheet
646 for details. */
647
648/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
649 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
650 "overclocking" issues or future 66Mhz PCI. */
651#define mdio_delay() inl(mdio_addr)
652
653/* Read and write the MII registers using software-generated serial
654 MDIO protocol. It is just different enough from the EEPROM protocol
655 to not share code. The maxium data clock rate is 2.5 Mhz. */
656#define MDIO_SHIFT_CLK 0x10000
657#define MDIO_DATA_WRITE0 0x00000
658#define MDIO_DATA_WRITE1 0x20000
659#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
660#define MDIO_ENB_IN 0x40000
661#define MDIO_DATA_READ 0x80000
662
663static int mdio_read(struct net_device *dev, int phy_id, int location)
664{
665 int i;
666 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
667 int retval = 0;
668 long ioaddr = dev->base_addr;
669 long mdio_addr = ioaddr + CSR9;
670
671 /* Establish sync by sending at least 32 logic ones. */
672 for (i = 32; i >= 0; i--) {
673 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
674 mdio_delay();
675 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
676 mdio_delay();
677 }
678 /* Shift the read command bits out. */
679 for (i = 15; i >= 0; i--) {
680 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
681
682 outl(MDIO_ENB | dataval, mdio_addr);
683 mdio_delay();
684 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
685 mdio_delay();
686 }
687 /* Read the two transition, 16 data, and wire-idle bits. */
688 for (i = 19; i > 0; i--) {
689 outl(MDIO_ENB_IN, mdio_addr);
690 mdio_delay();
691 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
692 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
693 mdio_delay();
694 }
695 return (retval>>1) & 0xffff;
696}
697
698
699static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
700{
701 int i;
702 int cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
703 long ioaddr = dev->base_addr;
704 long mdio_addr = ioaddr + CSR9;
705
706 /* Establish sync by sending 32 logic ones. */
707 for (i = 32; i >= 0; i--) {
708 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
709 mdio_delay();
710 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
711 mdio_delay();
712 }
713 /* Shift the command bits out. */
714 for (i = 31; i >= 0; i--) {
715 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
716 outl(MDIO_ENB | dataval, mdio_addr);
717 mdio_delay();
718 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
719 mdio_delay();
720 }
721 /* Clear out extra bits. */
722 for (i = 2; i > 0; i--) {
723 outl(MDIO_ENB_IN, mdio_addr);
724 mdio_delay();
725 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
726 mdio_delay();
727 }
728 return;
729}
730
731
732static void
733xircom_up(struct net_device *dev)
734{
735 struct xircom_private *tp = netdev_priv(dev);
736 long ioaddr = dev->base_addr;
737 int i;
738
739 xircom_init_ring(dev);
740 /* Clear the tx ring */
741 for (i = 0; i < TX_RING_SIZE; i++) {
742 tp->tx_skbuff[i] = NULL;
743 tp->tx_ring[i].status = 0;
744 }
745
746 if (xircom_debug > 1)
747 printk(KERN_DEBUG "%s: xircom_up() irq %d.\n", dev->name, dev->irq);
748
749 outl(virt_to_bus(tp->rx_ring), ioaddr + CSR3);
750 outl(virt_to_bus(tp->tx_ring), ioaddr + CSR4);
751
752 tp->saved_if_port = dev->if_port;
753 if (dev->if_port == 0)
754 dev->if_port = tp->default_port;
755
756 tp->csr6 = TxThresh10 /*| FullDuplexBit*/; /* XXX: why 10 and not 100? */
757
758 set_rx_mode(dev);
759
760 /* Start the chip's Tx to process setup frame. */
761 outl_CSR6(tp->csr6, ioaddr);
762 outl_CSR6(tp->csr6 | EnableTx, ioaddr);
763
764 /* Acknowledge all outstanding interrupts sources */
765 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
766 /* Enable interrupts by setting the interrupt mask. */
767 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
768 /* Enable Rx */
769 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
770 /* Rx poll demand */
771 outl(0, ioaddr + CSR2);
772
773 /* Tell the net layer we're ready */
774 netif_start_queue (dev);
775
776 /* Check current media state */
777 xircom_media_change(dev);
778
779 if (xircom_debug > 2) {
780 printk(KERN_DEBUG "%s: Done xircom_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
781 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5),
782 inl(ioaddr + CSR6));
783 }
784}
785
786
787static int
788xircom_open(struct net_device *dev)
789{
790 struct xircom_private *tp = netdev_priv(dev);
791
792 if (request_irq(dev->irq, &xircom_interrupt, IRQF_SHARED, dev->name, dev))
793 return -EAGAIN;
794
795 xircom_up(dev);
796 tp->open = 1;
797
798 return 0;
799}
800
801
802static void xircom_tx_timeout(struct net_device *dev)
803{
804 struct xircom_private *tp = netdev_priv(dev);
805 long ioaddr = dev->base_addr;
806
807 if (media_cap[dev->if_port] & MediaIsMII) {
808 /* Do nothing -- the media monitor should handle this. */
809 if (xircom_debug > 1)
810 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
811 dev->name);
812 }
813
814#if defined(way_too_many_messages)
815 if (xircom_debug > 3) {
816 int i;
817 for (i = 0; i < RX_RING_SIZE; i++) {
818 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
819 int j;
820 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
821 "%2.2x %2.2x %2.2x.\n",
822 i, (unsigned int)tp->rx_ring[i].status,
823 (unsigned int)tp->rx_ring[i].length,
824 (unsigned int)tp->rx_ring[i].buffer1,
825 (unsigned int)tp->rx_ring[i].buffer2,
826 buf[0], buf[1], buf[2]);
827 for (j = 0; buf[j] != 0xee && j < 1600; j++)
828 if (j < 100) printk(" %2.2x", buf[j]);
829 printk(" j=%d.\n", j);
830 }
831 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
832 for (i = 0; i < RX_RING_SIZE; i++)
833 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
834 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
835 for (i = 0; i < TX_RING_SIZE; i++)
836 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
837 printk("\n");
838 }
839#endif
840
841 /* Stop and restart the chip's Tx/Rx processes . */
842 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
843 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
844 /* Trigger an immediate transmit demand. */
845 outl(0, ioaddr + CSR1);
846
847 dev->trans_start = jiffies;
848 netif_wake_queue (dev);
849 tp->stats.tx_errors++;
850}
851
852
853/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
854static void xircom_init_ring(struct net_device *dev)
855{
856 struct xircom_private *tp = netdev_priv(dev);
857 int i;
858
859 tp->tx_full = 0;
860 tp->cur_rx = tp->cur_tx = 0;
861 tp->dirty_rx = tp->dirty_tx = 0;
862
863 for (i = 0; i < RX_RING_SIZE; i++) {
864 tp->rx_ring[i].status = 0;
865 tp->rx_ring[i].length = PKT_BUF_SZ;
866 tp->rx_ring[i].buffer2 = virt_to_bus(&tp->rx_ring[i+1]);
867 tp->rx_skbuff[i] = NULL;
868 }
869 /* Mark the last entry as wrapping the ring. */
870 tp->rx_ring[i-1].length = PKT_BUF_SZ | Rx1RingWrap;
871 tp->rx_ring[i-1].buffer2 = virt_to_bus(&tp->rx_ring[0]);
872
873 for (i = 0; i < RX_RING_SIZE; i++) {
874 /* Note the receive buffer must be longword aligned.
875 dev_alloc_skb() provides 16 byte alignment. But do *not*
876 use skb_reserve() to align the IP header! */
877 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
878 tp->rx_skbuff[i] = skb;
879 if (skb == NULL)
880 break;
881 skb->dev = dev; /* Mark as being used by this device. */
882 tp->rx_ring[i].status = Rx0DescOwned; /* Owned by Xircom chip */
883 tp->rx_ring[i].buffer1 = virt_to_bus(skb->data);
884 }
885 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
886
887 /* The Tx buffer descriptor is filled in as needed, but we
888 do need to clear the ownership bit. */
889 for (i = 0; i < TX_RING_SIZE; i++) {
890 tp->tx_skbuff[i] = NULL;
891 tp->tx_ring[i].status = 0;
892 tp->tx_ring[i].buffer2 = virt_to_bus(&tp->tx_ring[i+1]);
893 if (tp->chip_id == X3201_3)
894 tp->tx_aligned_skbuff[i] = dev_alloc_skb(PKT_BUF_SZ);
895 }
896 tp->tx_ring[i-1].buffer2 = virt_to_bus(&tp->tx_ring[0]);
897}
898
899
900static int
901xircom_start_xmit(struct sk_buff *skb, struct net_device *dev)
902{
903 struct xircom_private *tp = netdev_priv(dev);
904 int entry;
905 u32 flag;
906
907 /* Caution: the write order is important here, set the base address
908 with the "ownership" bits last. */
909
910 /* Calculate the next Tx descriptor entry. */
911 entry = tp->cur_tx % TX_RING_SIZE;
912
913 tp->tx_skbuff[entry] = skb;
914 if (tp->chip_id == X3201_3) {
915 skb_copy_from_linear_data(skb,
916 tp->tx_aligned_skbuff[entry]->data,
917 skb->len);
918 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->tx_aligned_skbuff[entry]->data);
919 } else
920 tp->tx_ring[entry].buffer1 = virt_to_bus(skb->data);
921
922 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
923 flag = Tx1WholePkt; /* No interrupt */
924 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
925 flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */
926 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
927 flag = Tx1WholePkt; /* No Tx-done intr. */
928 } else {
929 /* Leave room for set_rx_mode() to fill entries. */
930 flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */
931 tp->tx_full = 1;
932 }
933 if (entry == TX_RING_SIZE - 1)
934 flag |= Tx1WholePkt | Tx1ComplIntr | Tx1RingWrap;
935
936 tp->tx_ring[entry].length = skb->len | flag;
937 tp->tx_ring[entry].status = Tx0DescOwned; /* Pass ownership to the chip. */
938 tp->cur_tx++;
939 if (tp->tx_full)
940 netif_stop_queue (dev);
941 else
942 netif_wake_queue (dev);
943
944 /* Trigger an immediate transmit demand. */
945 outl(0, dev->base_addr + CSR1);
946
947 dev->trans_start = jiffies;
948
949 return 0;
950}
951
952
953static void xircom_media_change(struct net_device *dev)
954{
955 struct xircom_private *tp = netdev_priv(dev);
956 long ioaddr = dev->base_addr;
957 u16 reg0, reg1, reg4, reg5;
958 u32 csr6 = inl(ioaddr + CSR6), newcsr6;
959
960 /* reset status first */
961 mdio_read(dev, tp->phys[0], MII_BMCR);
962 mdio_read(dev, tp->phys[0], MII_BMSR);
963
964 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
965 reg1 = mdio_read(dev, tp->phys[0], MII_BMSR);
966
967 if (reg1 & BMSR_LSTATUS) {
968 /* link is up */
969 if (reg0 & BMCR_ANENABLE) {
970 /* autonegotiation is enabled */
971 reg4 = mdio_read(dev, tp->phys[0], MII_ADVERTISE);
972 reg5 = mdio_read(dev, tp->phys[0], MII_LPA);
973 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
974 tp->speed100 = 1;
975 tp->full_duplex = 1;
976 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
977 tp->speed100 = 1;
978 tp->full_duplex = 0;
979 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
980 tp->speed100 = 0;
981 tp->full_duplex = 1;
982 } else {
983 tp->speed100 = 0;
984 tp->full_duplex = 0;
985 }
986 } else {
987 /* autonegotiation is disabled */
988 if (reg0 & BMCR_SPEED100)
989 tp->speed100 = 1;
990 else
991 tp->speed100 = 0;
992 if (reg0 & BMCR_FULLDPLX)
993 tp->full_duplex = 1;
994 else
995 tp->full_duplex = 0;
996 }
997 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
998 dev->name,
999 tp->speed100 ? "100" : "10",
1000 tp->full_duplex ? "full" : "half");
1001 netif_carrier_on(dev);
1002 newcsr6 = csr6 & ~FullDuplexBit;
1003 if (tp->full_duplex)
1004 newcsr6 |= FullDuplexBit;
1005 if (newcsr6 != csr6)
1006 outl_CSR6(newcsr6, ioaddr + CSR6);
1007 } else {
1008 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1009 netif_carrier_off(dev);
1010 }
1011}
1012
1013
1014static void check_duplex(struct net_device *dev)
1015{
1016 struct xircom_private *tp = netdev_priv(dev);
1017 u16 reg0;
1018
1019 mdio_write(dev, tp->phys[0], MII_BMCR, BMCR_RESET);
1020 udelay(500);
1021 while (mdio_read(dev, tp->phys[0], MII_BMCR) & BMCR_RESET);
1022
1023 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1024 mdio_write(dev, tp->phys[0], MII_ADVERTISE, tp->advertising[0]);
1025
1026 if (tp->autoneg) {
1027 reg0 &= ~(BMCR_SPEED100 | BMCR_FULLDPLX);
1028 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1029 } else {
1030 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1031 if (tp->speed100)
1032 reg0 |= BMCR_SPEED100;
1033 if (tp->full_duplex)
1034 reg0 |= BMCR_FULLDPLX;
1035 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1036 dev->name,
1037 tp->speed100 ? "100" : "10",
1038 tp->full_duplex ? "full" : "half");
1039 }
1040 mdio_write(dev, tp->phys[0], MII_BMCR, reg0);
1041}
1042
1043
1044/* The interrupt handler does all of the Rx thread work and cleans up
1045 after the Tx thread. */
1046static irqreturn_t xircom_interrupt(int irq, void *dev_instance)
1047{
1048 struct net_device *dev = dev_instance;
1049 struct xircom_private *tp = netdev_priv(dev);
1050 long ioaddr = dev->base_addr;
1051 int csr5, work_budget = max_interrupt_work;
1052 int handled = 0;
1053
1054 spin_lock (&tp->lock);
1055
1056 do {
1057 csr5 = inl(ioaddr + CSR5);
1058 /* Acknowledge all of the current interrupt sources ASAP. */
1059 outl(csr5 & 0x0001ffff, ioaddr + CSR5);
1060
1061 if (xircom_debug > 4)
1062 printk(KERN_DEBUG "%s: interrupt csr5=%#8.8x new csr5=%#8.8x.\n",
1063 dev->name, csr5, inl(dev->base_addr + CSR5));
1064
1065 if (csr5 == 0xffffffff)
1066 break; /* all bits set, assume PCMCIA card removed */
1067
1068 if ((csr5 & (NormalIntr|AbnormalIntr)) == 0)
1069 break;
1070
1071 handled = 1;
1072
1073 if (csr5 & (RxIntr | RxNoBuf))
1074 work_budget -= xircom_rx(dev);
1075
1076 if (csr5 & (TxNoBuf | TxDied | TxIntr)) {
1077 unsigned int dirty_tx;
1078
1079 for (dirty_tx = tp->dirty_tx; tp->cur_tx - dirty_tx > 0;
1080 dirty_tx++) {
1081 int entry = dirty_tx % TX_RING_SIZE;
1082 int status = tp->tx_ring[entry].status;
1083
1084 if (status < 0)
1085 break; /* It still hasn't been Txed */
1086 /* Check for Rx filter setup frames. */
1087 if (tp->tx_skbuff[entry] == NULL)
1088 continue;
1089
1090 if (status & Tx0DescError) {
1091 /* There was an major error, log it. */
1092#ifndef final_version
1093 if (xircom_debug > 1)
1094 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1095 dev->name, status);
1096#endif
1097 tp->stats.tx_errors++;
1098 if (status & Tx0ManyColl) {
1099 tp->stats.tx_aborted_errors++;
1100 }
1101 if (status & Tx0NoCarrier) tp->stats.tx_carrier_errors++;
1102 if (status & Tx0LateColl) tp->stats.tx_window_errors++;
1103 if (status & Tx0Underflow) tp->stats.tx_fifo_errors++;
1104 } else {
1105 tp->stats.tx_bytes += tp->tx_ring[entry].length & 0x7ff;
1106 tp->stats.collisions += (status >> 3) & 15;
1107 tp->stats.tx_packets++;
1108 }
1109
1110 /* Free the original skb. */
1111 dev_kfree_skb_irq(tp->tx_skbuff[entry]);
1112 tp->tx_skbuff[entry] = NULL;
1113 }
1114
1115#ifndef final_version
1116 if (tp->cur_tx - dirty_tx > TX_RING_SIZE) {
1117 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1118 dev->name, dirty_tx, tp->cur_tx, tp->tx_full);
1119 dirty_tx += TX_RING_SIZE;
1120 }
1121#endif
1122
1123 if (tp->tx_full &&
1124 tp->cur_tx - dirty_tx < TX_RING_SIZE - 2)
1125 /* The ring is no longer full */
1126 tp->tx_full = 0;
1127
1128 if (tp->tx_full)
1129 netif_stop_queue (dev);
1130 else
1131 netif_wake_queue (dev);
1132
1133 tp->dirty_tx = dirty_tx;
1134 if (csr5 & TxDied) {
1135 if (xircom_debug > 2)
1136 printk(KERN_WARNING "%s: The transmitter stopped."
1137 " CSR5 is %x, CSR6 %x, new CSR6 %x.\n",
1138 dev->name, csr5, inl(ioaddr + CSR6), tp->csr6);
1139 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
1140 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1141 }
1142 }
1143
1144 /* Log errors. */
1145 if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */
1146 if (csr5 & LinkChange)
1147 xircom_media_change(dev);
1148 if (csr5 & TxFIFOUnderflow) {
1149 if ((tp->csr6 & TxThreshMask) != TxThreshMask)
1150 tp->csr6 += (1 << TxThreshShift); /* Bump up the Tx threshold */
1151 else
1152 tp->csr6 |= TxStoreForw; /* Store-n-forward. */
1153 /* Restart the transmit process. */
1154 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
1155 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1156 }
1157 if (csr5 & RxDied) { /* Missed a Rx frame. */
1158 tp->stats.rx_errors++;
1159 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1160 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1161 }
1162 /* Clear all error sources, included undocumented ones! */
1163 outl(0x0800f7ba, ioaddr + CSR5);
1164 }
1165 if (--work_budget < 0) {
1166 if (xircom_debug > 1)
1167 printk(KERN_WARNING "%s: Too much work during an interrupt, "
1168 "csr5=0x%8.8x.\n", dev->name, csr5);
1169 /* Acknowledge all interrupt sources. */
1170 outl(0x8001ffff, ioaddr + CSR5);
1171 break;
1172 }
1173 } while (1);
1174
1175 if (xircom_debug > 3)
1176 printk(KERN_DEBUG "%s: exiting interrupt, csr5=%#4.4x.\n",
1177 dev->name, inl(ioaddr + CSR5));
1178
1179 spin_unlock (&tp->lock);
1180 return IRQ_RETVAL(handled);
1181}
1182
1183
1184static int
1185xircom_rx(struct net_device *dev)
1186{
1187 struct xircom_private *tp = netdev_priv(dev);
1188 int entry = tp->cur_rx % RX_RING_SIZE;
1189 int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx;
1190 int work_done = 0;
1191
1192 if (xircom_debug > 4)
1193 printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry,
1194 tp->rx_ring[entry].status);
1195 /* If we own the next entry, it's a new packet. Send it up. */
1196 while (tp->rx_ring[entry].status >= 0) {
1197 s32 status = tp->rx_ring[entry].status;
1198
1199 if (xircom_debug > 5)
1200 printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry,
1201 tp->rx_ring[entry].status);
1202 if (--rx_work_limit < 0)
1203 break;
1204 if ((status & 0x38008300) != 0x0300) {
1205 if ((status & 0x38000300) != 0x0300) {
1206 /* Ignore earlier buffers. */
1207 if ((status & 0xffff) != 0x7fff) {
1208 if (xircom_debug > 1)
1209 printk(KERN_WARNING "%s: Oversized Ethernet frame "
1210 "spanned multiple buffers, status %8.8x!\n",
1211 dev->name, status);
1212 tp->stats.rx_length_errors++;
1213 }
1214 } else if (status & Rx0DescError) {
1215 /* There was a fatal error. */
1216 if (xircom_debug > 2)
1217 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1218 dev->name, status);
1219 tp->stats.rx_errors++; /* end of a packet.*/
1220 if (status & (Rx0Runt | Rx0HugeFrame)) tp->stats.rx_length_errors++;
1221 if (status & Rx0CRCError) tp->stats.rx_crc_errors++;
1222 }
1223 } else {
1224 /* Omit the four octet CRC from the length. */
1225 short pkt_len = ((status >> 16) & 0x7ff) - 4;
1226 struct sk_buff *skb;
1227
1228#ifndef final_version
1229 if (pkt_len > 1518) {
1230 printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n",
1231 dev->name, pkt_len, pkt_len);
1232 pkt_len = 1518;
1233 tp->stats.rx_length_errors++;
1234 }
1235#endif
1236 /* Check if the packet is long enough to accept without copying
1237 to a minimally-sized skbuff. */
1238 if (pkt_len < rx_copybreak
1239 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1240 skb_reserve(skb, 2); /* 16 byte align the IP header */
1241#if ! defined(__alpha__)
1242 skb_copy_to_linear_data(skb, bus_to_virt(tp->rx_ring[entry].buffer1),
1243 pkt_len);
1244 skb_put(skb, pkt_len);
1245#else
1246 memcpy(skb_put(skb, pkt_len),
1247 bus_to_virt(tp->rx_ring[entry].buffer1), pkt_len);
1248#endif
1249 work_done++;
1250 } else { /* Pass up the skb already on the Rx ring. */
1251 skb_put(skb = tp->rx_skbuff[entry], pkt_len);
1252 tp->rx_skbuff[entry] = NULL;
1253 }
1254 skb->protocol = eth_type_trans(skb, dev);
1255 netif_rx(skb);
1256 dev->last_rx = jiffies;
1257 tp->stats.rx_packets++;
1258 tp->stats.rx_bytes += pkt_len;
1259 }
1260 entry = (++tp->cur_rx) % RX_RING_SIZE;
1261 }
1262
1263 /* Refill the Rx ring buffers. */
1264 for (; tp->cur_rx - tp->dirty_rx > 0; tp->dirty_rx++) {
1265 entry = tp->dirty_rx % RX_RING_SIZE;
1266 if (tp->rx_skbuff[entry] == NULL) {
1267 struct sk_buff *skb;
1268 skb = tp->rx_skbuff[entry] = dev_alloc_skb(PKT_BUF_SZ);
1269 if (skb == NULL)
1270 break;
1271 skb->dev = dev; /* Mark as being used by this device. */
1272 tp->rx_ring[entry].buffer1 = virt_to_bus(skb->data);
1273 work_done++;
1274 }
1275 tp->rx_ring[entry].status = Rx0DescOwned;
1276 }
1277
1278 return work_done;
1279}
1280
1281
1282static void
1283xircom_down(struct net_device *dev)
1284{
1285 long ioaddr = dev->base_addr;
1286 struct xircom_private *tp = netdev_priv(dev);
1287
1288 /* Disable interrupts by clearing the interrupt mask. */
1289 outl(0, ioaddr + CSR7);
1290 /* Stop the chip's Tx and Rx processes. */
1291 outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr);
1292
1293 if (inl(ioaddr + CSR6) != 0xffffffff)
1294 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1295
1296 dev->if_port = tp->saved_if_port;
1297}
1298
1299
1300static int
1301xircom_close(struct net_device *dev)
1302{
1303 long ioaddr = dev->base_addr;
1304 struct xircom_private *tp = netdev_priv(dev);
1305 int i;
1306
1307 if (xircom_debug > 1)
1308 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1309 dev->name, inl(ioaddr + CSR5));
1310
1311 netif_stop_queue(dev);
1312
1313 if (netif_device_present(dev))
1314 xircom_down(dev);
1315
1316 free_irq(dev->irq, dev);
1317
1318 /* Free all the skbuffs in the Rx queue. */
1319 for (i = 0; i < RX_RING_SIZE; i++) {
1320 struct sk_buff *skb = tp->rx_skbuff[i];
1321 tp->rx_skbuff[i] = NULL;
1322 tp->rx_ring[i].status = 0; /* Not owned by Xircom chip. */
1323 tp->rx_ring[i].length = 0;
1324 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
1325 if (skb) {
1326 dev_kfree_skb(skb);
1327 }
1328 }
1329 for (i = 0; i < TX_RING_SIZE; i++) {
1330 if (tp->tx_skbuff[i])
1331 dev_kfree_skb(tp->tx_skbuff[i]);
1332 tp->tx_skbuff[i] = NULL;
1333 }
1334
1335 tp->open = 0;
1336 return 0;
1337}
1338
1339
1340static struct net_device_stats *xircom_get_stats(struct net_device *dev)
1341{
1342 struct xircom_private *tp = netdev_priv(dev);
1343 long ioaddr = dev->base_addr;
1344
1345 if (netif_device_present(dev))
1346 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1347
1348 return &tp->stats;
1349}
1350
1351static int xircom_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1352{
1353 struct xircom_private *tp = netdev_priv(dev);
1354 ecmd->supported =
1355 SUPPORTED_10baseT_Half |
1356 SUPPORTED_10baseT_Full |
1357 SUPPORTED_100baseT_Half |
1358 SUPPORTED_100baseT_Full |
1359 SUPPORTED_Autoneg |
1360 SUPPORTED_MII;
1361
1362 ecmd->advertising = ADVERTISED_MII;
1363 if (tp->advertising[0] & ADVERTISE_10HALF)
1364 ecmd->advertising |= ADVERTISED_10baseT_Half;
1365 if (tp->advertising[0] & ADVERTISE_10FULL)
1366 ecmd->advertising |= ADVERTISED_10baseT_Full;
1367 if (tp->advertising[0] & ADVERTISE_100HALF)
1368 ecmd->advertising |= ADVERTISED_100baseT_Half;
1369 if (tp->advertising[0] & ADVERTISE_100FULL)
1370 ecmd->advertising |= ADVERTISED_100baseT_Full;
1371 if (tp->autoneg) {
1372 ecmd->advertising |= ADVERTISED_Autoneg;
1373 ecmd->autoneg = AUTONEG_ENABLE;
1374 } else
1375 ecmd->autoneg = AUTONEG_DISABLE;
1376
1377 ecmd->port = PORT_MII;
1378 ecmd->transceiver = XCVR_INTERNAL;
1379 ecmd->phy_address = tp->phys[0];
1380 ecmd->speed = tp->speed100 ? SPEED_100 : SPEED_10;
1381 ecmd->duplex = tp->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1382 ecmd->maxtxpkt = TX_RING_SIZE / 2;
1383 ecmd->maxrxpkt = 0;
1384 return 0;
1385}
1386
1387static int xircom_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1388{
1389 struct xircom_private *tp = netdev_priv(dev);
1390 u16 autoneg, speed100, full_duplex;
1391
1392 autoneg = (ecmd->autoneg == AUTONEG_ENABLE);
1393 speed100 = (ecmd->speed == SPEED_100);
1394 full_duplex = (ecmd->duplex == DUPLEX_FULL);
1395
1396 tp->autoneg = autoneg;
1397 if (speed100 != tp->speed100 ||
1398 full_duplex != tp->full_duplex) {
1399 tp->speed100 = speed100;
1400 tp->full_duplex = full_duplex;
1401 /* change advertising bits */
1402 tp->advertising[0] &= ~(ADVERTISE_10HALF |
1403 ADVERTISE_10FULL |
1404 ADVERTISE_100HALF |
1405 ADVERTISE_100FULL |
1406 ADVERTISE_100BASE4);
1407 if (speed100) {
1408 if (full_duplex)
1409 tp->advertising[0] |= ADVERTISE_100FULL;
1410 else
1411 tp->advertising[0] |= ADVERTISE_100HALF;
1412 } else {
1413 if (full_duplex)
1414 tp->advertising[0] |= ADVERTISE_10FULL;
1415 else
1416 tp->advertising[0] |= ADVERTISE_10HALF;
1417 }
1418 }
1419 check_duplex(dev);
1420 return 0;
1421}
1422
1423static void xircom_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1424{
1425 struct xircom_private *tp = netdev_priv(dev);
1426 strcpy(info->driver, DRV_NAME);
1427 strcpy(info->version, DRV_VERSION);
1428 strcpy(info->bus_info, pci_name(tp->pdev));
1429}
1430
1431static const struct ethtool_ops ops = {
1432 .get_settings = xircom_get_settings,
1433 .set_settings = xircom_set_settings,
1434 .get_drvinfo = xircom_get_drvinfo,
1435};
1436
1437/* Provide ioctl() calls to examine the MII xcvr state. */
1438static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1439{
1440 struct xircom_private *tp = netdev_priv(dev);
1441 u16 *data = (u16 *)&rq->ifr_ifru;
1442 int phy = tp->phys[0] & 0x1f;
1443 unsigned long flags;
1444
1445 switch(cmd) {
1446 /* Legacy mii-diag interface */
1447 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1448 if (tp->mii_cnt)
1449 data[0] = phy;
1450 else
1451 return -ENODEV;
1452 return 0;
1453 case SIOCGMIIREG: /* Read MII PHY register. */
1454 save_flags(flags);
1455 cli();
1456 data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f);
1457 restore_flags(flags);
1458 return 0;
1459 case SIOCSMIIREG: /* Write MII PHY register. */
1460 if (!capable(CAP_NET_ADMIN))
1461 return -EPERM;
1462 save_flags(flags);
1463 cli();
1464 if (data[0] == tp->phys[0]) {
1465 u16 value = data[2];
1466 switch (data[1]) {
1467 case 0:
1468 if (value & (BMCR_RESET | BMCR_ANENABLE))
1469 /* Autonegotiation. */
1470 tp->autoneg = 1;
1471 else {
1472 tp->full_duplex = (value & BMCR_FULLDPLX) ? 1 : 0;
1473 tp->autoneg = 0;
1474 }
1475 break;
1476 case 4:
1477 tp->advertising[0] = value;
1478 break;
1479 }
1480 check_duplex(dev);
1481 }
1482 mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1483 restore_flags(flags);
1484 return 0;
1485 default:
1486 return -EOPNOTSUPP;
1487 }
1488
1489 return -EOPNOTSUPP;
1490}
1491
1492/* Set or clear the multicast filter for this adaptor.
1493 Note that we only use exclusion around actually queueing the
1494 new frame, not around filling tp->setup_frame. This is non-deterministic
1495 when re-entered but still correct. */
1496static void set_rx_mode(struct net_device *dev)
1497{
1498 struct xircom_private *tp = netdev_priv(dev);
1499 struct dev_mc_list *mclist;
1500 long ioaddr = dev->base_addr;
1501 int csr6 = inl(ioaddr + CSR6);
1502 u16 *eaddrs, *setup_frm;
1503 u32 tx_flags;
1504 int i;
1505
1506 tp->csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit);
1507 csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit);
1508 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1509 tp->csr6 |= PromiscBit;
1510 csr6 |= PromiscBit;
1511 goto out;
1512 }
1513
1514 if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1515 /* Too many to filter well -- accept all multicasts. */
1516 tp->csr6 |= AllMultiBit;
1517 csr6 |= AllMultiBit;
1518 goto out;
1519 }
1520
1521 tx_flags = Tx1WholePkt | Tx1SetupPkt | PKT_SETUP_SZ;
1522
1523 /* Note that only the low-address shortword of setup_frame is valid! */
1524 setup_frm = tp->setup_frame;
1525 mclist = dev->mc_list;
1526
1527 /* Fill the first entry with our physical address. */
1528 eaddrs = (u16 *)dev->dev_addr;
1529 *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2;
1530 *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2;
1531 *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2;
1532
1533 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1534 u32 *hash_table = (u32 *)(tp->setup_frame + 4 * 12);
1535 u32 hash, hash2;
1536
1537 tx_flags |= Tx1HashSetup;
1538 tp->csr6 |= HashFilterBit;
1539 csr6 |= HashFilterBit;
1540
1541 /* Fill the unused 3 entries with the broadcast address.
1542 At least one entry *must* contain the broadcast address!!!*/
1543 for (i = 0; i < 3; i++) {
1544 *setup_frm = 0xffff; setup_frm += 2;
1545 *setup_frm = 0xffff; setup_frm += 2;
1546 *setup_frm = 0xffff; setup_frm += 2;
1547 }
1548
1549 /* Truly brain-damaged hash filter layout */
1550 /* XXX: not sure if I should take the last or the first 9 bits */
1551 for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) {
1552 u32 *hptr;
1553 hash = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
1554 if (hash < 384) {
1555 hash2 = hash + ((hash >> 4) << 4) +
1556 ((hash >> 5) << 5);
1557 } else {
1558 hash -= 384;
1559 hash2 = 64 + hash + (hash >> 4) * 80;
1560 }
1561 hptr = &hash_table[hash2 & ~0x1f];
1562 *hptr |= cpu_to_le32(1 << (hash2 & 0x1f));
1563 }
1564 } else {
1565 /* We have <= 14 mcast addresses so we can use Xircom's
1566 wonderful 16-address perfect filter. */
1567 for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) {
1568 eaddrs = (u16 *)mclist->dmi_addr;
1569 *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2;
1570 *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2;
1571 *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2;
1572 }
1573 /* Fill the unused entries with the broadcast address.
1574 At least one entry *must* contain the broadcast address!!!*/
1575 for (; i < 15; i++) {
1576 *setup_frm = 0xffff; setup_frm += 2;
1577 *setup_frm = 0xffff; setup_frm += 2;
1578 *setup_frm = 0xffff; setup_frm += 2;
1579 }
1580 }
1581
1582 /* Now add this frame to the Tx list. */
1583 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1584 /* Same setup recently queued, we need not add it. */
1585 /* XXX: Huh? All it means is that the Tx list is full...*/
1586 } else {
1587 unsigned long flags;
1588 unsigned int entry;
1589 int dummy = -1;
1590
1591 save_flags(flags); cli();
1592 entry = tp->cur_tx++ % TX_RING_SIZE;
1593
1594 if (entry != 0) {
1595 /* Avoid a chip errata by prefixing a dummy entry. */
1596 tp->tx_skbuff[entry] = NULL;
1597 tp->tx_ring[entry].length =
1598 (entry == TX_RING_SIZE - 1) ? Tx1RingWrap : 0;
1599 tp->tx_ring[entry].buffer1 = 0;
1600 /* race with chip, set Tx0DescOwned later */
1601 dummy = entry;
1602 entry = tp->cur_tx++ % TX_RING_SIZE;
1603 }
1604
1605 tp->tx_skbuff[entry] = NULL;
1606 /* Put the setup frame on the Tx list. */
1607 if (entry == TX_RING_SIZE - 1)
1608 tx_flags |= Tx1RingWrap; /* Wrap ring. */
1609 tp->tx_ring[entry].length = tx_flags;
1610 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->setup_frame);
1611 tp->tx_ring[entry].status = Tx0DescOwned;
1612 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2) {
1613 tp->tx_full = 1;
1614 netif_stop_queue (dev);
1615 }
1616 if (dummy >= 0)
1617 tp->tx_ring[dummy].status = Tx0DescOwned;
1618 restore_flags(flags);
1619 /* Trigger an immediate transmit demand. */
1620 outl(0, ioaddr + CSR1);
1621 }
1622
1623out:
1624 outl_CSR6(csr6, ioaddr);
1625}
1626
1627
1628static struct pci_device_id xircom_pci_table[] = {
1629 { 0x115D, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, X3201_3 },
1630 {0},
1631};
1632MODULE_DEVICE_TABLE(pci, xircom_pci_table);
1633
1634
1635#ifdef CONFIG_PM
1636static int xircom_suspend(struct pci_dev *pdev, pm_message_t state)
1637{
1638 struct net_device *dev = pci_get_drvdata(pdev);
1639 struct xircom_private *tp = netdev_priv(dev);
1640 printk(KERN_INFO "xircom_suspend(%s)\n", dev->name);
1641 if (tp->open)
1642 xircom_down(dev);
1643
1644 pci_save_state(pdev);
1645 pci_disable_device(pdev);
1646 pci_set_power_state(pdev, 3);
1647
1648 return 0;
1649}
1650
1651
1652static int xircom_resume(struct pci_dev *pdev)
1653{
1654 struct net_device *dev = pci_get_drvdata(pdev);
1655 struct xircom_private *tp = netdev_priv(dev);
1656 printk(KERN_INFO "xircom_resume(%s)\n", dev->name);
1657
1658 pci_set_power_state(pdev,0);
1659 pci_enable_device(pdev);
1660 pci_restore_state(pdev);
1661
1662 /* Bring the chip out of sleep mode.
1663 Caution: Snooze mode does not work with some boards! */
1664 if (xircom_tbl[tp->chip_id].flags & HAS_ACPI)
1665 pci_write_config_dword(tp->pdev, PCI_POWERMGMT, 0);
1666
1667 transceiver_voodoo(dev);
1668 if (xircom_tbl[tp->chip_id].flags & HAS_MII)
1669 check_duplex(dev);
1670
1671 if (tp->open)
1672 xircom_up(dev);
1673 return 0;
1674}
1675#endif /* CONFIG_PM */
1676
1677
1678static void __devexit xircom_remove_one(struct pci_dev *pdev)
1679{
1680 struct net_device *dev = pci_get_drvdata(pdev);
1681
1682 printk(KERN_INFO "xircom_remove_one(%s)\n", dev->name);
1683 unregister_netdev(dev);
1684 pci_release_regions(pdev);
1685 free_netdev(dev);
1686 pci_set_drvdata(pdev, NULL);
1687}
1688
1689
1690static struct pci_driver xircom_driver = {
1691 .name = DRV_NAME,
1692 .id_table = xircom_pci_table,
1693 .probe = xircom_init_one,
1694 .remove = __devexit_p(xircom_remove_one),
1695#ifdef CONFIG_PM
1696 .suspend = xircom_suspend,
1697 .resume = xircom_resume
1698#endif /* CONFIG_PM */
1699};
1700
1701
1702static int __init xircom_init(void)
1703{
1704/* when a module, this is printed whether or not devices are found in probe */
1705#ifdef MODULE
1706 printk(version);
1707#endif
1708 return pci_register_driver(&xircom_driver);
1709}
1710
1711
1712static void __exit xircom_exit(void)
1713{
1714 pci_unregister_driver(&xircom_driver);
1715}
1716
1717module_init(xircom_init)
1718module_exit(xircom_exit)
1719
1720/*
1721 * Local variables:
1722 * c-indent-level: 4
1723 * c-basic-offset: 4
1724 * tab-width: 4
1725 * End:
1726 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 16:08:15 -0500