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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/tulip
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/tulip')
-rw-r--r--drivers/net/tulip/21142.c245
-rw-r--r--drivers/net/tulip/Kconfig166
-rw-r--r--drivers/net/tulip/Makefile17
-rw-r--r--drivers/net/tulip/de2104x.c2187
-rw-r--r--drivers/net/tulip/de4x5.c5778
-rw-r--r--drivers/net/tulip/de4x5.h1029
-rw-r--r--drivers/net/tulip/dmfe.c2066
-rw-r--r--drivers/net/tulip/eeprom.c357
-rw-r--r--drivers/net/tulip/interrupt.c786
-rw-r--r--drivers/net/tulip/media.c562
-rw-r--r--drivers/net/tulip/pnic.c172
-rw-r--r--drivers/net/tulip/pnic2.c407
-rw-r--r--drivers/net/tulip/timer.c175
-rw-r--r--drivers/net/tulip/tulip.h493
-rw-r--r--drivers/net/tulip/tulip_core.c1861
-rw-r--r--drivers/net/tulip/winbond-840.c1716
-rw-r--r--drivers/net/tulip/xircom_cb.c1277
-rw-r--r--drivers/net/tulip/xircom_tulip_cb.c1748
18 files changed, 21042 insertions, 0 deletions
diff --git a/drivers/net/tulip/21142.c b/drivers/net/tulip/21142.c
new file mode 100644
index 000000000000..5db694c4eb02
--- /dev/null
+++ b/drivers/net/tulip/21142.c
@@ -0,0 +1,245 @@
1/*
2 drivers/net/tulip/21142.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include "tulip.h"
20
21
22static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
23u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
24static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
25
26
27/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
28 of available transceivers. */
29void t21142_timer(unsigned long data)
30{
31 struct net_device *dev = (struct net_device *)data;
32 struct tulip_private *tp = netdev_priv(dev);
33 void __iomem *ioaddr = tp->base_addr;
34 int csr12 = ioread32(ioaddr + CSR12);
35 int next_tick = 60*HZ;
36 int new_csr6 = 0;
37
38 if (tulip_debug > 2)
39 printk(KERN_INFO"%s: 21143 negotiation status %8.8x, %s.\n",
40 dev->name, csr12, medianame[dev->if_port]);
41 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
42 if (tulip_check_duplex(dev) < 0) {
43 netif_carrier_off(dev);
44 next_tick = 3*HZ;
45 } else {
46 netif_carrier_on(dev);
47 next_tick = 60*HZ;
48 }
49 } else if (tp->nwayset) {
50 /* Don't screw up a negotiated session! */
51 if (tulip_debug > 1)
52 printk(KERN_INFO"%s: Using NWay-set %s media, csr12 %8.8x.\n",
53 dev->name, medianame[dev->if_port], csr12);
54 } else if (tp->medialock) {
55 ;
56 } else if (dev->if_port == 3) {
57 if (csr12 & 2) { /* No 100mbps link beat, revert to 10mbps. */
58 if (tulip_debug > 1)
59 printk(KERN_INFO"%s: No 21143 100baseTx link beat, %8.8x, "
60 "trying NWay.\n", dev->name, csr12);
61 t21142_start_nway(dev);
62 next_tick = 3*HZ;
63 }
64 } else if ((csr12 & 0x7000) != 0x5000) {
65 /* Negotiation failed. Search media types. */
66 if (tulip_debug > 1)
67 printk(KERN_INFO"%s: 21143 negotiation failed, status %8.8x.\n",
68 dev->name, csr12);
69 if (!(csr12 & 4)) { /* 10mbps link beat good. */
70 new_csr6 = 0x82420000;
71 dev->if_port = 0;
72 iowrite32(0, ioaddr + CSR13);
73 iowrite32(0x0003FFFF, ioaddr + CSR14);
74 iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
75 iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13);
76 } else {
77 /* Select 100mbps port to check for link beat. */
78 new_csr6 = 0x83860000;
79 dev->if_port = 3;
80 iowrite32(0, ioaddr + CSR13);
81 iowrite32(0x0003FF7F, ioaddr + CSR14);
82 iowrite16(8, ioaddr + CSR15);
83 iowrite32(1, ioaddr + CSR13);
84 }
85 if (tulip_debug > 1)
86 printk(KERN_INFO"%s: Testing new 21143 media %s.\n",
87 dev->name, medianame[dev->if_port]);
88 if (new_csr6 != (tp->csr6 & ~0x00D5)) {
89 tp->csr6 &= 0x00D5;
90 tp->csr6 |= new_csr6;
91 iowrite32(0x0301, ioaddr + CSR12);
92 tulip_restart_rxtx(tp);
93 }
94 next_tick = 3*HZ;
95 }
96
97 /* mod_timer synchronizes us with potential add_timer calls
98 * from interrupts.
99 */
100 mod_timer(&tp->timer, RUN_AT(next_tick));
101}
102
103
104void t21142_start_nway(struct net_device *dev)
105{
106 struct tulip_private *tp = netdev_priv(dev);
107 void __iomem *ioaddr = tp->base_addr;
108 int csr14 = ((tp->sym_advertise & 0x0780) << 9) |
109 ((tp->sym_advertise & 0x0020) << 1) | 0xffbf;
110
111 dev->if_port = 0;
112 tp->nway = tp->mediasense = 1;
113 tp->nwayset = tp->lpar = 0;
114 if (tulip_debug > 1)
115 printk(KERN_DEBUG "%s: Restarting 21143 autonegotiation, csr14=%8.8x.\n",
116 dev->name, csr14);
117 iowrite32(0x0001, ioaddr + CSR13);
118 udelay(100);
119 iowrite32(csr14, ioaddr + CSR14);
120 tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? FullDuplex : 0);
121 iowrite32(tp->csr6, ioaddr + CSR6);
122 if (tp->mtable && tp->mtable->csr15dir) {
123 iowrite32(tp->mtable->csr15dir, ioaddr + CSR15);
124 iowrite32(tp->mtable->csr15val, ioaddr + CSR15);
125 } else
126 iowrite16(0x0008, ioaddr + CSR15);
127 iowrite32(0x1301, ioaddr + CSR12); /* Trigger NWAY. */
128}
129
130
131
132void t21142_lnk_change(struct net_device *dev, int csr5)
133{
134 struct tulip_private *tp = netdev_priv(dev);
135 void __iomem *ioaddr = tp->base_addr;
136 int csr12 = ioread32(ioaddr + CSR12);
137
138 if (tulip_debug > 1)
139 printk(KERN_INFO"%s: 21143 link status interrupt %8.8x, CSR5 %x, "
140 "%8.8x.\n", dev->name, csr12, csr5, ioread32(ioaddr + CSR14));
141
142 /* If NWay finished and we have a negotiated partner capability. */
143 if (tp->nway && !tp->nwayset && (csr12 & 0x7000) == 0x5000) {
144 int setup_done = 0;
145 int negotiated = tp->sym_advertise & (csr12 >> 16);
146 tp->lpar = csr12 >> 16;
147 tp->nwayset = 1;
148 if (negotiated & 0x0100) dev->if_port = 5;
149 else if (negotiated & 0x0080) dev->if_port = 3;
150 else if (negotiated & 0x0040) dev->if_port = 4;
151 else if (negotiated & 0x0020) dev->if_port = 0;
152 else {
153 tp->nwayset = 0;
154 if ((csr12 & 2) == 0 && (tp->sym_advertise & 0x0180))
155 dev->if_port = 3;
156 }
157 tp->full_duplex = (tulip_media_cap[dev->if_port] & MediaAlwaysFD) ? 1:0;
158
159 if (tulip_debug > 1) {
160 if (tp->nwayset)
161 printk(KERN_INFO "%s: Switching to %s based on link "
162 "negotiation %4.4x & %4.4x = %4.4x.\n",
163 dev->name, medianame[dev->if_port], tp->sym_advertise,
164 tp->lpar, negotiated);
165 else
166 printk(KERN_INFO "%s: Autonegotiation failed, using %s,"
167 " link beat status %4.4x.\n",
168 dev->name, medianame[dev->if_port], csr12);
169 }
170
171 if (tp->mtable) {
172 int i;
173 for (i = 0; i < tp->mtable->leafcount; i++)
174 if (tp->mtable->mleaf[i].media == dev->if_port) {
175 int startup = ! ((tp->chip_id == DC21143 && tp->revision == 65));
176 tp->cur_index = i;
177 tulip_select_media(dev, startup);
178 setup_done = 1;
179 break;
180 }
181 }
182 if ( ! setup_done) {
183 tp->csr6 = (dev->if_port & 1 ? 0x838E0000 : 0x82420000) | (tp->csr6 & 0x20ff);
184 if (tp->full_duplex)
185 tp->csr6 |= 0x0200;
186 iowrite32(1, ioaddr + CSR13);
187 }
188#if 0 /* Restart shouldn't be needed. */
189 iowrite32(tp->csr6 | RxOn, ioaddr + CSR6);
190 if (tulip_debug > 2)
191 printk(KERN_DEBUG "%s: Restarting Tx and Rx, CSR5 is %8.8x.\n",
192 dev->name, ioread32(ioaddr + CSR5));
193#endif
194 tulip_start_rxtx(tp);
195 if (tulip_debug > 2)
196 printk(KERN_DEBUG "%s: Setting CSR6 %8.8x/%x CSR12 %8.8x.\n",
197 dev->name, tp->csr6, ioread32(ioaddr + CSR6),
198 ioread32(ioaddr + CSR12));
199 } else if ((tp->nwayset && (csr5 & 0x08000000)
200 && (dev->if_port == 3 || dev->if_port == 5)
201 && (csr12 & 2) == 2) ||
202 (tp->nway && (csr5 & (TPLnkFail)))) {
203 /* Link blew? Maybe restart NWay. */
204 del_timer_sync(&tp->timer);
205 t21142_start_nway(dev);
206 tp->timer.expires = RUN_AT(3*HZ);
207 add_timer(&tp->timer);
208 } else if (dev->if_port == 3 || dev->if_port == 5) {
209 if (tulip_debug > 1)
210 printk(KERN_INFO"%s: 21143 %s link beat %s.\n",
211 dev->name, medianame[dev->if_port],
212 (csr12 & 2) ? "failed" : "good");
213 if ((csr12 & 2) && ! tp->medialock) {
214 del_timer_sync(&tp->timer);
215 t21142_start_nway(dev);
216 tp->timer.expires = RUN_AT(3*HZ);
217 add_timer(&tp->timer);
218 } else if (dev->if_port == 5)
219 iowrite32(ioread32(ioaddr + CSR14) & ~0x080, ioaddr + CSR14);
220 } else if (dev->if_port == 0 || dev->if_port == 4) {
221 if ((csr12 & 4) == 0)
222 printk(KERN_INFO"%s: 21143 10baseT link beat good.\n",
223 dev->name);
224 } else if (!(csr12 & 4)) { /* 10mbps link beat good. */
225 if (tulip_debug)
226 printk(KERN_INFO"%s: 21143 10mbps sensed media.\n",
227 dev->name);
228 dev->if_port = 0;
229 } else if (tp->nwayset) {
230 if (tulip_debug)
231 printk(KERN_INFO"%s: 21143 using NWay-set %s, csr6 %8.8x.\n",
232 dev->name, medianame[dev->if_port], tp->csr6);
233 } else { /* 100mbps link beat good. */
234 if (tulip_debug)
235 printk(KERN_INFO"%s: 21143 100baseTx sensed media.\n",
236 dev->name);
237 dev->if_port = 3;
238 tp->csr6 = 0x838E0000 | (tp->csr6 & 0x20ff);
239 iowrite32(0x0003FF7F, ioaddr + CSR14);
240 iowrite32(0x0301, ioaddr + CSR12);
241 tulip_restart_rxtx(tp);
242 }
243}
244
245
diff --git a/drivers/net/tulip/Kconfig b/drivers/net/tulip/Kconfig
new file mode 100644
index 000000000000..e2cdaf876201
--- /dev/null
+++ b/drivers/net/tulip/Kconfig
@@ -0,0 +1,166 @@
1#
2# Tulip family network device configuration
3#
4
5menu "Tulip family network device support"
6 depends on NET_ETHERNET && (PCI || EISA || CARDBUS)
7
8config NET_TULIP
9 bool "\"Tulip\" family network device support"
10 help
11 This selects the "Tulip" family of EISA/PCI network cards.
12
13config DE2104X
14 tristate "Early DECchip Tulip (dc2104x) PCI support (EXPERIMENTAL)"
15 depends on NET_TULIP && PCI && EXPERIMENTAL
16 select CRC32
17 ---help---
18 This driver is developed for the SMC EtherPower series Ethernet
19 cards and also works with cards based on the DECchip
20 21040 (Tulip series) chips. Some LinkSys PCI cards are
21 of this type. (If your card is NOT SMC EtherPower 10/100 PCI
22 (smc9332dst), you can also try the driver for "Generic DECchip"
23 cards, below. However, most people with a network card of this type
24 will say Y here.) Do read the Ethernet-HOWTO, available from
25 <http://www.tldp.org/docs.html#howto>.
26
27 To compile this driver as a module, choose M here and read
28 <file:Documentation/networking/net-modules.txt>. The module will
29 be called de2104x.
30
31config TULIP
32 tristate "DECchip Tulip (dc2114x) PCI support"
33 depends on NET_TULIP && PCI
34 select CRC32
35 ---help---
36 This driver is developed for the SMC EtherPower series Ethernet
37 cards and also works with cards based on the DECchip
38 21140 (Tulip series) chips. Some LinkSys PCI cards are
39 of this type. (If your card is NOT SMC EtherPower 10/100 PCI
40 (smc9332dst), you can also try the driver for "Generic DECchip"
41 cards, above. However, most people with a network card of this type
42 will say Y here.) Do read the Ethernet-HOWTO, available from
43 <http://www.tldp.org/docs.html#howto>.
44
45 To compile this driver as a module, choose M here and read
46 <file:Documentation/networking/net-modules.txt>. The module will
47 be called tulip.
48
49config TULIP_MWI
50 bool "New bus configuration (EXPERIMENTAL)"
51 depends on TULIP && EXPERIMENTAL
52 help
53 This configures your Tulip card specifically for the card and
54 system cache line size type you are using.
55
56 This is experimental code, not yet tested on many boards.
57
58 If unsure, say N.
59
60config TULIP_MMIO
61 bool "Use PCI shared mem for NIC registers"
62 depends on TULIP
63 help
64 Use PCI shared memory for the NIC registers, rather than going through
65 the Tulip's PIO (programmed I/O ports). Faster, but could produce
66 obscure bugs if your mainboard has memory controller timing issues.
67 If in doubt, say N.
68
69config TULIP_NAPI
70 bool "Use NAPI RX polling "
71 depends on TULIP
72 help
73 NAPI is a new driver API designed to reduce CPU and interrupt load
74 when the driver is receiving lots of packets from the card. It is
75 still somewhat experimental and thus not yet enabled by default.
76
77 If your estimated Rx load is 10kpps or more, or if the card will be
78 deployed on potentially unfriendly networks (e.g. in a firewall),
79 then say Y here.
80
81 See <file:Documentation/networking/NAPI_HOWTO.txt> for more
82 information.
83
84 If in doubt, say N.
85
86config TULIP_NAPI_HW_MITIGATION
87 bool "Use Interrupt Mitigation "
88 depends on TULIP_NAPI
89 ---help---
90 Use HW to reduce RX interrupts. Not strict necessary since NAPI reduces
91 RX interrupts but itself. Although this reduces RX interrupts even at
92 low levels traffic at the cost of a small latency.
93
94 If in doubt, say Y.
95
96config DE4X5
97 tristate "Generic DECchip & DIGITAL EtherWORKS PCI/EISA"
98 depends on NET_TULIP && (PCI || EISA)
99 select CRC32
100 ---help---
101 This is support for the DIGITAL series of PCI/EISA Ethernet cards.
102 These include the DE425, DE434, DE435, DE450 and DE500 models. If
103 you have a network card of this type, say Y and read the
104 Ethernet-HOWTO, available from
105 <http://www.tldp.org/docs.html#howto>. More specific
106 information is contained in
107 <file:Documentation/networking/de4x5.txt>.
108
109 To compile this driver as a module, choose M here and read
110 <file:Documentation/networking/net-modules.txt>. The module will
111 be called de4x5.
112
113config WINBOND_840
114 tristate "Winbond W89c840 Ethernet support"
115 depends on NET_TULIP && PCI
116 select CRC32
117 select MII
118 help
119 This driver is for the Winbond W89c840 chip. It also works with
120 the TX9882 chip on the Compex RL100-ATX board.
121 More specific information and updates are available from
122 <http://www.scyld.com/network/drivers.html>.
123
124config DM9102
125 tristate "Davicom DM910x/DM980x support"
126 depends on NET_TULIP && PCI
127 select CRC32
128 ---help---
129 This driver is for DM9102(A)/DM9132/DM9801 compatible PCI cards from
130 Davicom (<http://www.davicom.com.tw/>). If you have such a network
131 (Ethernet) card, say Y. Some information is contained in the file
132 <file:Documentation/networking/dmfe.txt>.
133
134 To compile this driver as a module, choose M here and read
135 <file:Documentation/networking/net-modules.txt>. The module will
136 be called dmfe.
137
138config PCMCIA_XIRCOM
139 tristate "Xircom CardBus support (new driver)"
140 depends on NET_TULIP && CARDBUS
141 ---help---
142 This driver is for the Digital "Tulip" Ethernet CardBus adapters.
143 It should work with most DEC 21*4*-based chips/ethercards, as well
144 as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
145 ASIX.
146
147 To compile this driver as a module, choose M here and read
148 <file:Documentation/networking/net-modules.txt>. The module will
149 be called xircom_cb. If unsure, say N.
150
151config PCMCIA_XIRTULIP
152 tristate "Xircom Tulip-like CardBus support (old driver)"
153 depends on NET_TULIP && CARDBUS && BROKEN_ON_SMP
154 select CRC32
155 ---help---
156 This driver is for the Digital "Tulip" Ethernet CardBus adapters.
157 It should work with most DEC 21*4*-based chips/ethercards, as well
158 as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
159 ASIX.
160
161 To compile this driver as a module, choose M here and read
162 <file:Documentation/networking/net-modules.txt>. The module will
163 be called xircom_tulip_cb. If unsure, say N.
164
165endmenu
166
diff --git a/drivers/net/tulip/Makefile b/drivers/net/tulip/Makefile
new file mode 100644
index 000000000000..8bb9b4683979
--- /dev/null
+++ b/drivers/net/tulip/Makefile
@@ -0,0 +1,17 @@
1#
2# Makefile for the Linux "Tulip" family network device drivers.
3#
4
5obj-$(CONFIG_PCMCIA_XIRTULIP) += xircom_tulip_cb.o
6obj-$(CONFIG_PCMCIA_XIRCOM) += xircom_cb.o
7obj-$(CONFIG_DM9102) += dmfe.o
8obj-$(CONFIG_WINBOND_840) += winbond-840.o
9obj-$(CONFIG_DE2104X) += de2104x.o
10obj-$(CONFIG_TULIP) += tulip.o
11obj-$(CONFIG_DE4X5) += de4x5.o
12
13# Declare multi-part drivers.
14
15tulip-objs := eeprom.o interrupt.o media.o \
16 timer.o tulip_core.o \
17 21142.o pnic.o pnic2.o
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c
new file mode 100644
index 000000000000..008e19210e66
--- /dev/null
+++ b/drivers/net/tulip/de2104x.c
@@ -0,0 +1,2187 @@
1/* de2104x.c: A Linux PCI Ethernet driver for Intel/Digital 21040/1 chips. */
2/*
3 Copyright 2001,2003 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright 1994, 1995 Digital Equipment Corporation. [de4x5.c]
6 Written/copyright 1994-2001 by Donald Becker. [tulip.c]
7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL.
14
15 See the file COPYING in this distribution for more information.
16
17 TODO, in rough priority order:
18 * Support forcing media type with a module parameter,
19 like dl2k.c/sundance.c
20 * Constants (module parms?) for Rx work limit
21 * Complete reset on PciErr
22 * Jumbo frames / dev->change_mtu
23 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
24 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
25 * Implement Tx software interrupt mitigation via
26 Tx descriptor bit
27
28 */
29
30#define DRV_NAME "de2104x"
31#define DRV_VERSION "0.7"
32#define DRV_RELDATE "Mar 17, 2004"
33
34#include <linux/config.h>
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/ethtool.h>
43#include <linux/compiler.h>
44#include <linux/rtnetlink.h>
45#include <linux/crc32.h>
46
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/uaccess.h>
50#include <asm/unaligned.h>
51
52/* These identify the driver base version and may not be removed. */
53static char version[] =
54KERN_INFO DRV_NAME " PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
55
56MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
57MODULE_DESCRIPTION("Intel/Digital 21040/1 series PCI Ethernet driver");
58MODULE_LICENSE("GPL");
59MODULE_VERSION(DRV_VERSION);
60
61static int debug = -1;
62module_param (debug, int, 0);
63MODULE_PARM_DESC (debug, "de2104x bitmapped message enable number");
64
65/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
66#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
67 || defined(__sparc_) || defined(__ia64__) \
68 || defined(__sh__) || defined(__mips__)
69static int rx_copybreak = 1518;
70#else
71static int rx_copybreak = 100;
72#endif
73module_param (rx_copybreak, int, 0);
74MODULE_PARM_DESC (rx_copybreak, "de2104x Breakpoint at which Rx packets are copied");
75
76#define PFX DRV_NAME ": "
77
78#define DE_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86#define DE_RX_RING_SIZE 64
87#define DE_TX_RING_SIZE 64
88#define DE_RING_BYTES \
89 ((sizeof(struct de_desc) * DE_RX_RING_SIZE) + \
90 (sizeof(struct de_desc) * DE_TX_RING_SIZE))
91#define NEXT_TX(N) (((N) + 1) & (DE_TX_RING_SIZE - 1))
92#define NEXT_RX(N) (((N) + 1) & (DE_RX_RING_SIZE - 1))
93#define TX_BUFFS_AVAIL(CP) \
94 (((CP)->tx_tail <= (CP)->tx_head) ? \
95 (CP)->tx_tail + (DE_TX_RING_SIZE - 1) - (CP)->tx_head : \
96 (CP)->tx_tail - (CP)->tx_head - 1)
97
98#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
99#define RX_OFFSET 2
100
101#define DE_SETUP_SKB ((struct sk_buff *) 1)
102#define DE_DUMMY_SKB ((struct sk_buff *) 2)
103#define DE_SETUP_FRAME_WORDS 96
104#define DE_EEPROM_WORDS 256
105#define DE_EEPROM_SIZE (DE_EEPROM_WORDS * sizeof(u16))
106#define DE_MAX_MEDIA 5
107
108#define DE_MEDIA_TP_AUTO 0
109#define DE_MEDIA_BNC 1
110#define DE_MEDIA_AUI 2
111#define DE_MEDIA_TP 3
112#define DE_MEDIA_TP_FD 4
113#define DE_MEDIA_INVALID DE_MAX_MEDIA
114#define DE_MEDIA_FIRST 0
115#define DE_MEDIA_LAST (DE_MAX_MEDIA - 1)
116#define DE_AUI_BNC (SUPPORTED_AUI | SUPPORTED_BNC)
117
118#define DE_TIMER_LINK (60 * HZ)
119#define DE_TIMER_NO_LINK (5 * HZ)
120
121#define DE_NUM_REGS 16
122#define DE_REGS_SIZE (DE_NUM_REGS * sizeof(u32))
123#define DE_REGS_VER 1
124
125/* Time in jiffies before concluding the transmitter is hung. */
126#define TX_TIMEOUT (6*HZ)
127
128#define DE_UNALIGNED_16(a) (u16)(get_unaligned((u16 *)(a)))
129
130/* This is a mysterious value that can be written to CSR11 in the 21040 (only)
131 to support a pre-NWay full-duplex signaling mechanism using short frames.
132 No one knows what it should be, but if left at its default value some
133 10base2(!) packets trigger a full-duplex-request interrupt. */
134#define FULL_DUPLEX_MAGIC 0x6969
135
136enum {
137 /* NIC registers */
138 BusMode = 0x00,
139 TxPoll = 0x08,
140 RxPoll = 0x10,
141 RxRingAddr = 0x18,
142 TxRingAddr = 0x20,
143 MacStatus = 0x28,
144 MacMode = 0x30,
145 IntrMask = 0x38,
146 RxMissed = 0x40,
147 ROMCmd = 0x48,
148 CSR11 = 0x58,
149 SIAStatus = 0x60,
150 CSR13 = 0x68,
151 CSR14 = 0x70,
152 CSR15 = 0x78,
153 PCIPM = 0x40,
154
155 /* BusMode bits */
156 CmdReset = (1 << 0),
157 CacheAlign16 = 0x00008000,
158 BurstLen4 = 0x00000400,
159
160 /* Rx/TxPoll bits */
161 NormalTxPoll = (1 << 0),
162 NormalRxPoll = (1 << 0),
163
164 /* Tx/Rx descriptor status bits */
165 DescOwn = (1 << 31),
166 RxError = (1 << 15),
167 RxErrLong = (1 << 7),
168 RxErrCRC = (1 << 1),
169 RxErrFIFO = (1 << 0),
170 RxErrRunt = (1 << 11),
171 RxErrFrame = (1 << 14),
172 RingEnd = (1 << 25),
173 FirstFrag = (1 << 29),
174 LastFrag = (1 << 30),
175 TxError = (1 << 15),
176 TxFIFOUnder = (1 << 1),
177 TxLinkFail = (1 << 2) | (1 << 10) | (1 << 11),
178 TxMaxCol = (1 << 8),
179 TxOWC = (1 << 9),
180 TxJabber = (1 << 14),
181 SetupFrame = (1 << 27),
182 TxSwInt = (1 << 31),
183
184 /* MacStatus bits */
185 IntrOK = (1 << 16),
186 IntrErr = (1 << 15),
187 RxIntr = (1 << 6),
188 RxEmpty = (1 << 7),
189 TxIntr = (1 << 0),
190 TxEmpty = (1 << 2),
191 PciErr = (1 << 13),
192 TxState = (1 << 22) | (1 << 21) | (1 << 20),
193 RxState = (1 << 19) | (1 << 18) | (1 << 17),
194 LinkFail = (1 << 12),
195 LinkPass = (1 << 4),
196 RxStopped = (1 << 8),
197 TxStopped = (1 << 1),
198
199 /* MacMode bits */
200 TxEnable = (1 << 13),
201 RxEnable = (1 << 1),
202 RxTx = TxEnable | RxEnable,
203 FullDuplex = (1 << 9),
204 AcceptAllMulticast = (1 << 7),
205 AcceptAllPhys = (1 << 6),
206 BOCnt = (1 << 5),
207 MacModeClear = (1<<12) | (1<<11) | (1<<10) | (1<<8) | (1<<3) |
208 RxTx | BOCnt | AcceptAllPhys | AcceptAllMulticast,
209
210 /* ROMCmd bits */
211 EE_SHIFT_CLK = 0x02, /* EEPROM shift clock. */
212 EE_CS = 0x01, /* EEPROM chip select. */
213 EE_DATA_WRITE = 0x04, /* Data from the Tulip to EEPROM. */
214 EE_WRITE_0 = 0x01,
215 EE_WRITE_1 = 0x05,
216 EE_DATA_READ = 0x08, /* Data from the EEPROM chip. */
217 EE_ENB = (0x4800 | EE_CS),
218
219 /* The EEPROM commands include the alway-set leading bit. */
220 EE_READ_CMD = 6,
221
222 /* RxMissed bits */
223 RxMissedOver = (1 << 16),
224 RxMissedMask = 0xffff,
225
226 /* SROM-related bits */
227 SROMC0InfoLeaf = 27,
228 MediaBlockMask = 0x3f,
229 MediaCustomCSRs = (1 << 6),
230
231 /* PCIPM bits */
232 PM_Sleep = (1 << 31),
233 PM_Snooze = (1 << 30),
234 PM_Mask = PM_Sleep | PM_Snooze,
235
236 /* SIAStatus bits */
237 NWayState = (1 << 14) | (1 << 13) | (1 << 12),
238 NWayRestart = (1 << 12),
239 NonselPortActive = (1 << 9),
240 LinkFailStatus = (1 << 2),
241 NetCxnErr = (1 << 1),
242};
243
244static const u32 de_intr_mask =
245 IntrOK | IntrErr | RxIntr | RxEmpty | TxIntr | TxEmpty |
246 LinkPass | LinkFail | PciErr;
247
248/*
249 * Set the programmable burst length to 4 longwords for all:
250 * DMA errors result without these values. Cache align 16 long.
251 */
252static const u32 de_bus_mode = CacheAlign16 | BurstLen4;
253
254struct de_srom_media_block {
255 u8 opts;
256 u16 csr13;
257 u16 csr14;
258 u16 csr15;
259} __attribute__((packed));
260
261struct de_srom_info_leaf {
262 u16 default_media;
263 u8 n_blocks;
264 u8 unused;
265} __attribute__((packed));
266
267struct de_desc {
268 u32 opts1;
269 u32 opts2;
270 u32 addr1;
271 u32 addr2;
272};
273
274struct media_info {
275 u16 type; /* DE_MEDIA_xxx */
276 u16 csr13;
277 u16 csr14;
278 u16 csr15;
279};
280
281struct ring_info {
282 struct sk_buff *skb;
283 dma_addr_t mapping;
284};
285
286struct de_private {
287 unsigned tx_head;
288 unsigned tx_tail;
289 unsigned rx_tail;
290
291 void __iomem *regs;
292 struct net_device *dev;
293 spinlock_t lock;
294
295 struct de_desc *rx_ring;
296 struct de_desc *tx_ring;
297 struct ring_info tx_skb[DE_TX_RING_SIZE];
298 struct ring_info rx_skb[DE_RX_RING_SIZE];
299 unsigned rx_buf_sz;
300 dma_addr_t ring_dma;
301
302 u32 msg_enable;
303
304 struct net_device_stats net_stats;
305
306 struct pci_dev *pdev;
307
308 u16 setup_frame[DE_SETUP_FRAME_WORDS];
309
310 u32 media_type;
311 u32 media_supported;
312 u32 media_advertise;
313 struct media_info media[DE_MAX_MEDIA];
314 struct timer_list media_timer;
315
316 u8 *ee_data;
317 unsigned board_idx;
318 unsigned de21040 : 1;
319 unsigned media_lock : 1;
320};
321
322
323static void de_set_rx_mode (struct net_device *dev);
324static void de_tx (struct de_private *de);
325static void de_clean_rings (struct de_private *de);
326static void de_media_interrupt (struct de_private *de, u32 status);
327static void de21040_media_timer (unsigned long data);
328static void de21041_media_timer (unsigned long data);
329static unsigned int de_ok_to_advertise (struct de_private *de, u32 new_media);
330
331
332static struct pci_device_id de_pci_tbl[] = {
333 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
335 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
337 { },
338};
339MODULE_DEVICE_TABLE(pci, de_pci_tbl);
340
341static const char * const media_name[DE_MAX_MEDIA] = {
342 "10baseT auto",
343 "BNC",
344 "AUI",
345 "10baseT-HD",
346 "10baseT-FD"
347};
348
349/* 21040 transceiver register settings:
350 * TP AUTO(unused), BNC(unused), AUI, TP, TP FD*/
351static u16 t21040_csr13[] = { 0, 0, 0x8F09, 0x8F01, 0x8F01, };
352static u16 t21040_csr14[] = { 0, 0, 0x0705, 0xFFFF, 0xFFFD, };
353static u16 t21040_csr15[] = { 0, 0, 0x0006, 0x0000, 0x0000, };
354
355/* 21041 transceiver register settings: TP AUTO, BNC, AUI, TP, TP FD*/
356static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
357static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x6F3F, 0x6F3D, };
358static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
359
360
361#define dr32(reg) readl(de->regs + (reg))
362#define dw32(reg,val) writel((val), de->regs + (reg))
363
364
365static void de_rx_err_acct (struct de_private *de, unsigned rx_tail,
366 u32 status, u32 len)
367{
368 if (netif_msg_rx_err (de))
369 printk (KERN_DEBUG
370 "%s: rx err, slot %d status 0x%x len %d\n",
371 de->dev->name, rx_tail, status, len);
372
373 if ((status & 0x38000300) != 0x0300) {
374 /* Ingore earlier buffers. */
375 if ((status & 0xffff) != 0x7fff) {
376 if (netif_msg_rx_err(de))
377 printk(KERN_WARNING "%s: Oversized Ethernet frame "
378 "spanned multiple buffers, status %8.8x!\n",
379 de->dev->name, status);
380 de->net_stats.rx_length_errors++;
381 }
382 } else if (status & RxError) {
383 /* There was a fatal error. */
384 de->net_stats.rx_errors++; /* end of a packet.*/
385 if (status & 0x0890) de->net_stats.rx_length_errors++;
386 if (status & RxErrCRC) de->net_stats.rx_crc_errors++;
387 if (status & RxErrFIFO) de->net_stats.rx_fifo_errors++;
388 }
389}
390
391static void de_rx (struct de_private *de)
392{
393 unsigned rx_tail = de->rx_tail;
394 unsigned rx_work = DE_RX_RING_SIZE;
395 unsigned drop = 0;
396 int rc;
397
398 while (rx_work--) {
399 u32 status, len;
400 dma_addr_t mapping;
401 struct sk_buff *skb, *copy_skb;
402 unsigned copying_skb, buflen;
403
404 skb = de->rx_skb[rx_tail].skb;
405 if (!skb)
406 BUG();
407 rmb();
408 status = le32_to_cpu(de->rx_ring[rx_tail].opts1);
409 if (status & DescOwn)
410 break;
411
412 len = ((status >> 16) & 0x7ff) - 4;
413 mapping = de->rx_skb[rx_tail].mapping;
414
415 if (unlikely(drop)) {
416 de->net_stats.rx_dropped++;
417 goto rx_next;
418 }
419
420 if (unlikely((status & 0x38008300) != 0x0300)) {
421 de_rx_err_acct(de, rx_tail, status, len);
422 goto rx_next;
423 }
424
425 copying_skb = (len <= rx_copybreak);
426
427 if (unlikely(netif_msg_rx_status(de)))
428 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d copying? %d\n",
429 de->dev->name, rx_tail, status, len,
430 copying_skb);
431
432 buflen = copying_skb ? (len + RX_OFFSET) : de->rx_buf_sz;
433 copy_skb = dev_alloc_skb (buflen);
434 if (unlikely(!copy_skb)) {
435 de->net_stats.rx_dropped++;
436 drop = 1;
437 rx_work = 100;
438 goto rx_next;
439 }
440 copy_skb->dev = de->dev;
441
442 if (!copying_skb) {
443 pci_unmap_single(de->pdev, mapping,
444 buflen, PCI_DMA_FROMDEVICE);
445 skb_put(skb, len);
446
447 mapping =
448 de->rx_skb[rx_tail].mapping =
449 pci_map_single(de->pdev, copy_skb->tail,
450 buflen, PCI_DMA_FROMDEVICE);
451 de->rx_skb[rx_tail].skb = copy_skb;
452 } else {
453 pci_dma_sync_single_for_cpu(de->pdev, mapping, len, PCI_DMA_FROMDEVICE);
454 skb_reserve(copy_skb, RX_OFFSET);
455 memcpy(skb_put(copy_skb, len), skb->tail, len);
456
457 pci_dma_sync_single_for_device(de->pdev, mapping, len, PCI_DMA_FROMDEVICE);
458
459 /* We'll reuse the original ring buffer. */
460 skb = copy_skb;
461 }
462
463 skb->protocol = eth_type_trans (skb, de->dev);
464
465 de->net_stats.rx_packets++;
466 de->net_stats.rx_bytes += skb->len;
467 de->dev->last_rx = jiffies;
468 rc = netif_rx (skb);
469 if (rc == NET_RX_DROP)
470 drop = 1;
471
472rx_next:
473 de->rx_ring[rx_tail].opts1 = cpu_to_le32(DescOwn);
474 if (rx_tail == (DE_RX_RING_SIZE - 1))
475 de->rx_ring[rx_tail].opts2 =
476 cpu_to_le32(RingEnd | de->rx_buf_sz);
477 else
478 de->rx_ring[rx_tail].opts2 = cpu_to_le32(de->rx_buf_sz);
479 de->rx_ring[rx_tail].addr1 = cpu_to_le32(mapping);
480 rx_tail = NEXT_RX(rx_tail);
481 }
482
483 if (!rx_work)
484 printk(KERN_WARNING "%s: rx work limit reached\n", de->dev->name);
485
486 de->rx_tail = rx_tail;
487}
488
489static irqreturn_t de_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
490{
491 struct net_device *dev = dev_instance;
492 struct de_private *de = dev->priv;
493 u32 status;
494
495 status = dr32(MacStatus);
496 if ((!(status & (IntrOK|IntrErr))) || (status == 0xFFFF))
497 return IRQ_NONE;
498
499 if (netif_msg_intr(de))
500 printk(KERN_DEBUG "%s: intr, status %08x mode %08x desc %u/%u/%u\n",
501 dev->name, status, dr32(MacMode), de->rx_tail, de->tx_head, de->tx_tail);
502
503 dw32(MacStatus, status);
504
505 if (status & (RxIntr | RxEmpty)) {
506 de_rx(de);
507 if (status & RxEmpty)
508 dw32(RxPoll, NormalRxPoll);
509 }
510
511 spin_lock(&de->lock);
512
513 if (status & (TxIntr | TxEmpty))
514 de_tx(de);
515
516 if (status & (LinkPass | LinkFail))
517 de_media_interrupt(de, status);
518
519 spin_unlock(&de->lock);
520
521 if (status & PciErr) {
522 u16 pci_status;
523
524 pci_read_config_word(de->pdev, PCI_STATUS, &pci_status);
525 pci_write_config_word(de->pdev, PCI_STATUS, pci_status);
526 printk(KERN_ERR "%s: PCI bus error, status=%08x, PCI status=%04x\n",
527 dev->name, status, pci_status);
528 }
529
530 return IRQ_HANDLED;
531}
532
533static void de_tx (struct de_private *de)
534{
535 unsigned tx_head = de->tx_head;
536 unsigned tx_tail = de->tx_tail;
537
538 while (tx_tail != tx_head) {
539 struct sk_buff *skb;
540 u32 status;
541
542 rmb();
543 status = le32_to_cpu(de->tx_ring[tx_tail].opts1);
544 if (status & DescOwn)
545 break;
546
547 skb = de->tx_skb[tx_tail].skb;
548 if (!skb)
549 BUG();
550 if (unlikely(skb == DE_DUMMY_SKB))
551 goto next;
552
553 if (unlikely(skb == DE_SETUP_SKB)) {
554 pci_unmap_single(de->pdev, de->tx_skb[tx_tail].mapping,
555 sizeof(de->setup_frame), PCI_DMA_TODEVICE);
556 goto next;
557 }
558
559 pci_unmap_single(de->pdev, de->tx_skb[tx_tail].mapping,
560 skb->len, PCI_DMA_TODEVICE);
561
562 if (status & LastFrag) {
563 if (status & TxError) {
564 if (netif_msg_tx_err(de))
565 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
566 de->dev->name, status);
567 de->net_stats.tx_errors++;
568 if (status & TxOWC)
569 de->net_stats.tx_window_errors++;
570 if (status & TxMaxCol)
571 de->net_stats.tx_aborted_errors++;
572 if (status & TxLinkFail)
573 de->net_stats.tx_carrier_errors++;
574 if (status & TxFIFOUnder)
575 de->net_stats.tx_fifo_errors++;
576 } else {
577 de->net_stats.tx_packets++;
578 de->net_stats.tx_bytes += skb->len;
579 if (netif_msg_tx_done(de))
580 printk(KERN_DEBUG "%s: tx done, slot %d\n", de->dev->name, tx_tail);
581 }
582 dev_kfree_skb_irq(skb);
583 }
584
585next:
586 de->tx_skb[tx_tail].skb = NULL;
587
588 tx_tail = NEXT_TX(tx_tail);
589 }
590
591 de->tx_tail = tx_tail;
592
593 if (netif_queue_stopped(de->dev) && (TX_BUFFS_AVAIL(de) > (DE_TX_RING_SIZE / 4)))
594 netif_wake_queue(de->dev);
595}
596
597static int de_start_xmit (struct sk_buff *skb, struct net_device *dev)
598{
599 struct de_private *de = dev->priv;
600 unsigned int entry, tx_free;
601 u32 mapping, len, flags = FirstFrag | LastFrag;
602 struct de_desc *txd;
603
604 spin_lock_irq(&de->lock);
605
606 tx_free = TX_BUFFS_AVAIL(de);
607 if (tx_free == 0) {
608 netif_stop_queue(dev);
609 spin_unlock_irq(&de->lock);
610 return 1;
611 }
612 tx_free--;
613
614 entry = de->tx_head;
615
616 txd = &de->tx_ring[entry];
617
618 len = skb->len;
619 mapping = pci_map_single(de->pdev, skb->data, len, PCI_DMA_TODEVICE);
620 if (entry == (DE_TX_RING_SIZE - 1))
621 flags |= RingEnd;
622 if (!tx_free || (tx_free == (DE_TX_RING_SIZE / 2)))
623 flags |= TxSwInt;
624 flags |= len;
625 txd->opts2 = cpu_to_le32(flags);
626 txd->addr1 = cpu_to_le32(mapping);
627
628 de->tx_skb[entry].skb = skb;
629 de->tx_skb[entry].mapping = mapping;
630 wmb();
631
632 txd->opts1 = cpu_to_le32(DescOwn);
633 wmb();
634
635 de->tx_head = NEXT_TX(entry);
636 if (netif_msg_tx_queued(de))
637 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
638 dev->name, entry, skb->len);
639
640 if (tx_free == 0)
641 netif_stop_queue(dev);
642
643 spin_unlock_irq(&de->lock);
644
645 /* Trigger an immediate transmit demand. */
646 dw32(TxPoll, NormalTxPoll);
647 dev->trans_start = jiffies;
648
649 return 0;
650}
651
652/* Set or clear the multicast filter for this adaptor.
653 Note that we only use exclusion around actually queueing the
654 new frame, not around filling de->setup_frame. This is non-deterministic
655 when re-entered but still correct. */
656
657#undef set_bit_le
658#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
659
660static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
661{
662 struct de_private *de = dev->priv;
663 u16 hash_table[32];
664 struct dev_mc_list *mclist;
665 int i;
666 u16 *eaddrs;
667
668 memset(hash_table, 0, sizeof(hash_table));
669 set_bit_le(255, hash_table); /* Broadcast entry */
670 /* This should work on big-endian machines as well. */
671 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
672 i++, mclist = mclist->next) {
673 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
674
675 set_bit_le(index, hash_table);
676
677 for (i = 0; i < 32; i++) {
678 *setup_frm++ = hash_table[i];
679 *setup_frm++ = hash_table[i];
680 }
681 setup_frm = &de->setup_frame[13*6];
682 }
683
684 /* Fill the final entry with our physical address. */
685 eaddrs = (u16 *)dev->dev_addr;
686 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
687 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
688 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
689}
690
691static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
692{
693 struct de_private *de = dev->priv;
694 struct dev_mc_list *mclist;
695 int i;
696 u16 *eaddrs;
697
698 /* We have <= 14 addresses so we can use the wonderful
699 16 address perfect filtering of the Tulip. */
700 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
701 i++, mclist = mclist->next) {
702 eaddrs = (u16 *)mclist->dmi_addr;
703 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
704 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
705 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
706 }
707 /* Fill the unused entries with the broadcast address. */
708 memset(setup_frm, 0xff, (15-i)*12);
709 setup_frm = &de->setup_frame[15*6];
710
711 /* Fill the final entry with our physical address. */
712 eaddrs = (u16 *)dev->dev_addr;
713 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
714 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
715 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
716}
717
718
719static void __de_set_rx_mode (struct net_device *dev)
720{
721 struct de_private *de = dev->priv;
722 u32 macmode;
723 unsigned int entry;
724 u32 mapping;
725 struct de_desc *txd;
726 struct de_desc *dummy_txd = NULL;
727
728 macmode = dr32(MacMode) & ~(AcceptAllMulticast | AcceptAllPhys);
729
730 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
731 macmode |= AcceptAllMulticast | AcceptAllPhys;
732 goto out;
733 }
734
735 if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
736 /* Too many to filter well -- accept all multicasts. */
737 macmode |= AcceptAllMulticast;
738 goto out;
739 }
740
741 /* Note that only the low-address shortword of setup_frame is valid!
742 The values are doubled for big-endian architectures. */
743 if (dev->mc_count > 14) /* Must use a multicast hash table. */
744 build_setup_frame_hash (de->setup_frame, dev);
745 else
746 build_setup_frame_perfect (de->setup_frame, dev);
747
748 /*
749 * Now add this frame to the Tx list.
750 */
751
752 entry = de->tx_head;
753
754 /* Avoid a chip errata by prefixing a dummy entry. */
755 if (entry != 0) {
756 de->tx_skb[entry].skb = DE_DUMMY_SKB;
757
758 dummy_txd = &de->tx_ring[entry];
759 dummy_txd->opts2 = (entry == (DE_TX_RING_SIZE - 1)) ?
760 cpu_to_le32(RingEnd) : 0;
761 dummy_txd->addr1 = 0;
762
763 /* Must set DescOwned later to avoid race with chip */
764
765 entry = NEXT_TX(entry);
766 }
767
768 de->tx_skb[entry].skb = DE_SETUP_SKB;
769 de->tx_skb[entry].mapping = mapping =
770 pci_map_single (de->pdev, de->setup_frame,
771 sizeof (de->setup_frame), PCI_DMA_TODEVICE);
772
773 /* Put the setup frame on the Tx list. */
774 txd = &de->tx_ring[entry];
775 if (entry == (DE_TX_RING_SIZE - 1))
776 txd->opts2 = cpu_to_le32(SetupFrame | RingEnd | sizeof (de->setup_frame));
777 else
778 txd->opts2 = cpu_to_le32(SetupFrame | sizeof (de->setup_frame));
779 txd->addr1 = cpu_to_le32(mapping);
780 wmb();
781
782 txd->opts1 = cpu_to_le32(DescOwn);
783 wmb();
784
785 if (dummy_txd) {
786 dummy_txd->opts1 = cpu_to_le32(DescOwn);
787 wmb();
788 }
789
790 de->tx_head = NEXT_TX(entry);
791
792 if (TX_BUFFS_AVAIL(de) < 0)
793 BUG();
794 if (TX_BUFFS_AVAIL(de) == 0)
795 netif_stop_queue(dev);
796
797 /* Trigger an immediate transmit demand. */
798 dw32(TxPoll, NormalTxPoll);
799
800out:
801 if (macmode != dr32(MacMode))
802 dw32(MacMode, macmode);
803}
804
805static void de_set_rx_mode (struct net_device *dev)
806{
807 unsigned long flags;
808 struct de_private *de = dev->priv;
809
810 spin_lock_irqsave (&de->lock, flags);
811 __de_set_rx_mode(dev);
812 spin_unlock_irqrestore (&de->lock, flags);
813}
814
815static inline void de_rx_missed(struct de_private *de, u32 rx_missed)
816{
817 if (unlikely(rx_missed & RxMissedOver))
818 de->net_stats.rx_missed_errors += RxMissedMask;
819 else
820 de->net_stats.rx_missed_errors += (rx_missed & RxMissedMask);
821}
822
823static void __de_get_stats(struct de_private *de)
824{
825 u32 tmp = dr32(RxMissed); /* self-clearing */
826
827 de_rx_missed(de, tmp);
828}
829
830static struct net_device_stats *de_get_stats(struct net_device *dev)
831{
832 struct de_private *de = dev->priv;
833
834 /* The chip only need report frame silently dropped. */
835 spin_lock_irq(&de->lock);
836 if (netif_running(dev) && netif_device_present(dev))
837 __de_get_stats(de);
838 spin_unlock_irq(&de->lock);
839
840 return &de->net_stats;
841}
842
843static inline int de_is_running (struct de_private *de)
844{
845 return (dr32(MacStatus) & (RxState | TxState)) ? 1 : 0;
846}
847
848static void de_stop_rxtx (struct de_private *de)
849{
850 u32 macmode;
851 unsigned int work = 1000;
852
853 macmode = dr32(MacMode);
854 if (macmode & RxTx) {
855 dw32(MacMode, macmode & ~RxTx);
856 dr32(MacMode);
857 }
858
859 while (--work > 0) {
860 if (!de_is_running(de))
861 return;
862 cpu_relax();
863 }
864
865 printk(KERN_WARNING "%s: timeout expired stopping DMA\n", de->dev->name);
866}
867
868static inline void de_start_rxtx (struct de_private *de)
869{
870 u32 macmode;
871
872 macmode = dr32(MacMode);
873 if ((macmode & RxTx) != RxTx) {
874 dw32(MacMode, macmode | RxTx);
875 dr32(MacMode);
876 }
877}
878
879static void de_stop_hw (struct de_private *de)
880{
881
882 udelay(5);
883 dw32(IntrMask, 0);
884
885 de_stop_rxtx(de);
886
887 dw32(MacStatus, dr32(MacStatus));
888
889 udelay(10);
890
891 de->rx_tail = 0;
892 de->tx_head = de->tx_tail = 0;
893}
894
895static void de_link_up(struct de_private *de)
896{
897 if (!netif_carrier_ok(de->dev)) {
898 netif_carrier_on(de->dev);
899 if (netif_msg_link(de))
900 printk(KERN_INFO "%s: link up, media %s\n",
901 de->dev->name, media_name[de->media_type]);
902 }
903}
904
905static void de_link_down(struct de_private *de)
906{
907 if (netif_carrier_ok(de->dev)) {
908 netif_carrier_off(de->dev);
909 if (netif_msg_link(de))
910 printk(KERN_INFO "%s: link down\n", de->dev->name);
911 }
912}
913
914static void de_set_media (struct de_private *de)
915{
916 unsigned media = de->media_type;
917 u32 macmode = dr32(MacMode);
918
919 if (de_is_running(de))
920 BUG();
921
922 if (de->de21040)
923 dw32(CSR11, FULL_DUPLEX_MAGIC);
924 dw32(CSR13, 0); /* Reset phy */
925 dw32(CSR14, de->media[media].csr14);
926 dw32(CSR15, de->media[media].csr15);
927 dw32(CSR13, de->media[media].csr13);
928
929 /* must delay 10ms before writing to other registers,
930 * especially CSR6
931 */
932 mdelay(10);
933
934 if (media == DE_MEDIA_TP_FD)
935 macmode |= FullDuplex;
936 else
937 macmode &= ~FullDuplex;
938
939 if (netif_msg_link(de)) {
940 printk(KERN_INFO "%s: set link %s\n"
941 KERN_INFO "%s: mode 0x%x, sia 0x%x,0x%x,0x%x,0x%x\n"
942 KERN_INFO "%s: set mode 0x%x, set sia 0x%x,0x%x,0x%x\n",
943 de->dev->name, media_name[media],
944 de->dev->name, dr32(MacMode), dr32(SIAStatus),
945 dr32(CSR13), dr32(CSR14), dr32(CSR15),
946 de->dev->name, macmode, de->media[media].csr13,
947 de->media[media].csr14, de->media[media].csr15);
948 }
949 if (macmode != dr32(MacMode))
950 dw32(MacMode, macmode);
951}
952
953static void de_next_media (struct de_private *de, u32 *media,
954 unsigned int n_media)
955{
956 unsigned int i;
957
958 for (i = 0; i < n_media; i++) {
959 if (de_ok_to_advertise(de, media[i])) {
960 de->media_type = media[i];
961 return;
962 }
963 }
964}
965
966static void de21040_media_timer (unsigned long data)
967{
968 struct de_private *de = (struct de_private *) data;
969 struct net_device *dev = de->dev;
970 u32 status = dr32(SIAStatus);
971 unsigned int carrier;
972 unsigned long flags;
973
974 carrier = (status & NetCxnErr) ? 0 : 1;
975
976 if (carrier) {
977 if (de->media_type != DE_MEDIA_AUI && (status & LinkFailStatus))
978 goto no_link_yet;
979
980 de->media_timer.expires = jiffies + DE_TIMER_LINK;
981 add_timer(&de->media_timer);
982 if (!netif_carrier_ok(dev))
983 de_link_up(de);
984 else
985 if (netif_msg_timer(de))
986 printk(KERN_INFO "%s: %s link ok, status %x\n",
987 dev->name, media_name[de->media_type],
988 status);
989 return;
990 }
991
992 de_link_down(de);
993
994 if (de->media_lock)
995 return;
996
997 if (de->media_type == DE_MEDIA_AUI) {
998 u32 next_state = DE_MEDIA_TP;
999 de_next_media(de, &next_state, 1);
1000 } else {
1001 u32 next_state = DE_MEDIA_AUI;
1002 de_next_media(de, &next_state, 1);
1003 }
1004
1005 spin_lock_irqsave(&de->lock, flags);
1006 de_stop_rxtx(de);
1007 spin_unlock_irqrestore(&de->lock, flags);
1008 de_set_media(de);
1009 de_start_rxtx(de);
1010
1011no_link_yet:
1012 de->media_timer.expires = jiffies + DE_TIMER_NO_LINK;
1013 add_timer(&de->media_timer);
1014
1015 if (netif_msg_timer(de))
1016 printk(KERN_INFO "%s: no link, trying media %s, status %x\n",
1017 dev->name, media_name[de->media_type], status);
1018}
1019
1020static unsigned int de_ok_to_advertise (struct de_private *de, u32 new_media)
1021{
1022 switch (new_media) {
1023 case DE_MEDIA_TP_AUTO:
1024 if (!(de->media_advertise & ADVERTISED_Autoneg))
1025 return 0;
1026 if (!(de->media_advertise & (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full)))
1027 return 0;
1028 break;
1029 case DE_MEDIA_BNC:
1030 if (!(de->media_advertise & ADVERTISED_BNC))
1031 return 0;
1032 break;
1033 case DE_MEDIA_AUI:
1034 if (!(de->media_advertise & ADVERTISED_AUI))
1035 return 0;
1036 break;
1037 case DE_MEDIA_TP:
1038 if (!(de->media_advertise & ADVERTISED_10baseT_Half))
1039 return 0;
1040 break;
1041 case DE_MEDIA_TP_FD:
1042 if (!(de->media_advertise & ADVERTISED_10baseT_Full))
1043 return 0;
1044 break;
1045 }
1046
1047 return 1;
1048}
1049
1050static void de21041_media_timer (unsigned long data)
1051{
1052 struct de_private *de = (struct de_private *) data;
1053 struct net_device *dev = de->dev;
1054 u32 status = dr32(SIAStatus);
1055 unsigned int carrier;
1056 unsigned long flags;
1057
1058 carrier = (status & NetCxnErr) ? 0 : 1;
1059
1060 if (carrier) {
1061 if ((de->media_type == DE_MEDIA_TP_AUTO ||
1062 de->media_type == DE_MEDIA_TP ||
1063 de->media_type == DE_MEDIA_TP_FD) &&
1064 (status & LinkFailStatus))
1065 goto no_link_yet;
1066
1067 de->media_timer.expires = jiffies + DE_TIMER_LINK;
1068 add_timer(&de->media_timer);
1069 if (!netif_carrier_ok(dev))
1070 de_link_up(de);
1071 else
1072 if (netif_msg_timer(de))
1073 printk(KERN_INFO "%s: %s link ok, mode %x status %x\n",
1074 dev->name, media_name[de->media_type],
1075 dr32(MacMode), status);
1076 return;
1077 }
1078
1079 de_link_down(de);
1080
1081 /* if media type locked, don't switch media */
1082 if (de->media_lock)
1083 goto set_media;
1084
1085 /* if activity detected, use that as hint for new media type */
1086 if (status & NonselPortActive) {
1087 unsigned int have_media = 1;
1088
1089 /* if AUI/BNC selected, then activity is on TP port */
1090 if (de->media_type == DE_MEDIA_AUI ||
1091 de->media_type == DE_MEDIA_BNC) {
1092 if (de_ok_to_advertise(de, DE_MEDIA_TP_AUTO))
1093 de->media_type = DE_MEDIA_TP_AUTO;
1094 else
1095 have_media = 0;
1096 }
1097
1098 /* TP selected. If there is only TP and BNC, then it's BNC */
1099 else if (((de->media_supported & DE_AUI_BNC) == SUPPORTED_BNC) &&
1100 de_ok_to_advertise(de, DE_MEDIA_BNC))
1101 de->media_type = DE_MEDIA_BNC;
1102
1103 /* TP selected. If there is only TP and AUI, then it's AUI */
1104 else if (((de->media_supported & DE_AUI_BNC) == SUPPORTED_AUI) &&
1105 de_ok_to_advertise(de, DE_MEDIA_AUI))
1106 de->media_type = DE_MEDIA_AUI;
1107
1108 /* otherwise, ignore the hint */
1109 else
1110 have_media = 0;
1111
1112 if (have_media)
1113 goto set_media;
1114 }
1115
1116 /*
1117 * Absent or ambiguous activity hint, move to next advertised
1118 * media state. If de->media_type is left unchanged, this
1119 * simply resets the PHY and reloads the current media settings.
1120 */
1121 if (de->media_type == DE_MEDIA_AUI) {
1122 u32 next_states[] = { DE_MEDIA_BNC, DE_MEDIA_TP_AUTO };
1123 de_next_media(de, next_states, ARRAY_SIZE(next_states));
1124 } else if (de->media_type == DE_MEDIA_BNC) {
1125 u32 next_states[] = { DE_MEDIA_TP_AUTO, DE_MEDIA_AUI };
1126 de_next_media(de, next_states, ARRAY_SIZE(next_states));
1127 } else {
1128 u32 next_states[] = { DE_MEDIA_AUI, DE_MEDIA_BNC, DE_MEDIA_TP_AUTO };
1129 de_next_media(de, next_states, ARRAY_SIZE(next_states));
1130 }
1131
1132set_media:
1133 spin_lock_irqsave(&de->lock, flags);
1134 de_stop_rxtx(de);
1135 spin_unlock_irqrestore(&de->lock, flags);
1136 de_set_media(de);
1137 de_start_rxtx(de);
1138
1139no_link_yet:
1140 de->media_timer.expires = jiffies + DE_TIMER_NO_LINK;
1141 add_timer(&de->media_timer);
1142
1143 if (netif_msg_timer(de))
1144 printk(KERN_INFO "%s: no link, trying media %s, status %x\n",
1145 dev->name, media_name[de->media_type], status);
1146}
1147
1148static void de_media_interrupt (struct de_private *de, u32 status)
1149{
1150 if (status & LinkPass) {
1151 de_link_up(de);
1152 mod_timer(&de->media_timer, jiffies + DE_TIMER_LINK);
1153 return;
1154 }
1155
1156 if (!(status & LinkFail))
1157 BUG();
1158
1159 if (netif_carrier_ok(de->dev)) {
1160 de_link_down(de);
1161 mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
1162 }
1163}
1164
1165static int de_reset_mac (struct de_private *de)
1166{
1167 u32 status, tmp;
1168
1169 /*
1170 * Reset MAC. de4x5.c and tulip.c examined for "advice"
1171 * in this area.
1172 */
1173
1174 if (dr32(BusMode) == 0xffffffff)
1175 return -EBUSY;
1176
1177 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
1178 dw32 (BusMode, CmdReset);
1179 mdelay (1);
1180
1181 dw32 (BusMode, de_bus_mode);
1182 mdelay (1);
1183
1184 for (tmp = 0; tmp < 5; tmp++) {
1185 dr32 (BusMode);
1186 mdelay (1);
1187 }
1188
1189 mdelay (1);
1190
1191 status = dr32(MacStatus);
1192 if (status & (RxState | TxState))
1193 return -EBUSY;
1194 if (status == 0xffffffff)
1195 return -ENODEV;
1196 return 0;
1197}
1198
1199static void de_adapter_wake (struct de_private *de)
1200{
1201 u32 pmctl;
1202
1203 if (de->de21040)
1204 return;
1205
1206 pci_read_config_dword(de->pdev, PCIPM, &pmctl);
1207 if (pmctl & PM_Mask) {
1208 pmctl &= ~PM_Mask;
1209 pci_write_config_dword(de->pdev, PCIPM, pmctl);
1210
1211 /* de4x5.c delays, so we do too */
1212 msleep(10);
1213 }
1214}
1215
1216static void de_adapter_sleep (struct de_private *de)
1217{
1218 u32 pmctl;
1219
1220 if (de->de21040)
1221 return;
1222
1223 pci_read_config_dword(de->pdev, PCIPM, &pmctl);
1224 pmctl |= PM_Sleep;
1225 pci_write_config_dword(de->pdev, PCIPM, pmctl);
1226}
1227
1228static int de_init_hw (struct de_private *de)
1229{
1230 struct net_device *dev = de->dev;
1231 u32 macmode;
1232 int rc;
1233
1234 de_adapter_wake(de);
1235
1236 macmode = dr32(MacMode) & ~MacModeClear;
1237
1238 rc = de_reset_mac(de);
1239 if (rc)
1240 return rc;
1241
1242 de_set_media(de); /* reset phy */
1243
1244 dw32(RxRingAddr, de->ring_dma);
1245 dw32(TxRingAddr, de->ring_dma + (sizeof(struct de_desc) * DE_RX_RING_SIZE));
1246
1247 dw32(MacMode, RxTx | macmode);
1248
1249 dr32(RxMissed); /* self-clearing */
1250
1251 dw32(IntrMask, de_intr_mask);
1252
1253 de_set_rx_mode(dev);
1254
1255 return 0;
1256}
1257
1258static int de_refill_rx (struct de_private *de)
1259{
1260 unsigned i;
1261
1262 for (i = 0; i < DE_RX_RING_SIZE; i++) {
1263 struct sk_buff *skb;
1264
1265 skb = dev_alloc_skb(de->rx_buf_sz);
1266 if (!skb)
1267 goto err_out;
1268
1269 skb->dev = de->dev;
1270
1271 de->rx_skb[i].mapping = pci_map_single(de->pdev,
1272 skb->tail, de->rx_buf_sz, PCI_DMA_FROMDEVICE);
1273 de->rx_skb[i].skb = skb;
1274
1275 de->rx_ring[i].opts1 = cpu_to_le32(DescOwn);
1276 if (i == (DE_RX_RING_SIZE - 1))
1277 de->rx_ring[i].opts2 =
1278 cpu_to_le32(RingEnd | de->rx_buf_sz);
1279 else
1280 de->rx_ring[i].opts2 = cpu_to_le32(de->rx_buf_sz);
1281 de->rx_ring[i].addr1 = cpu_to_le32(de->rx_skb[i].mapping);
1282 de->rx_ring[i].addr2 = 0;
1283 }
1284
1285 return 0;
1286
1287err_out:
1288 de_clean_rings(de);
1289 return -ENOMEM;
1290}
1291
1292static int de_init_rings (struct de_private *de)
1293{
1294 memset(de->tx_ring, 0, sizeof(struct de_desc) * DE_TX_RING_SIZE);
1295 de->tx_ring[DE_TX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
1296
1297 de->rx_tail = 0;
1298 de->tx_head = de->tx_tail = 0;
1299
1300 return de_refill_rx (de);
1301}
1302
1303static int de_alloc_rings (struct de_private *de)
1304{
1305 de->rx_ring = pci_alloc_consistent(de->pdev, DE_RING_BYTES, &de->ring_dma);
1306 if (!de->rx_ring)
1307 return -ENOMEM;
1308 de->tx_ring = &de->rx_ring[DE_RX_RING_SIZE];
1309 return de_init_rings(de);
1310}
1311
1312static void de_clean_rings (struct de_private *de)
1313{
1314 unsigned i;
1315
1316 memset(de->rx_ring, 0, sizeof(struct de_desc) * DE_RX_RING_SIZE);
1317 de->rx_ring[DE_RX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
1318 wmb();
1319 memset(de->tx_ring, 0, sizeof(struct de_desc) * DE_TX_RING_SIZE);
1320 de->tx_ring[DE_TX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
1321 wmb();
1322
1323 for (i = 0; i < DE_RX_RING_SIZE; i++) {
1324 if (de->rx_skb[i].skb) {
1325 pci_unmap_single(de->pdev, de->rx_skb[i].mapping,
1326 de->rx_buf_sz, PCI_DMA_FROMDEVICE);
1327 dev_kfree_skb(de->rx_skb[i].skb);
1328 }
1329 }
1330
1331 for (i = 0; i < DE_TX_RING_SIZE; i++) {
1332 struct sk_buff *skb = de->tx_skb[i].skb;
1333 if ((skb) && (skb != DE_DUMMY_SKB)) {
1334 if (skb != DE_SETUP_SKB) {
1335 dev_kfree_skb(skb);
1336 de->net_stats.tx_dropped++;
1337 pci_unmap_single(de->pdev,
1338 de->tx_skb[i].mapping,
1339 skb->len, PCI_DMA_TODEVICE);
1340 } else {
1341 pci_unmap_single(de->pdev,
1342 de->tx_skb[i].mapping,
1343 sizeof(de->setup_frame),
1344 PCI_DMA_TODEVICE);
1345 }
1346 }
1347 }
1348
1349 memset(&de->rx_skb, 0, sizeof(struct ring_info) * DE_RX_RING_SIZE);
1350 memset(&de->tx_skb, 0, sizeof(struct ring_info) * DE_TX_RING_SIZE);
1351}
1352
1353static void de_free_rings (struct de_private *de)
1354{
1355 de_clean_rings(de);
1356 pci_free_consistent(de->pdev, DE_RING_BYTES, de->rx_ring, de->ring_dma);
1357 de->rx_ring = NULL;
1358 de->tx_ring = NULL;
1359}
1360
1361static int de_open (struct net_device *dev)
1362{
1363 struct de_private *de = dev->priv;
1364 int rc;
1365 unsigned long flags;
1366
1367 if (netif_msg_ifup(de))
1368 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1369
1370 de->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1371
1372 rc = de_alloc_rings(de);
1373 if (rc) {
1374 printk(KERN_ERR "%s: ring allocation failure, err=%d\n",
1375 dev->name, rc);
1376 return rc;
1377 }
1378
1379 rc = de_init_hw(de);
1380 if (rc) {
1381 printk(KERN_ERR "%s: h/w init failure, err=%d\n",
1382 dev->name, rc);
1383 goto err_out_free;
1384 }
1385
1386 rc = request_irq(dev->irq, de_interrupt, SA_SHIRQ, dev->name, dev);
1387 if (rc) {
1388 printk(KERN_ERR "%s: IRQ %d request failure, err=%d\n",
1389 dev->name, dev->irq, rc);
1390 goto err_out_hw;
1391 }
1392
1393 netif_start_queue(dev);
1394 mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
1395
1396 return 0;
1397
1398err_out_hw:
1399 spin_lock_irqsave(&de->lock, flags);
1400 de_stop_hw(de);
1401 spin_unlock_irqrestore(&de->lock, flags);
1402
1403err_out_free:
1404 de_free_rings(de);
1405 return rc;
1406}
1407
1408static int de_close (struct net_device *dev)
1409{
1410 struct de_private *de = dev->priv;
1411 unsigned long flags;
1412
1413 if (netif_msg_ifdown(de))
1414 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1415
1416 del_timer_sync(&de->media_timer);
1417
1418 spin_lock_irqsave(&de->lock, flags);
1419 de_stop_hw(de);
1420 netif_stop_queue(dev);
1421 netif_carrier_off(dev);
1422 spin_unlock_irqrestore(&de->lock, flags);
1423
1424 free_irq(dev->irq, dev);
1425
1426 de_free_rings(de);
1427 de_adapter_sleep(de);
1428 pci_disable_device(de->pdev);
1429 return 0;
1430}
1431
1432static void de_tx_timeout (struct net_device *dev)
1433{
1434 struct de_private *de = dev->priv;
1435
1436 printk(KERN_DEBUG "%s: NIC status %08x mode %08x sia %08x desc %u/%u/%u\n",
1437 dev->name, dr32(MacStatus), dr32(MacMode), dr32(SIAStatus),
1438 de->rx_tail, de->tx_head, de->tx_tail);
1439
1440 del_timer_sync(&de->media_timer);
1441
1442 disable_irq(dev->irq);
1443 spin_lock_irq(&de->lock);
1444
1445 de_stop_hw(de);
1446 netif_stop_queue(dev);
1447 netif_carrier_off(dev);
1448
1449 spin_unlock_irq(&de->lock);
1450 enable_irq(dev->irq);
1451
1452 /* Update the error counts. */
1453 __de_get_stats(de);
1454
1455 synchronize_irq(dev->irq);
1456 de_clean_rings(de);
1457
1458 de_init_hw(de);
1459
1460 netif_wake_queue(dev);
1461}
1462
1463static void __de_get_regs(struct de_private *de, u8 *buf)
1464{
1465 int i;
1466 u32 *rbuf = (u32 *)buf;
1467
1468 /* read all CSRs */
1469 for (i = 0; i < DE_NUM_REGS; i++)
1470 rbuf[i] = dr32(i * 8);
1471
1472 /* handle self-clearing RxMissed counter, CSR8 */
1473 de_rx_missed(de, rbuf[8]);
1474}
1475
1476static int __de_get_settings(struct de_private *de, struct ethtool_cmd *ecmd)
1477{
1478 ecmd->supported = de->media_supported;
1479 ecmd->transceiver = XCVR_INTERNAL;
1480 ecmd->phy_address = 0;
1481 ecmd->advertising = de->media_advertise;
1482
1483 switch (de->media_type) {
1484 case DE_MEDIA_AUI:
1485 ecmd->port = PORT_AUI;
1486 ecmd->speed = 5;
1487 break;
1488 case DE_MEDIA_BNC:
1489 ecmd->port = PORT_BNC;
1490 ecmd->speed = 2;
1491 break;
1492 default:
1493 ecmd->port = PORT_TP;
1494 ecmd->speed = SPEED_10;
1495 break;
1496 }
1497
1498 if (dr32(MacMode) & FullDuplex)
1499 ecmd->duplex = DUPLEX_FULL;
1500 else
1501 ecmd->duplex = DUPLEX_HALF;
1502
1503 if (de->media_lock)
1504 ecmd->autoneg = AUTONEG_DISABLE;
1505 else
1506 ecmd->autoneg = AUTONEG_ENABLE;
1507
1508 /* ignore maxtxpkt, maxrxpkt for now */
1509
1510 return 0;
1511}
1512
1513static int __de_set_settings(struct de_private *de, struct ethtool_cmd *ecmd)
1514{
1515 u32 new_media;
1516 unsigned int media_lock;
1517
1518 if (ecmd->speed != SPEED_10 && ecmd->speed != 5 && ecmd->speed != 2)
1519 return -EINVAL;
1520 if (de->de21040 && ecmd->speed == 2)
1521 return -EINVAL;
1522 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1523 return -EINVAL;
1524 if (ecmd->port != PORT_TP && ecmd->port != PORT_AUI && ecmd->port != PORT_BNC)
1525 return -EINVAL;
1526 if (de->de21040 && ecmd->port == PORT_BNC)
1527 return -EINVAL;
1528 if (ecmd->transceiver != XCVR_INTERNAL)
1529 return -EINVAL;
1530 if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
1531 return -EINVAL;
1532 if (ecmd->advertising & ~de->media_supported)
1533 return -EINVAL;
1534 if (ecmd->autoneg == AUTONEG_ENABLE &&
1535 (!(ecmd->advertising & ADVERTISED_Autoneg)))
1536 return -EINVAL;
1537
1538 switch (ecmd->port) {
1539 case PORT_AUI:
1540 new_media = DE_MEDIA_AUI;
1541 if (!(ecmd->advertising & ADVERTISED_AUI))
1542 return -EINVAL;
1543 break;
1544 case PORT_BNC:
1545 new_media = DE_MEDIA_BNC;
1546 if (!(ecmd->advertising & ADVERTISED_BNC))
1547 return -EINVAL;
1548 break;
1549 default:
1550 if (ecmd->autoneg == AUTONEG_ENABLE)
1551 new_media = DE_MEDIA_TP_AUTO;
1552 else if (ecmd->duplex == DUPLEX_FULL)
1553 new_media = DE_MEDIA_TP_FD;
1554 else
1555 new_media = DE_MEDIA_TP;
1556 if (!(ecmd->advertising & ADVERTISED_TP))
1557 return -EINVAL;
1558 if (!(ecmd->advertising & (ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half)))
1559 return -EINVAL;
1560 break;
1561 }
1562
1563 media_lock = (ecmd->autoneg == AUTONEG_ENABLE) ? 0 : 1;
1564
1565 if ((new_media == de->media_type) &&
1566 (media_lock == de->media_lock) &&
1567 (ecmd->advertising == de->media_advertise))
1568 return 0; /* nothing to change */
1569
1570 de_link_down(de);
1571 de_stop_rxtx(de);
1572
1573 de->media_type = new_media;
1574 de->media_lock = media_lock;
1575 de->media_advertise = ecmd->advertising;
1576 de_set_media(de);
1577
1578 return 0;
1579}
1580
1581static void de_get_drvinfo (struct net_device *dev,struct ethtool_drvinfo *info)
1582{
1583 struct de_private *de = dev->priv;
1584
1585 strcpy (info->driver, DRV_NAME);
1586 strcpy (info->version, DRV_VERSION);
1587 strcpy (info->bus_info, pci_name(de->pdev));
1588 info->eedump_len = DE_EEPROM_SIZE;
1589}
1590
1591static int de_get_regs_len(struct net_device *dev)
1592{
1593 return DE_REGS_SIZE;
1594}
1595
1596static int de_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1597{
1598 struct de_private *de = dev->priv;
1599 int rc;
1600
1601 spin_lock_irq(&de->lock);
1602 rc = __de_get_settings(de, ecmd);
1603 spin_unlock_irq(&de->lock);
1604
1605 return rc;
1606}
1607
1608static int de_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1609{
1610 struct de_private *de = dev->priv;
1611 int rc;
1612
1613 spin_lock_irq(&de->lock);
1614 rc = __de_set_settings(de, ecmd);
1615 spin_unlock_irq(&de->lock);
1616
1617 return rc;
1618}
1619
1620static u32 de_get_msglevel(struct net_device *dev)
1621{
1622 struct de_private *de = dev->priv;
1623
1624 return de->msg_enable;
1625}
1626
1627static void de_set_msglevel(struct net_device *dev, u32 msglvl)
1628{
1629 struct de_private *de = dev->priv;
1630
1631 de->msg_enable = msglvl;
1632}
1633
1634static int de_get_eeprom(struct net_device *dev,
1635 struct ethtool_eeprom *eeprom, u8 *data)
1636{
1637 struct de_private *de = dev->priv;
1638
1639 if (!de->ee_data)
1640 return -EOPNOTSUPP;
1641 if ((eeprom->offset != 0) || (eeprom->magic != 0) ||
1642 (eeprom->len != DE_EEPROM_SIZE))
1643 return -EINVAL;
1644 memcpy(data, de->ee_data, eeprom->len);
1645
1646 return 0;
1647}
1648
1649static int de_nway_reset(struct net_device *dev)
1650{
1651 struct de_private *de = dev->priv;
1652 u32 status;
1653
1654 if (de->media_type != DE_MEDIA_TP_AUTO)
1655 return -EINVAL;
1656 if (netif_carrier_ok(de->dev))
1657 de_link_down(de);
1658
1659 status = dr32(SIAStatus);
1660 dw32(SIAStatus, (status & ~NWayState) | NWayRestart);
1661 if (netif_msg_link(de))
1662 printk(KERN_INFO "%s: link nway restart, status %x,%x\n",
1663 de->dev->name, status, dr32(SIAStatus));
1664 return 0;
1665}
1666
1667static void de_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1668 void *data)
1669{
1670 struct de_private *de = dev->priv;
1671
1672 regs->version = (DE_REGS_VER << 2) | de->de21040;
1673
1674 spin_lock_irq(&de->lock);
1675 __de_get_regs(de, data);
1676 spin_unlock_irq(&de->lock);
1677}
1678
1679static struct ethtool_ops de_ethtool_ops = {
1680 .get_link = ethtool_op_get_link,
1681 .get_tx_csum = ethtool_op_get_tx_csum,
1682 .get_sg = ethtool_op_get_sg,
1683 .get_drvinfo = de_get_drvinfo,
1684 .get_regs_len = de_get_regs_len,
1685 .get_settings = de_get_settings,
1686 .set_settings = de_set_settings,
1687 .get_msglevel = de_get_msglevel,
1688 .set_msglevel = de_set_msglevel,
1689 .get_eeprom = de_get_eeprom,
1690 .nway_reset = de_nway_reset,
1691 .get_regs = de_get_regs,
1692};
1693
1694static void __init de21040_get_mac_address (struct de_private *de)
1695{
1696 unsigned i;
1697
1698 dw32 (ROMCmd, 0); /* Reset the pointer with a dummy write. */
1699
1700 for (i = 0; i < 6; i++) {
1701 int value, boguscnt = 100000;
1702 do
1703 value = dr32(ROMCmd);
1704 while (value < 0 && --boguscnt > 0);
1705 de->dev->dev_addr[i] = value;
1706 udelay(1);
1707 if (boguscnt <= 0)
1708 printk(KERN_WARNING PFX "timeout reading 21040 MAC address byte %u\n", i);
1709 }
1710}
1711
1712static void __init de21040_get_media_info(struct de_private *de)
1713{
1714 unsigned int i;
1715
1716 de->media_type = DE_MEDIA_TP;
1717 de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Full |
1718 SUPPORTED_10baseT_Half | SUPPORTED_AUI;
1719 de->media_advertise = de->media_supported;
1720
1721 for (i = 0; i < DE_MAX_MEDIA; i++) {
1722 switch (i) {
1723 case DE_MEDIA_AUI:
1724 case DE_MEDIA_TP:
1725 case DE_MEDIA_TP_FD:
1726 de->media[i].type = i;
1727 de->media[i].csr13 = t21040_csr13[i];
1728 de->media[i].csr14 = t21040_csr14[i];
1729 de->media[i].csr15 = t21040_csr15[i];
1730 break;
1731 default:
1732 de->media[i].type = DE_MEDIA_INVALID;
1733 break;
1734 }
1735 }
1736}
1737
1738/* Note: this routine returns extra data bits for size detection. */
1739static unsigned __init tulip_read_eeprom(void __iomem *regs, int location, int addr_len)
1740{
1741 int i;
1742 unsigned retval = 0;
1743 void __iomem *ee_addr = regs + ROMCmd;
1744 int read_cmd = location | (EE_READ_CMD << addr_len);
1745
1746 writel(EE_ENB & ~EE_CS, ee_addr);
1747 writel(EE_ENB, ee_addr);
1748
1749 /* Shift the read command bits out. */
1750 for (i = 4 + addr_len; i >= 0; i--) {
1751 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1752 writel(EE_ENB | dataval, ee_addr);
1753 readl(ee_addr);
1754 writel(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1755 readl(ee_addr);
1756 retval = (retval << 1) | ((readl(ee_addr) & EE_DATA_READ) ? 1 : 0);
1757 }
1758 writel(EE_ENB, ee_addr);
1759 readl(ee_addr);
1760
1761 for (i = 16; i > 0; i--) {
1762 writel(EE_ENB | EE_SHIFT_CLK, ee_addr);
1763 readl(ee_addr);
1764 retval = (retval << 1) | ((readl(ee_addr) & EE_DATA_READ) ? 1 : 0);
1765 writel(EE_ENB, ee_addr);
1766 readl(ee_addr);
1767 }
1768
1769 /* Terminate the EEPROM access. */
1770 writel(EE_ENB & ~EE_CS, ee_addr);
1771 return retval;
1772}
1773
1774static void __init de21041_get_srom_info (struct de_private *de)
1775{
1776 unsigned i, sa_offset = 0, ofs;
1777 u8 ee_data[DE_EEPROM_SIZE + 6] = {};
1778 unsigned ee_addr_size = tulip_read_eeprom(de->regs, 0xff, 8) & 0x40000 ? 8 : 6;
1779 struct de_srom_info_leaf *il;
1780 void *bufp;
1781
1782 /* download entire eeprom */
1783 for (i = 0; i < DE_EEPROM_WORDS; i++)
1784 ((u16 *)ee_data)[i] =
1785 le16_to_cpu(tulip_read_eeprom(de->regs, i, ee_addr_size));
1786
1787 /* DEC now has a specification but early board makers
1788 just put the address in the first EEPROM locations. */
1789 /* This does memcmp(eedata, eedata+16, 8) */
1790 for (i = 0; i < 8; i ++)
1791 if (ee_data[i] != ee_data[16+i])
1792 sa_offset = 20;
1793
1794 /* store MAC address */
1795 for (i = 0; i < 6; i ++)
1796 de->dev->dev_addr[i] = ee_data[i + sa_offset];
1797
1798 /* get offset of controller 0 info leaf. ignore 2nd byte. */
1799 ofs = ee_data[SROMC0InfoLeaf];
1800 if (ofs >= (sizeof(ee_data) - sizeof(struct de_srom_info_leaf) - sizeof(struct de_srom_media_block)))
1801 goto bad_srom;
1802
1803 /* get pointer to info leaf */
1804 il = (struct de_srom_info_leaf *) &ee_data[ofs];
1805
1806 /* paranoia checks */
1807 if (il->n_blocks == 0)
1808 goto bad_srom;
1809 if ((sizeof(ee_data) - ofs) <
1810 (sizeof(struct de_srom_info_leaf) + (sizeof(struct de_srom_media_block) * il->n_blocks)))
1811 goto bad_srom;
1812
1813 /* get default media type */
1814 switch (DE_UNALIGNED_16(&il->default_media)) {
1815 case 0x0001: de->media_type = DE_MEDIA_BNC; break;
1816 case 0x0002: de->media_type = DE_MEDIA_AUI; break;
1817 case 0x0204: de->media_type = DE_MEDIA_TP_FD; break;
1818 default: de->media_type = DE_MEDIA_TP_AUTO; break;
1819 }
1820
1821 if (netif_msg_probe(de))
1822 printk(KERN_INFO "de%d: SROM leaf offset %u, default media %s\n",
1823 de->board_idx, ofs,
1824 media_name[de->media_type]);
1825
1826 /* init SIA register values to defaults */
1827 for (i = 0; i < DE_MAX_MEDIA; i++) {
1828 de->media[i].type = DE_MEDIA_INVALID;
1829 de->media[i].csr13 = 0xffff;
1830 de->media[i].csr14 = 0xffff;
1831 de->media[i].csr15 = 0xffff;
1832 }
1833
1834 /* parse media blocks to see what medias are supported,
1835 * and if any custom CSR values are provided
1836 */
1837 bufp = ((void *)il) + sizeof(*il);
1838 for (i = 0; i < il->n_blocks; i++) {
1839 struct de_srom_media_block *ib = bufp;
1840 unsigned idx;
1841
1842 /* index based on media type in media block */
1843 switch(ib->opts & MediaBlockMask) {
1844 case 0: /* 10baseT */
1845 de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Half
1846 | SUPPORTED_Autoneg;
1847 idx = DE_MEDIA_TP;
1848 de->media[DE_MEDIA_TP_AUTO].type = DE_MEDIA_TP_AUTO;
1849 break;
1850 case 1: /* BNC */
1851 de->media_supported |= SUPPORTED_BNC;
1852 idx = DE_MEDIA_BNC;
1853 break;
1854 case 2: /* AUI */
1855 de->media_supported |= SUPPORTED_AUI;
1856 idx = DE_MEDIA_AUI;
1857 break;
1858 case 4: /* 10baseT-FD */
1859 de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Full
1860 | SUPPORTED_Autoneg;
1861 idx = DE_MEDIA_TP_FD;
1862 de->media[DE_MEDIA_TP_AUTO].type = DE_MEDIA_TP_AUTO;
1863 break;
1864 default:
1865 goto bad_srom;
1866 }
1867
1868 de->media[idx].type = idx;
1869
1870 if (netif_msg_probe(de))
1871 printk(KERN_INFO "de%d: media block #%u: %s",
1872 de->board_idx, i,
1873 media_name[de->media[idx].type]);
1874
1875 bufp += sizeof (ib->opts);
1876
1877 if (ib->opts & MediaCustomCSRs) {
1878 de->media[idx].csr13 = DE_UNALIGNED_16(&ib->csr13);
1879 de->media[idx].csr14 = DE_UNALIGNED_16(&ib->csr14);
1880 de->media[idx].csr15 = DE_UNALIGNED_16(&ib->csr15);
1881 bufp += sizeof(ib->csr13) + sizeof(ib->csr14) +
1882 sizeof(ib->csr15);
1883
1884 if (netif_msg_probe(de))
1885 printk(" (%x,%x,%x)\n",
1886 de->media[idx].csr13,
1887 de->media[idx].csr14,
1888 de->media[idx].csr15);
1889
1890 } else if (netif_msg_probe(de))
1891 printk("\n");
1892
1893 if (bufp > ((void *)&ee_data[DE_EEPROM_SIZE - 3]))
1894 break;
1895 }
1896
1897 de->media_advertise = de->media_supported;
1898
1899fill_defaults:
1900 /* fill in defaults, for cases where custom CSRs not used */
1901 for (i = 0; i < DE_MAX_MEDIA; i++) {
1902 if (de->media[i].csr13 == 0xffff)
1903 de->media[i].csr13 = t21041_csr13[i];
1904 if (de->media[i].csr14 == 0xffff)
1905 de->media[i].csr14 = t21041_csr14[i];
1906 if (de->media[i].csr15 == 0xffff)
1907 de->media[i].csr15 = t21041_csr15[i];
1908 }
1909
1910 de->ee_data = kmalloc(DE_EEPROM_SIZE, GFP_KERNEL);
1911 if (de->ee_data)
1912 memcpy(de->ee_data, &ee_data[0], DE_EEPROM_SIZE);
1913
1914 return;
1915
1916bad_srom:
1917 /* for error cases, it's ok to assume we support all these */
1918 for (i = 0; i < DE_MAX_MEDIA; i++)
1919 de->media[i].type = i;
1920 de->media_supported =
1921 SUPPORTED_10baseT_Half |
1922 SUPPORTED_10baseT_Full |
1923 SUPPORTED_Autoneg |
1924 SUPPORTED_TP |
1925 SUPPORTED_AUI |
1926 SUPPORTED_BNC;
1927 goto fill_defaults;
1928}
1929
1930static int __init de_init_one (struct pci_dev *pdev,
1931 const struct pci_device_id *ent)
1932{
1933 struct net_device *dev;
1934 struct de_private *de;
1935 int rc;
1936 void __iomem *regs;
1937 long pciaddr;
1938 static int board_idx = -1;
1939
1940 board_idx++;
1941
1942#ifndef MODULE
1943 if (board_idx == 0)
1944 printk("%s", version);
1945#endif
1946
1947 /* allocate a new ethernet device structure, and fill in defaults */
1948 dev = alloc_etherdev(sizeof(struct de_private));
1949 if (!dev)
1950 return -ENOMEM;
1951
1952 SET_MODULE_OWNER(dev);
1953 SET_NETDEV_DEV(dev, &pdev->dev);
1954 dev->open = de_open;
1955 dev->stop = de_close;
1956 dev->set_multicast_list = de_set_rx_mode;
1957 dev->hard_start_xmit = de_start_xmit;
1958 dev->get_stats = de_get_stats;
1959 dev->ethtool_ops = &de_ethtool_ops;
1960 dev->tx_timeout = de_tx_timeout;
1961 dev->watchdog_timeo = TX_TIMEOUT;
1962
1963 de = dev->priv;
1964 de->de21040 = ent->driver_data == 0 ? 1 : 0;
1965 de->pdev = pdev;
1966 de->dev = dev;
1967 de->msg_enable = (debug < 0 ? DE_DEF_MSG_ENABLE : debug);
1968 de->board_idx = board_idx;
1969 spin_lock_init (&de->lock);
1970 init_timer(&de->media_timer);
1971 if (de->de21040)
1972 de->media_timer.function = de21040_media_timer;
1973 else
1974 de->media_timer.function = de21041_media_timer;
1975 de->media_timer.data = (unsigned long) de;
1976
1977 netif_carrier_off(dev);
1978 netif_stop_queue(dev);
1979
1980 /* wake up device, assign resources */
1981 rc = pci_enable_device(pdev);
1982 if (rc)
1983 goto err_out_free;
1984
1985 /* reserve PCI resources to ensure driver atomicity */
1986 rc = pci_request_regions(pdev, DRV_NAME);
1987 if (rc)
1988 goto err_out_disable;
1989
1990 /* check for invalid IRQ value */
1991 if (pdev->irq < 2) {
1992 rc = -EIO;
1993 printk(KERN_ERR PFX "invalid irq (%d) for pci dev %s\n",
1994 pdev->irq, pci_name(pdev));
1995 goto err_out_res;
1996 }
1997
1998 dev->irq = pdev->irq;
1999
2000 /* obtain and check validity of PCI I/O address */
2001 pciaddr = pci_resource_start(pdev, 1);
2002 if (!pciaddr) {
2003 rc = -EIO;
2004 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
2005 pci_name(pdev));
2006 goto err_out_res;
2007 }
2008 if (pci_resource_len(pdev, 1) < DE_REGS_SIZE) {
2009 rc = -EIO;
2010 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
2011 pci_resource_len(pdev, 1), pci_name(pdev));
2012 goto err_out_res;
2013 }
2014
2015 /* remap CSR registers */
2016 regs = ioremap_nocache(pciaddr, DE_REGS_SIZE);
2017 if (!regs) {
2018 rc = -EIO;
2019 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
2020 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
2021 goto err_out_res;
2022 }
2023 dev->base_addr = (unsigned long) regs;
2024 de->regs = regs;
2025
2026 de_adapter_wake(de);
2027
2028 /* make sure hardware is not running */
2029 rc = de_reset_mac(de);
2030 if (rc) {
2031 printk(KERN_ERR PFX "Cannot reset MAC, pci dev %s\n",
2032 pci_name(pdev));
2033 goto err_out_iomap;
2034 }
2035
2036 /* get MAC address, initialize default media type and
2037 * get list of supported media
2038 */
2039 if (de->de21040) {
2040 de21040_get_mac_address(de);
2041 de21040_get_media_info(de);
2042 } else {
2043 de21041_get_srom_info(de);
2044 }
2045
2046 /* register new network interface with kernel */
2047 rc = register_netdev(dev);
2048 if (rc)
2049 goto err_out_iomap;
2050
2051 /* print info about board and interface just registered */
2052 printk (KERN_INFO "%s: %s at 0x%lx, "
2053 "%02x:%02x:%02x:%02x:%02x:%02x, "
2054 "IRQ %d\n",
2055 dev->name,
2056 de->de21040 ? "21040" : "21041",
2057 dev->base_addr,
2058 dev->dev_addr[0], dev->dev_addr[1],
2059 dev->dev_addr[2], dev->dev_addr[3],
2060 dev->dev_addr[4], dev->dev_addr[5],
2061 dev->irq);
2062
2063 pci_set_drvdata(pdev, dev);
2064
2065 /* enable busmastering */
2066 pci_set_master(pdev);
2067
2068 /* put adapter to sleep */
2069 de_adapter_sleep(de);
2070
2071 return 0;
2072
2073err_out_iomap:
2074 if (de->ee_data)
2075 kfree(de->ee_data);
2076 iounmap(regs);
2077err_out_res:
2078 pci_release_regions(pdev);
2079err_out_disable:
2080 pci_disable_device(pdev);
2081err_out_free:
2082 free_netdev(dev);
2083 return rc;
2084}
2085
2086static void __exit de_remove_one (struct pci_dev *pdev)
2087{
2088 struct net_device *dev = pci_get_drvdata(pdev);
2089 struct de_private *de = dev->priv;
2090
2091 if (!dev)
2092 BUG();
2093 unregister_netdev(dev);
2094 if (de->ee_data)
2095 kfree(de->ee_data);
2096 iounmap(de->regs);
2097 pci_release_regions(pdev);
2098 pci_disable_device(pdev);
2099 pci_set_drvdata(pdev, NULL);
2100 free_netdev(dev);
2101}
2102
2103#ifdef CONFIG_PM
2104
2105static int de_suspend (struct pci_dev *pdev, u32 state)
2106{
2107 struct net_device *dev = pci_get_drvdata (pdev);
2108 struct de_private *de = dev->priv;
2109
2110 rtnl_lock();
2111 if (netif_running (dev)) {
2112 del_timer_sync(&de->media_timer);
2113
2114 disable_irq(dev->irq);
2115 spin_lock_irq(&de->lock);
2116
2117 de_stop_hw(de);
2118 netif_stop_queue(dev);
2119 netif_device_detach(dev);
2120 netif_carrier_off(dev);
2121
2122 spin_unlock_irq(&de->lock);
2123 enable_irq(dev->irq);
2124
2125 /* Update the error counts. */
2126 __de_get_stats(de);
2127
2128 synchronize_irq(dev->irq);
2129 de_clean_rings(de);
2130
2131 de_adapter_sleep(de);
2132 pci_disable_device(pdev);
2133 } else {
2134 netif_device_detach(dev);
2135 }
2136 rtnl_unlock();
2137 return 0;
2138}
2139
2140static int de_resume (struct pci_dev *pdev)
2141{
2142 struct net_device *dev = pci_get_drvdata (pdev);
2143 struct de_private *de = dev->priv;
2144
2145 rtnl_lock();
2146 if (netif_device_present(dev))
2147 goto out;
2148 if (netif_running(dev)) {
2149 pci_enable_device(pdev);
2150 de_init_hw(de);
2151 netif_device_attach(dev);
2152 } else {
2153 netif_device_attach(dev);
2154 }
2155out:
2156 rtnl_unlock();
2157 return 0;
2158}
2159
2160#endif /* CONFIG_PM */
2161
2162static struct pci_driver de_driver = {
2163 .name = DRV_NAME,
2164 .id_table = de_pci_tbl,
2165 .probe = de_init_one,
2166 .remove = __exit_p(de_remove_one),
2167#ifdef CONFIG_PM
2168 .suspend = de_suspend,
2169 .resume = de_resume,
2170#endif
2171};
2172
2173static int __init de_init (void)
2174{
2175#ifdef MODULE
2176 printk("%s", version);
2177#endif
2178 return pci_module_init (&de_driver);
2179}
2180
2181static void __exit de_exit (void)
2182{
2183 pci_unregister_driver (&de_driver);
2184}
2185
2186module_init(de_init);
2187module_exit(de_exit);
diff --git a/drivers/net/tulip/de4x5.c b/drivers/net/tulip/de4x5.c
new file mode 100644
index 000000000000..93800c126e86
--- /dev/null
+++ b/drivers/net/tulip/de4x5.c
@@ -0,0 +1,5778 @@
1/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444*/
445
446#include <linux/config.h>
447#include <linux/module.h>
448#include <linux/kernel.h>
449#include <linux/string.h>
450#include <linux/interrupt.h>
451#include <linux/ptrace.h>
452#include <linux/errno.h>
453#include <linux/ioport.h>
454#include <linux/slab.h>
455#include <linux/pci.h>
456#include <linux/eisa.h>
457#include <linux/delay.h>
458#include <linux/init.h>
459#include <linux/spinlock.h>
460#include <linux/crc32.h>
461#include <linux/netdevice.h>
462#include <linux/etherdevice.h>
463#include <linux/skbuff.h>
464#include <linux/time.h>
465#include <linux/types.h>
466#include <linux/unistd.h>
467#include <linux/ctype.h>
468#include <linux/dma-mapping.h>
469#include <linux/moduleparam.h>
470#include <linux/bitops.h>
471
472#include <asm/io.h>
473#include <asm/dma.h>
474#include <asm/byteorder.h>
475#include <asm/unaligned.h>
476#include <asm/uaccess.h>
477#ifdef CONFIG_PPC_MULTIPLATFORM
478#include <asm/machdep.h>
479#endif /* CONFIG_PPC_MULTIPLATFORM */
480
481#include "de4x5.h"
482
483static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485#define c_char const char
486#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
487
488/*
489** MII Information
490*/
491struct phy_table {
492 int reset; /* Hard reset required? */
493 int id; /* IEEE OUI */
494 int ta; /* One cycle TA time - 802.3u is confusing here */
495 struct { /* Non autonegotiation (parallel) speed det. */
496 int reg;
497 int mask;
498 int value;
499 } spd;
500};
501
502struct mii_phy {
503 int reset; /* Hard reset required? */
504 int id; /* IEEE OUI */
505 int ta; /* One cycle TA time */
506 struct { /* Non autonegotiation (parallel) speed det. */
507 int reg;
508 int mask;
509 int value;
510 } spd;
511 int addr; /* MII address for the PHY */
512 u_char *gep; /* Start of GEP sequence block in SROM */
513 u_char *rst; /* Start of reset sequence in SROM */
514 u_int mc; /* Media Capabilities */
515 u_int ana; /* NWay Advertisement */
516 u_int fdx; /* Full DupleX capabilites for each media */
517 u_int ttm; /* Transmit Threshold Mode for each media */
518 u_int mci; /* 21142 MII Connector Interrupt info */
519};
520
521#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
522
523struct sia_phy {
524 u_char mc; /* Media Code */
525 u_char ext; /* csr13-15 valid when set */
526 int csr13; /* SIA Connectivity Register */
527 int csr14; /* SIA TX/RX Register */
528 int csr15; /* SIA General Register */
529 int gepc; /* SIA GEP Control Information */
530 int gep; /* SIA GEP Data */
531};
532
533/*
534** Define the know universe of PHY devices that can be
535** recognised by this driver.
536*/
537static struct phy_table phy_info[] = {
538 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
539 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
540 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
541 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
542 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
543};
544
545/*
546** These GENERIC values assumes that the PHY devices follow 802.3u and
547** allow parallel detection to set the link partner ability register.
548** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
549*/
550#define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
551#define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
552#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
553
554/*
555** Define special SROM detection cases
556*/
557static c_char enet_det[][ETH_ALEN] = {
558 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
559 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
560};
561
562#define SMC 1
563#define ACCTON 2
564
565/*
566** SROM Repair definitions. If a broken SROM is detected a card may
567** use this information to help figure out what to do. This is a
568** "stab in the dark" and so far for SMC9332's only.
569*/
570static c_char srom_repair_info[][100] = {
571 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
572 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
573 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
574 0x00,0x18,}
575};
576
577
578#ifdef DE4X5_DEBUG
579static int de4x5_debug = DE4X5_DEBUG;
580#else
581/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
582static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
583#endif
584
585/*
586** Allow per adapter set up. For modules this is simply a command line
587** parameter, e.g.:
588** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
589**
590** For a compiled in driver, place e.g.
591** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
592** here
593*/
594#ifdef DE4X5_PARM
595static char *args = DE4X5_PARM;
596#else
597static char *args;
598#endif
599
600struct parameters {
601 int fdx;
602 int autosense;
603};
604
605#define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
606
607#define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
608
609/*
610** Ethernet PROM defines
611*/
612#define PROBE_LENGTH 32
613#define ETH_PROM_SIG 0xAA5500FFUL
614
615/*
616** Ethernet Info
617*/
618#define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
619#define IEEE802_3_SZ 1518 /* Packet + CRC */
620#define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
621#define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
622#define MIN_DAT_SZ 1 /* Minimum ethernet data length */
623#define PKT_HDR_LEN 14 /* Addresses and data length info */
624#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
625#define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
626
627
628/*
629** EISA bus defines
630*/
631#define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
632#define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633
634#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
635
636#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
637#define DE4X5_NAME_LENGTH 8
638
639static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
640
641/*
642** Ethernet PROM defines for DC21040
643*/
644#define PROBE_LENGTH 32
645#define ETH_PROM_SIG 0xAA5500FFUL
646
647/*
648** PCI Bus defines
649*/
650#define PCI_MAX_BUS_NUM 8
651#define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
652#define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
653
654/*
655** Memory Alignment. Each descriptor is 4 longwords long. To force a
656** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
657** DESC_ALIGN. ALIGN aligns the start address of the private memory area
658** and hence the RX descriptor ring's first entry.
659*/
660#define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661#define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662#define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663#define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664#define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665#define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666
667#define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
668#define DE4X5_CACHE_ALIGN CAL_16LONG
669#define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
670/*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
671#define DESC_ALIGN
672
673#ifndef DEC_ONLY /* See README.de4x5 for using this */
674static int dec_only;
675#else
676static int dec_only = 1;
677#endif
678
679/*
680** DE4X5 IRQ ENABLE/DISABLE
681*/
682#define ENABLE_IRQs { \
683 imr |= lp->irq_en;\
684 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
685}
686
687#define DISABLE_IRQs {\
688 imr = inl(DE4X5_IMR);\
689 imr &= ~lp->irq_en;\
690 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
691}
692
693#define UNMASK_IRQs {\
694 imr |= lp->irq_mask;\
695 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
696}
697
698#define MASK_IRQs {\
699 imr = inl(DE4X5_IMR);\
700 imr &= ~lp->irq_mask;\
701 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
702}
703
704/*
705** DE4X5 START/STOP
706*/
707#define START_DE4X5 {\
708 omr = inl(DE4X5_OMR);\
709 omr |= OMR_ST | OMR_SR;\
710 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
711}
712
713#define STOP_DE4X5 {\
714 omr = inl(DE4X5_OMR);\
715 omr &= ~(OMR_ST|OMR_SR);\
716 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
717}
718
719/*
720** DE4X5 SIA RESET
721*/
722#define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
723
724/*
725** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726*/
727#define DE4X5_AUTOSENSE_MS 250
728
729/*
730** SROM Structure
731*/
732struct de4x5_srom {
733 char sub_vendor_id[2];
734 char sub_system_id[2];
735 char reserved[12];
736 char id_block_crc;
737 char reserved2;
738 char version;
739 char num_controllers;
740 char ieee_addr[6];
741 char info[100];
742 short chksum;
743};
744#define SUB_VENDOR_ID 0x500a
745
746/*
747** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
748** and have sizes of both a power of 2 and a multiple of 4.
749** A size of 256 bytes for each buffer could be chosen because over 90% of
750** all packets in our network are <256 bytes long and 64 longword alignment
751** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
752** descriptors are needed for machines with an ALPHA CPU.
753*/
754#define NUM_RX_DESC 8 /* Number of RX descriptors */
755#define NUM_TX_DESC 32 /* Number of TX descriptors */
756#define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
757 /* Multiple of 4 for DC21040 */
758 /* Allows 512 byte alignment */
759struct de4x5_desc {
760 volatile s32 status;
761 u32 des1;
762 u32 buf;
763 u32 next;
764 DESC_ALIGN
765};
766
767/*
768** The DE4X5 private structure
769*/
770#define DE4X5_PKT_STAT_SZ 16
771#define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
772 increase DE4X5_PKT_STAT_SZ */
773
774struct pkt_stats {
775 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
776 u_int unicast;
777 u_int multicast;
778 u_int broadcast;
779 u_int excessive_collisions;
780 u_int tx_underruns;
781 u_int excessive_underruns;
782 u_int rx_runt_frames;
783 u_int rx_collision;
784 u_int rx_dribble;
785 u_int rx_overflow;
786};
787
788struct de4x5_private {
789 char adapter_name[80]; /* Adapter name */
790 u_long interrupt; /* Aligned ISR flag */
791 struct de4x5_desc *rx_ring; /* RX descriptor ring */
792 struct de4x5_desc *tx_ring; /* TX descriptor ring */
793 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
794 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
795 int rx_new, rx_old; /* RX descriptor ring pointers */
796 int tx_new, tx_old; /* TX descriptor ring pointers */
797 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
798 char frame[64]; /* Min sized packet for loopback*/
799 spinlock_t lock; /* Adapter specific spinlock */
800 struct net_device_stats stats; /* Public stats */
801 struct pkt_stats pktStats; /* Private stats counters */
802 char rxRingSize;
803 char txRingSize;
804 int bus; /* EISA or PCI */
805 int bus_num; /* PCI Bus number */
806 int device; /* Device number on PCI bus */
807 int state; /* Adapter OPENED or CLOSED */
808 int chipset; /* DC21040, DC21041 or DC21140 */
809 s32 irq_mask; /* Interrupt Mask (Enable) bits */
810 s32 irq_en; /* Summary interrupt bits */
811 int media; /* Media (eg TP), mode (eg 100B)*/
812 int c_media; /* Remember the last media conn */
813 int fdx; /* media full duplex flag */
814 int linkOK; /* Link is OK */
815 int autosense; /* Allow/disallow autosensing */
816 int tx_enable; /* Enable descriptor polling */
817 int setup_f; /* Setup frame filtering type */
818 int local_state; /* State within a 'media' state */
819 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
820 struct sia_phy sia; /* SIA PHY Information */
821 int active; /* Index to active PHY device */
822 int mii_cnt; /* Number of attached PHY's */
823 int timeout; /* Scheduling counter */
824 struct timer_list timer; /* Timer info for kernel */
825 int tmp; /* Temporary global per card */
826 struct {
827 u_long lock; /* Lock the cache accesses */
828 s32 csr0; /* Saved Bus Mode Register */
829 s32 csr6; /* Saved Operating Mode Reg. */
830 s32 csr7; /* Saved IRQ Mask Register */
831 s32 gep; /* Saved General Purpose Reg. */
832 s32 gepc; /* Control info for GEP */
833 s32 csr13; /* Saved SIA Connectivity Reg. */
834 s32 csr14; /* Saved SIA TX/RX Register */
835 s32 csr15; /* Saved SIA General Register */
836 int save_cnt; /* Flag if state already saved */
837 struct sk_buff *skb; /* Save the (re-ordered) skb's */
838 } cache;
839 struct de4x5_srom srom; /* A copy of the SROM */
840 int cfrv; /* Card CFRV copy */
841 int rx_ovf; /* Check for 'RX overflow' tag */
842 int useSROM; /* For non-DEC card use SROM */
843 int useMII; /* Infoblock using the MII */
844 int asBitValid; /* Autosense bits in GEP? */
845 int asPolarity; /* 0 => asserted high */
846 int asBit; /* Autosense bit number in GEP */
847 int defMedium; /* SROM default medium */
848 int tcount; /* Last infoblock number */
849 int infoblock_init; /* Initialised this infoblock? */
850 int infoleaf_offset; /* SROM infoleaf for controller */
851 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
852 int infoblock_media; /* infoblock media */
853 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
854 u_char *rst; /* Pointer to Type 5 reset info */
855 u_char ibn; /* Infoblock number */
856 struct parameters params; /* Command line/ #defined params */
857 struct device *gendev; /* Generic device */
858 dma_addr_t dma_rings; /* DMA handle for rings */
859 int dma_size; /* Size of the DMA area */
860 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
861};
862
863/*
864** To get around certain poxy cards that don't provide an SROM
865** for the second and more DECchip, I have to key off the first
866** chip's address. I'll assume there's not a bad SROM iff:
867**
868** o the chipset is the same
869** o the bus number is the same and > 0
870** o the sum of all the returned hw address bytes is 0 or 0x5fa
871**
872** Also have to save the irq for those cards whose hardware designers
873** can't follow the PCI to PCI Bridge Architecture spec.
874*/
875static struct {
876 int chipset;
877 int bus;
878 int irq;
879 u_char addr[ETH_ALEN];
880} last = {0,};
881
882/*
883** The transmit ring full condition is described by the tx_old and tx_new
884** pointers by:
885** tx_old = tx_new Empty ring
886** tx_old = tx_new+1 Full ring
887** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888*/
889#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
890 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
891 lp->tx_old -lp->tx_new-1)
892
893#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
894
895/*
896** Public Functions
897*/
898static int de4x5_open(struct net_device *dev);
899static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
900static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
901static int de4x5_close(struct net_device *dev);
902static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904static void set_multicast_list(struct net_device *dev);
905static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907/*
908** Private functions
909*/
910static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911static int de4x5_init(struct net_device *dev);
912static int de4x5_sw_reset(struct net_device *dev);
913static int de4x5_rx(struct net_device *dev);
914static int de4x5_tx(struct net_device *dev);
915static int de4x5_ast(struct net_device *dev);
916static int de4x5_txur(struct net_device *dev);
917static int de4x5_rx_ovfc(struct net_device *dev);
918
919static int autoconf_media(struct net_device *dev);
920static void create_packet(struct net_device *dev, char *frame, int len);
921static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922static int dc21040_autoconf(struct net_device *dev);
923static int dc21041_autoconf(struct net_device *dev);
924static int dc21140m_autoconf(struct net_device *dev);
925static int dc2114x_autoconf(struct net_device *dev);
926static int srom_autoconf(struct net_device *dev);
927static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930static int test_for_100Mb(struct net_device *dev, int msec);
931static int wait_for_link(struct net_device *dev);
932static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
933static int is_spd_100(struct net_device *dev);
934static int is_100_up(struct net_device *dev);
935static int is_10_up(struct net_device *dev);
936static int is_anc_capable(struct net_device *dev);
937static int ping_media(struct net_device *dev, int msec);
938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939static void de4x5_free_rx_buffs(struct net_device *dev);
940static void de4x5_free_tx_buffs(struct net_device *dev);
941static void de4x5_save_skbs(struct net_device *dev);
942static void de4x5_rst_desc_ring(struct net_device *dev);
943static void de4x5_cache_state(struct net_device *dev, int flag);
944static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947static void de4x5_setup_intr(struct net_device *dev);
948static void de4x5_init_connection(struct net_device *dev);
949static int de4x5_reset_phy(struct net_device *dev);
950static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952static int test_tp(struct net_device *dev, s32 msec);
953static int EISA_signature(char *name, struct device *device);
954static int PCI_signature(char *name, struct de4x5_private *lp);
955static void DevicePresent(struct net_device *dev, u_long iobase);
956static void enet_addr_rst(u_long aprom_addr);
957static int de4x5_bad_srom(struct de4x5_private *lp);
958static short srom_rd(u_long address, u_char offset);
959static void srom_latch(u_int command, u_long address);
960static void srom_command(u_int command, u_long address);
961static void srom_address(u_int command, u_long address, u_char offset);
962static short srom_data(u_int command, u_long address);
963/*static void srom_busy(u_int command, u_long address);*/
964static void sendto_srom(u_int command, u_long addr);
965static int getfrom_srom(u_long addr);
966static int srom_map_media(struct net_device *dev);
967static int srom_infoleaf_info(struct net_device *dev);
968static void srom_init(struct net_device *dev);
969static void srom_exec(struct net_device *dev, u_char *p);
970static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972static int mii_rdata(u_long ioaddr);
973static void mii_wdata(int data, int len, u_long ioaddr);
974static void mii_ta(u_long rw, u_long ioaddr);
975static int mii_swap(int data, int len);
976static void mii_address(u_char addr, u_long ioaddr);
977static void sendto_mii(u32 command, int data, u_long ioaddr);
978static int getfrom_mii(u32 command, u_long ioaddr);
979static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980static int mii_get_phy(struct net_device *dev);
981static void SetMulticastFilter(struct net_device *dev);
982static int get_hw_addr(struct net_device *dev);
983static void srom_repair(struct net_device *dev, int card);
984static int test_bad_enet(struct net_device *dev, int status);
985static int an_exception(struct de4x5_private *lp);
986static char *build_setup_frame(struct net_device *dev, int mode);
987static void disable_ast(struct net_device *dev);
988static void enable_ast(struct net_device *dev, u32 time_out);
989static long de4x5_switch_mac_port(struct net_device *dev);
990static int gep_rd(struct net_device *dev);
991static void gep_wr(s32 data, struct net_device *dev);
992static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
993static void yawn(struct net_device *dev, int state);
994static void de4x5_parse_params(struct net_device *dev);
995static void de4x5_dbg_open(struct net_device *dev);
996static void de4x5_dbg_mii(struct net_device *dev, int k);
997static void de4x5_dbg_media(struct net_device *dev);
998static void de4x5_dbg_srom(struct de4x5_srom *p);
999static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1000static int de4x5_strncmp(char *a, char *b, int n);
1001static int dc21041_infoleaf(struct net_device *dev);
1002static int dc21140_infoleaf(struct net_device *dev);
1003static int dc21142_infoleaf(struct net_device *dev);
1004static int dc21143_infoleaf(struct net_device *dev);
1005static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1010static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1011static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1012
1013/*
1014** Note now that module autoprobing is allowed under EISA and PCI. The
1015** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1016** to "do the right thing".
1017*/
1018
1019static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1020
1021module_param(io, int, 0);
1022module_param(de4x5_debug, int, 0);
1023module_param(dec_only, int, 0);
1024module_param(args, charp, 0);
1025
1026MODULE_PARM_DESC(io, "de4x5 I/O base address");
1027MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1028MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1029MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1030MODULE_LICENSE("GPL");
1031
1032/*
1033** List the SROM infoleaf functions and chipsets
1034*/
1035struct InfoLeaf {
1036 int chipset;
1037 int (*fn)(struct net_device *);
1038};
1039static struct InfoLeaf infoleaf_array[] = {
1040 {DC21041, dc21041_infoleaf},
1041 {DC21140, dc21140_infoleaf},
1042 {DC21142, dc21142_infoleaf},
1043 {DC21143, dc21143_infoleaf}
1044};
1045#define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1046
1047/*
1048** List the SROM info block functions
1049*/
1050static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1051 type0_infoblock,
1052 type1_infoblock,
1053 type2_infoblock,
1054 type3_infoblock,
1055 type4_infoblock,
1056 type5_infoblock,
1057 compact_infoblock
1058};
1059
1060#define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1061
1062/*
1063** Miscellaneous defines...
1064*/
1065#define RESET_DE4X5 {\
1066 int i;\
1067 i=inl(DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i | BMR_SWR, DE4X5_BMR);\
1070 mdelay(1);\
1071 outl(i, DE4X5_BMR);\
1072 mdelay(1);\
1073 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1074 mdelay(1);\
1075}
1076
1077#define PHY_HARD_RESET {\
1078 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1079 mdelay(1); /* Assert for 1ms */\
1080 outl(0x00, DE4X5_GEP);\
1081 mdelay(2); /* Wait for 2ms */\
1082}
1083
1084
1085static int __devinit
1086de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1087{
1088 char name[DE4X5_NAME_LENGTH + 1];
1089 struct de4x5_private *lp = netdev_priv(dev);
1090 struct pci_dev *pdev = NULL;
1091 int i, status=0;
1092
1093 gendev->driver_data = dev;
1094
1095 /* Ensure we're not sleeping */
1096 if (lp->bus == EISA) {
1097 outb(WAKEUP, PCI_CFPM);
1098 } else {
1099 pdev = to_pci_dev (gendev);
1100 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1101 }
1102 mdelay(10);
1103
1104 RESET_DE4X5;
1105
1106 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1107 return -ENXIO; /* Hardware could not reset */
1108 }
1109
1110 /*
1111 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1112 */
1113 lp->useSROM = FALSE;
1114 if (lp->bus == PCI) {
1115 PCI_signature(name, lp);
1116 } else {
1117 EISA_signature(name, gendev);
1118 }
1119
1120 if (*name == '\0') { /* Not found a board signature */
1121 return -ENXIO;
1122 }
1123
1124 dev->base_addr = iobase;
1125 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1126
1127 printk(", h/w address ");
1128 status = get_hw_addr(dev);
1129 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1130 printk("%2.2x:", dev->dev_addr[i]);
1131 }
1132 printk("%2.2x,\n", dev->dev_addr[i]);
1133
1134 if (status != 0) {
1135 printk(" which has an Ethernet PROM CRC error.\n");
1136 return -ENXIO;
1137 } else {
1138 lp->cache.gepc = GEP_INIT;
1139 lp->asBit = GEP_SLNK;
1140 lp->asPolarity = GEP_SLNK;
1141 lp->asBitValid = TRUE;
1142 lp->timeout = -1;
1143 lp->gendev = gendev;
1144 spin_lock_init(&lp->lock);
1145 init_timer(&lp->timer);
1146 de4x5_parse_params(dev);
1147
1148 /*
1149 ** Choose correct autosensing in case someone messed up
1150 */
1151 lp->autosense = lp->params.autosense;
1152 if (lp->chipset != DC21140) {
1153 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1154 lp->params.autosense = TP;
1155 }
1156 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1157 lp->params.autosense = BNC;
1158 }
1159 }
1160 lp->fdx = lp->params.fdx;
1161 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1162
1163 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1164#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1165 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1166#endif
1167 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1168 &lp->dma_rings, GFP_ATOMIC);
1169 if (lp->rx_ring == NULL) {
1170 return -ENOMEM;
1171 }
1172
1173 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1174
1175 /*
1176 ** Set up the RX descriptor ring (Intels)
1177 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1178 */
1179#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1180 for (i=0; i<NUM_RX_DESC; i++) {
1181 lp->rx_ring[i].status = 0;
1182 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1183 lp->rx_ring[i].buf = 0;
1184 lp->rx_ring[i].next = 0;
1185 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1186 }
1187
1188#else
1189 {
1190 dma_addr_t dma_rx_bufs;
1191
1192 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1193 * sizeof(struct de4x5_desc);
1194 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1195 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1196 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1197 for (i=0; i<NUM_RX_DESC; i++) {
1198 lp->rx_ring[i].status = 0;
1199 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1200 lp->rx_ring[i].buf =
1201 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1202 lp->rx_ring[i].next = 0;
1203 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1204 }
1205
1206 }
1207#endif
1208
1209 barrier();
1210
1211 lp->rxRingSize = NUM_RX_DESC;
1212 lp->txRingSize = NUM_TX_DESC;
1213
1214 /* Write the end of list marker to the descriptor lists */
1215 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1216 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1217
1218 /* Tell the adapter where the TX/RX rings are located. */
1219 outl(lp->dma_rings, DE4X5_RRBA);
1220 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1221 DE4X5_TRBA);
1222
1223 /* Initialise the IRQ mask and Enable/Disable */
1224 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1225 lp->irq_en = IMR_NIM | IMR_AIM;
1226
1227 /* Create a loopback packet frame for later media probing */
1228 create_packet(dev, lp->frame, sizeof(lp->frame));
1229
1230 /* Check if the RX overflow bug needs testing for */
1231 i = lp->cfrv & 0x000000fe;
1232 if ((lp->chipset == DC21140) && (i == 0x20)) {
1233 lp->rx_ovf = 1;
1234 }
1235
1236 /* Initialise the SROM pointers if possible */
1237 if (lp->useSROM) {
1238 lp->state = INITIALISED;
1239 if (srom_infoleaf_info(dev)) {
1240 dma_free_coherent (gendev, lp->dma_size,
1241 lp->rx_ring, lp->dma_rings);
1242 return -ENXIO;
1243 }
1244 srom_init(dev);
1245 }
1246
1247 lp->state = CLOSED;
1248
1249 /*
1250 ** Check for an MII interface
1251 */
1252 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1253 mii_get_phy(dev);
1254 }
1255
1256#ifndef __sparc_v9__
1257 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1258#else
1259 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1260#endif
1261 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1262 }
1263
1264 if (de4x5_debug & DEBUG_VERSION) {
1265 printk(version);
1266 }
1267
1268 /* The DE4X5-specific entries in the device structure. */
1269 SET_MODULE_OWNER(dev);
1270 SET_NETDEV_DEV(dev, gendev);
1271 dev->open = &de4x5_open;
1272 dev->hard_start_xmit = &de4x5_queue_pkt;
1273 dev->stop = &de4x5_close;
1274 dev->get_stats = &de4x5_get_stats;
1275 dev->set_multicast_list = &set_multicast_list;
1276 dev->do_ioctl = &de4x5_ioctl;
1277
1278 dev->mem_start = 0;
1279
1280 /* Fill in the generic fields of the device structure. */
1281 if ((status = register_netdev (dev))) {
1282 dma_free_coherent (gendev, lp->dma_size,
1283 lp->rx_ring, lp->dma_rings);
1284 return status;
1285 }
1286
1287 /* Let the adapter sleep to save power */
1288 yawn(dev, SLEEP);
1289
1290 return status;
1291}
1292
1293
1294static int
1295de4x5_open(struct net_device *dev)
1296{
1297 struct de4x5_private *lp = netdev_priv(dev);
1298 u_long iobase = dev->base_addr;
1299 int i, status = 0;
1300 s32 omr;
1301
1302 /* Allocate the RX buffers */
1303 for (i=0; i<lp->rxRingSize; i++) {
1304 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1305 de4x5_free_rx_buffs(dev);
1306 return -EAGAIN;
1307 }
1308 }
1309
1310 /*
1311 ** Wake up the adapter
1312 */
1313 yawn(dev, WAKEUP);
1314
1315 /*
1316 ** Re-initialize the DE4X5...
1317 */
1318 status = de4x5_init(dev);
1319 spin_lock_init(&lp->lock);
1320 lp->state = OPEN;
1321 de4x5_dbg_open(dev);
1322
1323 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1324 lp->adapter_name, dev)) {
1325 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1326 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1327 lp->adapter_name, dev)) {
1328 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1329 disable_ast(dev);
1330 de4x5_free_rx_buffs(dev);
1331 de4x5_free_tx_buffs(dev);
1332 yawn(dev, SLEEP);
1333 lp->state = CLOSED;
1334 return -EAGAIN;
1335 } else {
1336 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1337 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1338 }
1339 }
1340
1341 lp->interrupt = UNMASK_INTERRUPTS;
1342 dev->trans_start = jiffies;
1343
1344 START_DE4X5;
1345
1346 de4x5_setup_intr(dev);
1347
1348 if (de4x5_debug & DEBUG_OPEN) {
1349 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1350 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1351 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1352 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1353 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1354 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1355 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1356 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1357 }
1358
1359 return status;
1360}
1361
1362/*
1363** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1364** DC21140 requires using perfect filtering mode for that chip. Since I can't
1365** see why I'd want > 14 multicast addresses, I have changed all chips to use
1366** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1367** to be data corruption problems if it is larger (UDP errors seen from a
1368** ttcp source).
1369*/
1370static int
1371de4x5_init(struct net_device *dev)
1372{
1373 /* Lock out other processes whilst setting up the hardware */
1374 netif_stop_queue(dev);
1375
1376 de4x5_sw_reset(dev);
1377
1378 /* Autoconfigure the connected port */
1379 autoconf_media(dev);
1380
1381 return 0;
1382}
1383
1384static int
1385de4x5_sw_reset(struct net_device *dev)
1386{
1387 struct de4x5_private *lp = netdev_priv(dev);
1388 u_long iobase = dev->base_addr;
1389 int i, j, status = 0;
1390 s32 bmr, omr;
1391
1392 /* Select the MII or SRL port now and RESET the MAC */
1393 if (!lp->useSROM) {
1394 if (lp->phy[lp->active].id != 0) {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1396 } else {
1397 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1398 }
1399 de4x5_switch_mac_port(dev);
1400 }
1401
1402 /*
1403 ** Set the programmable burst length to 8 longwords for all the DC21140
1404 ** Fasternet chips and 4 longwords for all others: DMA errors result
1405 ** without these values. Cache align 16 long.
1406 */
1407 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1408 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1409 outl(bmr, DE4X5_BMR);
1410
1411 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1412 if (lp->chipset == DC21140) {
1413 omr |= (OMR_SDP | OMR_SB);
1414 }
1415 lp->setup_f = PERFECT;
1416 outl(lp->dma_rings, DE4X5_RRBA);
1417 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1418 DE4X5_TRBA);
1419
1420 lp->rx_new = lp->rx_old = 0;
1421 lp->tx_new = lp->tx_old = 0;
1422
1423 for (i = 0; i < lp->rxRingSize; i++) {
1424 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1425 }
1426
1427 for (i = 0; i < lp->txRingSize; i++) {
1428 lp->tx_ring[i].status = cpu_to_le32(0);
1429 }
1430
1431 barrier();
1432
1433 /* Build the setup frame depending on filtering mode */
1434 SetMulticastFilter(dev);
1435
1436 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1437 outl(omr|OMR_ST, DE4X5_OMR);
1438
1439 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1440
1441 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1442 mdelay(1);
1443 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1444 }
1445 outl(omr, DE4X5_OMR); /* Stop everything! */
1446
1447 if (j == 0) {
1448 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1449 inl(DE4X5_STS));
1450 status = -EIO;
1451 }
1452
1453 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1454 lp->tx_old = lp->tx_new;
1455
1456 return status;
1457}
1458
1459/*
1460** Writes a socket buffer address to the next available transmit descriptor.
1461*/
1462static int
1463de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1464{
1465 struct de4x5_private *lp = netdev_priv(dev);
1466 u_long iobase = dev->base_addr;
1467 int status = 0;
1468 u_long flags = 0;
1469
1470 netif_stop_queue(dev);
1471 if (lp->tx_enable == NO) { /* Cannot send for now */
1472 return -1;
1473 }
1474
1475 /*
1476 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1477 ** interrupts are lost by delayed descriptor status updates relative to
1478 ** the irq assertion, especially with a busy PCI bus.
1479 */
1480 spin_lock_irqsave(&lp->lock, flags);
1481 de4x5_tx(dev);
1482 spin_unlock_irqrestore(&lp->lock, flags);
1483
1484 /* Test if cache is already locked - requeue skb if so */
1485 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1486 return -1;
1487
1488 /* Transmit descriptor ring full or stale skb */
1489 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1490 if (lp->interrupt) {
1491 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1492 } else {
1493 de4x5_put_cache(dev, skb);
1494 }
1495 if (de4x5_debug & DEBUG_TX) {
1496 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1497 }
1498 } else if (skb->len > 0) {
1499 /* If we already have stuff queued locally, use that first */
1500 if (lp->cache.skb && !lp->interrupt) {
1501 de4x5_put_cache(dev, skb);
1502 skb = de4x5_get_cache(dev);
1503 }
1504
1505 while (skb && !netif_queue_stopped(dev) &&
1506 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1507 spin_lock_irqsave(&lp->lock, flags);
1508 netif_stop_queue(dev);
1509 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1510 lp->stats.tx_bytes += skb->len;
1511 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1512
1513 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1514 dev->trans_start = jiffies;
1515
1516 if (TX_BUFFS_AVAIL) {
1517 netif_start_queue(dev); /* Another pkt may be queued */
1518 }
1519 skb = de4x5_get_cache(dev);
1520 spin_unlock_irqrestore(&lp->lock, flags);
1521 }
1522 if (skb) de4x5_putb_cache(dev, skb);
1523 }
1524
1525 lp->cache.lock = 0;
1526
1527 return status;
1528}
1529
1530/*
1531** The DE4X5 interrupt handler.
1532**
1533** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1534** so that the asserted interrupt always has some real data to work with -
1535** if these I/O accesses are ever changed to memory accesses, ensure the
1536** STS write is read immediately to complete the transaction if the adapter
1537** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1538** is high and descriptor status bits cannot be set before the associated
1539** interrupt is asserted and this routine entered.
1540*/
1541static irqreturn_t
1542de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1543{
1544 struct net_device *dev = (struct net_device *)dev_id;
1545 struct de4x5_private *lp;
1546 s32 imr, omr, sts, limit;
1547 u_long iobase;
1548 unsigned int handled = 0;
1549
1550 if (dev == NULL) {
1551 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1552 return IRQ_NONE;
1553 }
1554 lp = netdev_priv(dev);
1555 spin_lock(&lp->lock);
1556 iobase = dev->base_addr;
1557
1558 DISABLE_IRQs; /* Ensure non re-entrancy */
1559
1560 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1561 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1562
1563 synchronize_irq(dev->irq);
1564
1565 for (limit=0; limit<8; limit++) {
1566 sts = inl(DE4X5_STS); /* Read IRQ status */
1567 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1568
1569 if (!(sts & lp->irq_mask)) break;/* All done */
1570 handled = 1;
1571
1572 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1573 de4x5_rx(dev);
1574
1575 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1576 de4x5_tx(dev);
1577
1578 if (sts & STS_LNF) { /* TP Link has failed */
1579 lp->irq_mask &= ~IMR_LFM;
1580 }
1581
1582 if (sts & STS_UNF) { /* Transmit underrun */
1583 de4x5_txur(dev);
1584 }
1585
1586 if (sts & STS_SE) { /* Bus Error */
1587 STOP_DE4X5;
1588 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1589 dev->name, sts);
1590 spin_unlock(&lp->lock);
1591 return IRQ_HANDLED;
1592 }
1593 }
1594
1595 /* Load the TX ring with any locally stored packets */
1596 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1597 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1598 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1599 }
1600 lp->cache.lock = 0;
1601 }
1602
1603 lp->interrupt = UNMASK_INTERRUPTS;
1604 ENABLE_IRQs;
1605 spin_unlock(&lp->lock);
1606
1607 return IRQ_RETVAL(handled);
1608}
1609
1610static int
1611de4x5_rx(struct net_device *dev)
1612{
1613 struct de4x5_private *lp = netdev_priv(dev);
1614 u_long iobase = dev->base_addr;
1615 int entry;
1616 s32 status;
1617
1618 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1619 entry=lp->rx_new) {
1620 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1621
1622 if (lp->rx_ovf) {
1623 if (inl(DE4X5_MFC) & MFC_FOCM) {
1624 de4x5_rx_ovfc(dev);
1625 break;
1626 }
1627 }
1628
1629 if (status & RD_FS) { /* Remember the start of frame */
1630 lp->rx_old = entry;
1631 }
1632
1633 if (status & RD_LS) { /* Valid frame status */
1634 if (lp->tx_enable) lp->linkOK++;
1635 if (status & RD_ES) { /* There was an error. */
1636 lp->stats.rx_errors++; /* Update the error stats. */
1637 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1638 if (status & RD_CE) lp->stats.rx_crc_errors++;
1639 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1640 if (status & RD_TL) lp->stats.rx_length_errors++;
1641 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1642 if (status & RD_CS) lp->pktStats.rx_collision++;
1643 if (status & RD_DB) lp->pktStats.rx_dribble++;
1644 if (status & RD_OF) lp->pktStats.rx_overflow++;
1645 } else { /* A valid frame received */
1646 struct sk_buff *skb;
1647 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1648 >> 16) - 4;
1649
1650 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1651 printk("%s: Insufficient memory; nuking packet.\n",
1652 dev->name);
1653 lp->stats.rx_dropped++;
1654 } else {
1655 de4x5_dbg_rx(skb, pkt_len);
1656
1657 /* Push up the protocol stack */
1658 skb->protocol=eth_type_trans(skb,dev);
1659 de4x5_local_stats(dev, skb->data, pkt_len);
1660 netif_rx(skb);
1661
1662 /* Update stats */
1663 dev->last_rx = jiffies;
1664 lp->stats.rx_packets++;
1665 lp->stats.rx_bytes += pkt_len;
1666 }
1667 }
1668
1669 /* Change buffer ownership for this frame, back to the adapter */
1670 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1671 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1672 barrier();
1673 }
1674 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1675 barrier();
1676 }
1677
1678 /*
1679 ** Update entry information
1680 */
1681 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1682 }
1683
1684 return 0;
1685}
1686
1687static inline void
1688de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1689{
1690 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1691 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1692 DMA_TO_DEVICE);
1693 if ((u_long) lp->tx_skb[entry] > 1)
1694 dev_kfree_skb_irq(lp->tx_skb[entry]);
1695 lp->tx_skb[entry] = NULL;
1696}
1697
1698/*
1699** Buffer sent - check for TX buffer errors.
1700*/
1701static int
1702de4x5_tx(struct net_device *dev)
1703{
1704 struct de4x5_private *lp = netdev_priv(dev);
1705 u_long iobase = dev->base_addr;
1706 int entry;
1707 s32 status;
1708
1709 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1710 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1711 if (status < 0) { /* Buffer not sent yet */
1712 break;
1713 } else if (status != 0x7fffffff) { /* Not setup frame */
1714 if (status & TD_ES) { /* An error happened */
1715 lp->stats.tx_errors++;
1716 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1717 if (status & TD_LC) lp->stats.tx_window_errors++;
1718 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1719 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1720 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1721
1722 if (TX_PKT_PENDING) {
1723 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1724 }
1725 } else { /* Packet sent */
1726 lp->stats.tx_packets++;
1727 if (lp->tx_enable) lp->linkOK++;
1728 }
1729 /* Update the collision counter */
1730 lp->stats.collisions += ((status & TD_EC) ? 16 :
1731 ((status & TD_CC) >> 3));
1732
1733 /* Free the buffer. */
1734 if (lp->tx_skb[entry] != NULL)
1735 de4x5_free_tx_buff(lp, entry);
1736 }
1737
1738 /* Update all the pointers */
1739 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1740 }
1741
1742 /* Any resources available? */
1743 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1744 if (lp->interrupt)
1745 netif_wake_queue(dev);
1746 else
1747 netif_start_queue(dev);
1748 }
1749
1750 return 0;
1751}
1752
1753static int
1754de4x5_ast(struct net_device *dev)
1755{
1756 struct de4x5_private *lp = netdev_priv(dev);
1757 int next_tick = DE4X5_AUTOSENSE_MS;
1758
1759 disable_ast(dev);
1760
1761 if (lp->useSROM) {
1762 next_tick = srom_autoconf(dev);
1763 } else if (lp->chipset == DC21140) {
1764 next_tick = dc21140m_autoconf(dev);
1765 } else if (lp->chipset == DC21041) {
1766 next_tick = dc21041_autoconf(dev);
1767 } else if (lp->chipset == DC21040) {
1768 next_tick = dc21040_autoconf(dev);
1769 }
1770 lp->linkOK = 0;
1771 enable_ast(dev, next_tick);
1772
1773 return 0;
1774}
1775
1776static int
1777de4x5_txur(struct net_device *dev)
1778{
1779 struct de4x5_private *lp = netdev_priv(dev);
1780 u_long iobase = dev->base_addr;
1781 int omr;
1782
1783 omr = inl(DE4X5_OMR);
1784 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1785 omr &= ~(OMR_ST|OMR_SR);
1786 outl(omr, DE4X5_OMR);
1787 while (inl(DE4X5_STS) & STS_TS);
1788 if ((omr & OMR_TR) < OMR_TR) {
1789 omr += 0x4000;
1790 } else {
1791 omr |= OMR_SF;
1792 }
1793 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1794 }
1795
1796 return 0;
1797}
1798
1799static int
1800de4x5_rx_ovfc(struct net_device *dev)
1801{
1802 struct de4x5_private *lp = netdev_priv(dev);
1803 u_long iobase = dev->base_addr;
1804 int omr;
1805
1806 omr = inl(DE4X5_OMR);
1807 outl(omr & ~OMR_SR, DE4X5_OMR);
1808 while (inl(DE4X5_STS) & STS_RS);
1809
1810 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1811 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1812 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1813 }
1814
1815 outl(omr, DE4X5_OMR);
1816
1817 return 0;
1818}
1819
1820static int
1821de4x5_close(struct net_device *dev)
1822{
1823 struct de4x5_private *lp = netdev_priv(dev);
1824 u_long iobase = dev->base_addr;
1825 s32 imr, omr;
1826
1827 disable_ast(dev);
1828
1829 netif_stop_queue(dev);
1830
1831 if (de4x5_debug & DEBUG_CLOSE) {
1832 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1833 dev->name, inl(DE4X5_STS));
1834 }
1835
1836 /*
1837 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1838 */
1839 DISABLE_IRQs;
1840 STOP_DE4X5;
1841
1842 /* Free the associated irq */
1843 free_irq(dev->irq, dev);
1844 lp->state = CLOSED;
1845
1846 /* Free any socket buffers */
1847 de4x5_free_rx_buffs(dev);
1848 de4x5_free_tx_buffs(dev);
1849
1850 /* Put the adapter to sleep to save power */
1851 yawn(dev, SLEEP);
1852
1853 return 0;
1854}
1855
1856static struct net_device_stats *
1857de4x5_get_stats(struct net_device *dev)
1858{
1859 struct de4x5_private *lp = netdev_priv(dev);
1860 u_long iobase = dev->base_addr;
1861
1862 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1863
1864 return &lp->stats;
1865}
1866
1867static void
1868de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1869{
1870 struct de4x5_private *lp = netdev_priv(dev);
1871 int i;
1872
1873 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1874 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1875 lp->pktStats.bins[i]++;
1876 i = DE4X5_PKT_STAT_SZ;
1877 }
1878 }
1879 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1880 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1881 lp->pktStats.broadcast++;
1882 } else {
1883 lp->pktStats.multicast++;
1884 }
1885 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1886 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1887 lp->pktStats.unicast++;
1888 }
1889
1890 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1891 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1892 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1893 }
1894
1895 return;
1896}
1897
1898/*
1899** Removes the TD_IC flag from previous descriptor to improve TX performance.
1900** If the flag is changed on a descriptor that is being read by the hardware,
1901** I assume PCI transaction ordering will mean you are either successful or
1902** just miss asserting the change to the hardware. Anyway you're messing with
1903** a descriptor you don't own, but this shouldn't kill the chip provided
1904** the descriptor register is read only to the hardware.
1905*/
1906static void
1907load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1908{
1909 struct de4x5_private *lp = netdev_priv(dev);
1910 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1911 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1912
1913 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1914 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1915 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1916 lp->tx_skb[lp->tx_new] = skb;
1917 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1918 barrier();
1919
1920 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1921 barrier();
1922}
1923
1924/*
1925** Set or clear the multicast filter for this adaptor.
1926*/
1927static void
1928set_multicast_list(struct net_device *dev)
1929{
1930 struct de4x5_private *lp = netdev_priv(dev);
1931 u_long iobase = dev->base_addr;
1932
1933 /* First, double check that the adapter is open */
1934 if (lp->state == OPEN) {
1935 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1936 u32 omr;
1937 omr = inl(DE4X5_OMR);
1938 omr |= OMR_PR;
1939 outl(omr, DE4X5_OMR);
1940 } else {
1941 SetMulticastFilter(dev);
1942 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1943 SETUP_FRAME_LEN, (struct sk_buff *)1);
1944
1945 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1946 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1947 dev->trans_start = jiffies;
1948 }
1949 }
1950}
1951
1952/*
1953** Calculate the hash code and update the logical address filter
1954** from a list of ethernet multicast addresses.
1955** Little endian crc one liner from Matt Thomas, DEC.
1956*/
1957static void
1958SetMulticastFilter(struct net_device *dev)
1959{
1960 struct de4x5_private *lp = netdev_priv(dev);
1961 struct dev_mc_list *dmi=dev->mc_list;
1962 u_long iobase = dev->base_addr;
1963 int i, j, bit, byte;
1964 u16 hashcode;
1965 u32 omr, crc;
1966 char *pa;
1967 unsigned char *addrs;
1968
1969 omr = inl(DE4X5_OMR);
1970 omr &= ~(OMR_PR | OMR_PM);
1971 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1972
1973 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1974 omr |= OMR_PM; /* Pass all multicasts */
1975 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1976 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1977 addrs=dmi->dmi_addr;
1978 dmi=dmi->next;
1979 if ((*addrs & 0x01) == 1) { /* multicast address? */
1980 crc = ether_crc_le(ETH_ALEN, addrs);
1981 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1982
1983 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1984 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1985
1986 byte <<= 1; /* calc offset into setup frame */
1987 if (byte & 0x02) {
1988 byte -= 1;
1989 }
1990 lp->setup_frame[byte] |= bit;
1991 }
1992 }
1993 } else { /* Perfect filtering */
1994 for (j=0; j<dev->mc_count; j++) {
1995 addrs=dmi->dmi_addr;
1996 dmi=dmi->next;
1997 for (i=0; i<ETH_ALEN; i++) {
1998 *(pa + (i&1)) = *addrs++;
1999 if (i & 0x01) pa += 4;
2000 }
2001 }
2002 }
2003 outl(omr, DE4X5_OMR);
2004
2005 return;
2006}
2007
2008#ifdef CONFIG_EISA
2009
2010static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2011
2012static int __init de4x5_eisa_probe (struct device *gendev)
2013{
2014 struct eisa_device *edev;
2015 u_long iobase;
2016 u_char irq, regval;
2017 u_short vendor;
2018 u32 cfid;
2019 int status, device;
2020 struct net_device *dev;
2021 struct de4x5_private *lp;
2022
2023 edev = to_eisa_device (gendev);
2024 iobase = edev->base_addr;
2025
2026 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2027 return -EBUSY;
2028
2029 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2030 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2031 status = -EBUSY;
2032 goto release_reg_1;
2033 }
2034
2035 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2036 status = -ENOMEM;
2037 goto release_reg_2;
2038 }
2039 lp = netdev_priv(dev);
2040
2041 cfid = (u32) inl(PCI_CFID);
2042 lp->cfrv = (u_short) inl(PCI_CFRV);
2043 device = (cfid >> 8) & 0x00ffff00;
2044 vendor = (u_short) cfid;
2045
2046 /* Read the EISA Configuration Registers */
2047 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2048#ifdef CONFIG_ALPHA
2049 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2050 * care about the EISA configuration, and thus doesn't
2051 * configure the PLX bridge properly. Oh well... Simply mimic
2052 * the EISA config file to sort it out. */
2053
2054 /* EISA REG1: Assert DecChip 21040 HW Reset */
2055 outb (ER1_IAM | 1, EISA_REG1);
2056 mdelay (1);
2057
2058 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2059 outb (ER1_IAM, EISA_REG1);
2060 mdelay (1);
2061
2062 /* EISA REG3: R/W Burst Transfer Enable */
2063 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2064
2065 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2066 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2067#endif
2068 irq = de4x5_irq[(regval >> 1) & 0x03];
2069
2070 if (is_DC2114x) {
2071 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2072 }
2073 lp->chipset = device;
2074 lp->bus = EISA;
2075
2076 /* Write the PCI Configuration Registers */
2077 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2078 outl(0x00006000, PCI_CFLT);
2079 outl(iobase, PCI_CBIO);
2080
2081 DevicePresent(dev, EISA_APROM);
2082
2083 dev->irq = irq;
2084
2085 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2086 return 0;
2087 }
2088
2089 free_netdev (dev);
2090 release_reg_2:
2091 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2092 release_reg_1:
2093 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2094
2095 return status;
2096}
2097
2098static int __devexit de4x5_eisa_remove (struct device *device)
2099{
2100 struct net_device *dev;
2101 u_long iobase;
2102
2103 dev = device->driver_data;
2104 iobase = dev->base_addr;
2105
2106 unregister_netdev (dev);
2107 free_netdev (dev);
2108 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2109 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2110
2111 return 0;
2112}
2113
2114static struct eisa_device_id de4x5_eisa_ids[] = {
2115 { "DEC4250", 0 }, /* 0 is the board name index... */
2116 { "" }
2117};
2118
2119static struct eisa_driver de4x5_eisa_driver = {
2120 .id_table = de4x5_eisa_ids,
2121 .driver = {
2122 .name = "de4x5",
2123 .probe = de4x5_eisa_probe,
2124 .remove = __devexit_p (de4x5_eisa_remove),
2125 }
2126};
2127MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2128#endif
2129
2130#ifdef CONFIG_PCI
2131
2132/*
2133** This function searches the current bus (which is >0) for a DECchip with an
2134** SROM, so that in multiport cards that have one SROM shared between multiple
2135** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2136** For single port cards this is a time waster...
2137*/
2138static void __devinit
2139srom_search(struct net_device *dev, struct pci_dev *pdev)
2140{
2141 u_char pb;
2142 u_short vendor, status;
2143 u_int irq = 0, device;
2144 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2145 int i, j, cfrv;
2146 struct de4x5_private *lp = netdev_priv(dev);
2147 struct list_head *walk = &pdev->bus_list;
2148
2149 for (walk = walk->next; walk != &pdev->bus_list; walk = walk->next) {
2150 struct pci_dev *this_dev = pci_dev_b(walk);
2151
2152 /* Skip the pci_bus list entry */
2153 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2154
2155 vendor = this_dev->vendor;
2156 device = this_dev->device << 8;
2157 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2158
2159 /* Get the chip configuration revision register */
2160 pb = this_dev->bus->number;
2161 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2162
2163 /* Set the device number information */
2164 lp->device = PCI_SLOT(this_dev->devfn);
2165 lp->bus_num = pb;
2166
2167 /* Set the chipset information */
2168 if (is_DC2114x) {
2169 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2170 }
2171 lp->chipset = device;
2172
2173 /* Get the board I/O address (64 bits on sparc64) */
2174 iobase = pci_resource_start(this_dev, 0);
2175
2176 /* Fetch the IRQ to be used */
2177 irq = this_dev->irq;
2178 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2179
2180 /* Check if I/O accesses are enabled */
2181 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2182 if (!(status & PCI_COMMAND_IO)) continue;
2183
2184 /* Search for a valid SROM attached to this DECchip */
2185 DevicePresent(dev, DE4X5_APROM);
2186 for (j=0, i=0; i<ETH_ALEN; i++) {
2187 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2188 }
2189 if ((j != 0) && (j != 0x5fa)) {
2190 last.chipset = device;
2191 last.bus = pb;
2192 last.irq = irq;
2193 for (i=0; i<ETH_ALEN; i++) {
2194 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2195 }
2196 return;
2197 }
2198 }
2199
2200 return;
2201}
2202
2203/*
2204** PCI bus I/O device probe
2205** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2206** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2207** enabled by the user first in the set up utility. Hence we just check for
2208** enabled features and silently ignore the card if they're not.
2209**
2210** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2211** bit. Here, check for I/O accesses and then set BM. If you put the card in
2212** a non BM slot, you're on your own (and complain to the PC vendor that your
2213** PC doesn't conform to the PCI standard)!
2214**
2215** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2216** kernels use the V0.535[n] drivers.
2217*/
2218
2219static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2220 const struct pci_device_id *ent)
2221{
2222 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2223 u_short vendor, status;
2224 u_int irq = 0, device;
2225 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2226 int error;
2227 struct net_device *dev;
2228 struct de4x5_private *lp;
2229
2230 dev_num = PCI_SLOT(pdev->devfn);
2231 pb = pdev->bus->number;
2232
2233 if (io) { /* probe a single PCI device */
2234 pbus = (u_short)(io >> 8);
2235 dnum = (u_short)(io & 0xff);
2236 if ((pbus != pb) || (dnum != dev_num))
2237 return -ENODEV;
2238 }
2239
2240 vendor = pdev->vendor;
2241 device = pdev->device << 8;
2242 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2243 return -ENODEV;
2244
2245 /* Ok, the device seems to be for us. */
2246 if ((error = pci_enable_device (pdev)))
2247 return error;
2248
2249 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2250 error = -ENOMEM;
2251 goto disable_dev;
2252 }
2253
2254 lp = netdev_priv(dev);
2255 lp->bus = PCI;
2256 lp->bus_num = 0;
2257
2258 /* Search for an SROM on this bus */
2259 if (lp->bus_num != pb) {
2260 lp->bus_num = pb;
2261 srom_search(dev, pdev);
2262 }
2263
2264 /* Get the chip configuration revision register */
2265 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2266
2267 /* Set the device number information */
2268 lp->device = dev_num;
2269 lp->bus_num = pb;
2270
2271 /* Set the chipset information */
2272 if (is_DC2114x) {
2273 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2274 }
2275 lp->chipset = device;
2276
2277 /* Get the board I/O address (64 bits on sparc64) */
2278 iobase = pci_resource_start(pdev, 0);
2279
2280 /* Fetch the IRQ to be used */
2281 irq = pdev->irq;
2282 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2283 error = -ENODEV;
2284 goto free_dev;
2285 }
2286
2287 /* Check if I/O accesses and Bus Mastering are enabled */
2288 pci_read_config_word(pdev, PCI_COMMAND, &status);
2289#ifdef __powerpc__
2290 if (!(status & PCI_COMMAND_IO)) {
2291 status |= PCI_COMMAND_IO;
2292 pci_write_config_word(pdev, PCI_COMMAND, status);
2293 pci_read_config_word(pdev, PCI_COMMAND, &status);
2294 }
2295#endif /* __powerpc__ */
2296 if (!(status & PCI_COMMAND_IO)) {
2297 error = -ENODEV;
2298 goto free_dev;
2299 }
2300
2301 if (!(status & PCI_COMMAND_MASTER)) {
2302 status |= PCI_COMMAND_MASTER;
2303 pci_write_config_word(pdev, PCI_COMMAND, status);
2304 pci_read_config_word(pdev, PCI_COMMAND, &status);
2305 }
2306 if (!(status & PCI_COMMAND_MASTER)) {
2307 error = -ENODEV;
2308 goto free_dev;
2309 }
2310
2311 /* Check the latency timer for values >= 0x60 */
2312 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2313 if (timer < 0x60) {
2314 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2315 }
2316
2317 DevicePresent(dev, DE4X5_APROM);
2318
2319 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2320 error = -EBUSY;
2321 goto free_dev;
2322 }
2323
2324 dev->irq = irq;
2325
2326 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2327 goto release;
2328 }
2329
2330 return 0;
2331
2332 release:
2333 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2334 free_dev:
2335 free_netdev (dev);
2336 disable_dev:
2337 pci_disable_device (pdev);
2338 return error;
2339}
2340
2341static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2342{
2343 struct net_device *dev;
2344 u_long iobase;
2345
2346 dev = pdev->dev.driver_data;
2347 iobase = dev->base_addr;
2348
2349 unregister_netdev (dev);
2350 free_netdev (dev);
2351 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2352 pci_disable_device (pdev);
2353}
2354
2355static struct pci_device_id de4x5_pci_tbl[] = {
2356 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2358 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2360 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2362 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2364 { },
2365};
2366
2367static struct pci_driver de4x5_pci_driver = {
2368 .name = "de4x5",
2369 .id_table = de4x5_pci_tbl,
2370 .probe = de4x5_pci_probe,
2371 .remove = __devexit_p (de4x5_pci_remove),
2372};
2373
2374#endif
2375
2376/*
2377** Auto configure the media here rather than setting the port at compile
2378** time. This routine is called by de4x5_init() and when a loss of media is
2379** detected (excessive collisions, loss of carrier, no carrier or link fail
2380** [TP] or no recent receive activity) to check whether the user has been
2381** sneaky and changed the port on us.
2382*/
2383static int
2384autoconf_media(struct net_device *dev)
2385{
2386 struct de4x5_private *lp = netdev_priv(dev);
2387 u_long iobase = dev->base_addr;
2388 int next_tick = DE4X5_AUTOSENSE_MS;
2389
2390 lp->linkOK = 0;
2391 lp->c_media = AUTO; /* Bogus last media */
2392 disable_ast(dev);
2393 inl(DE4X5_MFC); /* Zero the lost frames counter */
2394 lp->media = INIT;
2395 lp->tcount = 0;
2396
2397 if (lp->useSROM) {
2398 next_tick = srom_autoconf(dev);
2399 } else if (lp->chipset == DC21040) {
2400 next_tick = dc21040_autoconf(dev);
2401 } else if (lp->chipset == DC21041) {
2402 next_tick = dc21041_autoconf(dev);
2403 } else if (lp->chipset == DC21140) {
2404 next_tick = dc21140m_autoconf(dev);
2405 }
2406
2407 enable_ast(dev, next_tick);
2408
2409 return (lp->media);
2410}
2411
2412/*
2413** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2414** from BNC as the port has a jumper to set thick or thin wire. When set for
2415** BNC, the BNC port will indicate activity if it's not terminated correctly.
2416** The only way to test for that is to place a loopback packet onto the
2417** network and watch for errors. Since we're messing with the interrupt mask
2418** register, disable the board interrupts and do not allow any more packets to
2419** be queued to the hardware. Re-enable everything only when the media is
2420** found.
2421** I may have to "age out" locally queued packets so that the higher layer
2422** timeouts don't effectively duplicate packets on the network.
2423*/
2424static int
2425dc21040_autoconf(struct net_device *dev)
2426{
2427 struct de4x5_private *lp = netdev_priv(dev);
2428 u_long iobase = dev->base_addr;
2429 int next_tick = DE4X5_AUTOSENSE_MS;
2430 s32 imr;
2431
2432 switch (lp->media) {
2433 case INIT:
2434 DISABLE_IRQs;
2435 lp->tx_enable = NO;
2436 lp->timeout = -1;
2437 de4x5_save_skbs(dev);
2438 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2439 lp->media = TP;
2440 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2441 lp->media = BNC_AUI;
2442 } else if (lp->autosense == EXT_SIA) {
2443 lp->media = EXT_SIA;
2444 } else {
2445 lp->media = NC;
2446 }
2447 lp->local_state = 0;
2448 next_tick = dc21040_autoconf(dev);
2449 break;
2450
2451 case TP:
2452 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2453 TP_SUSPECT, test_tp);
2454 break;
2455
2456 case TP_SUSPECT:
2457 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2458 break;
2459
2460 case BNC:
2461 case AUI:
2462 case BNC_AUI:
2463 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2464 BNC_AUI_SUSPECT, ping_media);
2465 break;
2466
2467 case BNC_AUI_SUSPECT:
2468 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2469 break;
2470
2471 case EXT_SIA:
2472 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2473 NC, EXT_SIA_SUSPECT, ping_media);
2474 break;
2475
2476 case EXT_SIA_SUSPECT:
2477 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2478 break;
2479
2480 case NC:
2481 /* default to TP for all */
2482 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2483 if (lp->media != lp->c_media) {
2484 de4x5_dbg_media(dev);
2485 lp->c_media = lp->media;
2486 }
2487 lp->media = INIT;
2488 lp->tx_enable = NO;
2489 break;
2490 }
2491
2492 return next_tick;
2493}
2494
2495static int
2496dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2497 int next_state, int suspect_state,
2498 int (*fn)(struct net_device *, int))
2499{
2500 struct de4x5_private *lp = netdev_priv(dev);
2501 int next_tick = DE4X5_AUTOSENSE_MS;
2502 int linkBad;
2503
2504 switch (lp->local_state) {
2505 case 0:
2506 reset_init_sia(dev, csr13, csr14, csr15);
2507 lp->local_state++;
2508 next_tick = 500;
2509 break;
2510
2511 case 1:
2512 if (!lp->tx_enable) {
2513 linkBad = fn(dev, timeout);
2514 if (linkBad < 0) {
2515 next_tick = linkBad & ~TIMER_CB;
2516 } else {
2517 if (linkBad && (lp->autosense == AUTO)) {
2518 lp->local_state = 0;
2519 lp->media = next_state;
2520 } else {
2521 de4x5_init_connection(dev);
2522 }
2523 }
2524 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2525 lp->media = suspect_state;
2526 next_tick = 3000;
2527 }
2528 break;
2529 }
2530
2531 return next_tick;
2532}
2533
2534static int
2535de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2536 int (*fn)(struct net_device *, int),
2537 int (*asfn)(struct net_device *))
2538{
2539 struct de4x5_private *lp = netdev_priv(dev);
2540 int next_tick = DE4X5_AUTOSENSE_MS;
2541 int linkBad;
2542
2543 switch (lp->local_state) {
2544 case 1:
2545 if (lp->linkOK) {
2546 lp->media = prev_state;
2547 } else {
2548 lp->local_state++;
2549 next_tick = asfn(dev);
2550 }
2551 break;
2552
2553 case 2:
2554 linkBad = fn(dev, timeout);
2555 if (linkBad < 0) {
2556 next_tick = linkBad & ~TIMER_CB;
2557 } else if (!linkBad) {
2558 lp->local_state--;
2559 lp->media = prev_state;
2560 } else {
2561 lp->media = INIT;
2562 lp->tcount++;
2563 }
2564 }
2565
2566 return next_tick;
2567}
2568
2569/*
2570** Autoconfigure the media when using the DC21041. AUI needs to be tested
2571** before BNC, because the BNC port will indicate activity if it's not
2572** terminated correctly. The only way to test for that is to place a loopback
2573** packet onto the network and watch for errors. Since we're messing with
2574** the interrupt mask register, disable the board interrupts and do not allow
2575** any more packets to be queued to the hardware. Re-enable everything only
2576** when the media is found.
2577*/
2578static int
2579dc21041_autoconf(struct net_device *dev)
2580{
2581 struct de4x5_private *lp = netdev_priv(dev);
2582 u_long iobase = dev->base_addr;
2583 s32 sts, irqs, irq_mask, imr, omr;
2584 int next_tick = DE4X5_AUTOSENSE_MS;
2585
2586 switch (lp->media) {
2587 case INIT:
2588 DISABLE_IRQs;
2589 lp->tx_enable = NO;
2590 lp->timeout = -1;
2591 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2592 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2593 lp->media = TP; /* On chip auto negotiation is broken */
2594 } else if (lp->autosense == TP) {
2595 lp->media = TP;
2596 } else if (lp->autosense == BNC) {
2597 lp->media = BNC;
2598 } else if (lp->autosense == AUI) {
2599 lp->media = AUI;
2600 } else {
2601 lp->media = NC;
2602 }
2603 lp->local_state = 0;
2604 next_tick = dc21041_autoconf(dev);
2605 break;
2606
2607 case TP_NW:
2608 if (lp->timeout < 0) {
2609 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2610 outl(omr | OMR_FDX, DE4X5_OMR);
2611 }
2612 irqs = STS_LNF | STS_LNP;
2613 irq_mask = IMR_LFM | IMR_LPM;
2614 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2615 if (sts < 0) {
2616 next_tick = sts & ~TIMER_CB;
2617 } else {
2618 if (sts & STS_LNP) {
2619 lp->media = ANS;
2620 } else {
2621 lp->media = AUI;
2622 }
2623 next_tick = dc21041_autoconf(dev);
2624 }
2625 break;
2626
2627 case ANS:
2628 if (!lp->tx_enable) {
2629 irqs = STS_LNP;
2630 irq_mask = IMR_LPM;
2631 sts = test_ans(dev, irqs, irq_mask, 3000);
2632 if (sts < 0) {
2633 next_tick = sts & ~TIMER_CB;
2634 } else {
2635 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2636 lp->media = TP;
2637 next_tick = dc21041_autoconf(dev);
2638 } else {
2639 lp->local_state = 1;
2640 de4x5_init_connection(dev);
2641 }
2642 }
2643 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2644 lp->media = ANS_SUSPECT;
2645 next_tick = 3000;
2646 }
2647 break;
2648
2649 case ANS_SUSPECT:
2650 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2651 break;
2652
2653 case TP:
2654 if (!lp->tx_enable) {
2655 if (lp->timeout < 0) {
2656 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2657 outl(omr & ~OMR_FDX, DE4X5_OMR);
2658 }
2659 irqs = STS_LNF | STS_LNP;
2660 irq_mask = IMR_LFM | IMR_LPM;
2661 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2662 if (sts < 0) {
2663 next_tick = sts & ~TIMER_CB;
2664 } else {
2665 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2666 if (inl(DE4X5_SISR) & SISR_NRA) {
2667 lp->media = AUI; /* Non selected port activity */
2668 } else {
2669 lp->media = BNC;
2670 }
2671 next_tick = dc21041_autoconf(dev);
2672 } else {
2673 lp->local_state = 1;
2674 de4x5_init_connection(dev);
2675 }
2676 }
2677 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2678 lp->media = TP_SUSPECT;
2679 next_tick = 3000;
2680 }
2681 break;
2682
2683 case TP_SUSPECT:
2684 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2685 break;
2686
2687 case AUI:
2688 if (!lp->tx_enable) {
2689 if (lp->timeout < 0) {
2690 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2691 outl(omr & ~OMR_FDX, DE4X5_OMR);
2692 }
2693 irqs = 0;
2694 irq_mask = 0;
2695 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2696 if (sts < 0) {
2697 next_tick = sts & ~TIMER_CB;
2698 } else {
2699 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2700 lp->media = BNC;
2701 next_tick = dc21041_autoconf(dev);
2702 } else {
2703 lp->local_state = 1;
2704 de4x5_init_connection(dev);
2705 }
2706 }
2707 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2708 lp->media = AUI_SUSPECT;
2709 next_tick = 3000;
2710 }
2711 break;
2712
2713 case AUI_SUSPECT:
2714 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2715 break;
2716
2717 case BNC:
2718 switch (lp->local_state) {
2719 case 0:
2720 if (lp->timeout < 0) {
2721 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2722 outl(omr & ~OMR_FDX, DE4X5_OMR);
2723 }
2724 irqs = 0;
2725 irq_mask = 0;
2726 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2727 if (sts < 0) {
2728 next_tick = sts & ~TIMER_CB;
2729 } else {
2730 lp->local_state++; /* Ensure media connected */
2731 next_tick = dc21041_autoconf(dev);
2732 }
2733 break;
2734
2735 case 1:
2736 if (!lp->tx_enable) {
2737 if ((sts = ping_media(dev, 3000)) < 0) {
2738 next_tick = sts & ~TIMER_CB;
2739 } else {
2740 if (sts) {
2741 lp->local_state = 0;
2742 lp->media = NC;
2743 } else {
2744 de4x5_init_connection(dev);
2745 }
2746 }
2747 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2748 lp->media = BNC_SUSPECT;
2749 next_tick = 3000;
2750 }
2751 break;
2752 }
2753 break;
2754
2755 case BNC_SUSPECT:
2756 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2757 break;
2758
2759 case NC:
2760 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2761 outl(omr | OMR_FDX, DE4X5_OMR);
2762 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2763 if (lp->media != lp->c_media) {
2764 de4x5_dbg_media(dev);
2765 lp->c_media = lp->media;
2766 }
2767 lp->media = INIT;
2768 lp->tx_enable = NO;
2769 break;
2770 }
2771
2772 return next_tick;
2773}
2774
2775/*
2776** Some autonegotiation chips are broken in that they do not return the
2777** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2778** register, except at the first power up negotiation.
2779*/
2780static int
2781dc21140m_autoconf(struct net_device *dev)
2782{
2783 struct de4x5_private *lp = netdev_priv(dev);
2784 int ana, anlpa, cap, cr, slnk, sr;
2785 int next_tick = DE4X5_AUTOSENSE_MS;
2786 u_long imr, omr, iobase = dev->base_addr;
2787
2788 switch(lp->media) {
2789 case INIT:
2790 if (lp->timeout < 0) {
2791 DISABLE_IRQs;
2792 lp->tx_enable = FALSE;
2793 lp->linkOK = 0;
2794 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2795 }
2796 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2797 next_tick &= ~TIMER_CB;
2798 } else {
2799 if (lp->useSROM) {
2800 if (srom_map_media(dev) < 0) {
2801 lp->tcount++;
2802 return next_tick;
2803 }
2804 srom_exec(dev, lp->phy[lp->active].gep);
2805 if (lp->infoblock_media == ANS) {
2806 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2807 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2808 }
2809 } else {
2810 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2811 SET_10Mb;
2812 if (lp->autosense == _100Mb) {
2813 lp->media = _100Mb;
2814 } else if (lp->autosense == _10Mb) {
2815 lp->media = _10Mb;
2816 } else if ((lp->autosense == AUTO) &&
2817 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2818 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2819 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2820 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2821 lp->media = ANS;
2822 } else if (lp->autosense == AUTO) {
2823 lp->media = SPD_DET;
2824 } else if (is_spd_100(dev) && is_100_up(dev)) {
2825 lp->media = _100Mb;
2826 } else {
2827 lp->media = NC;
2828 }
2829 }
2830 lp->local_state = 0;
2831 next_tick = dc21140m_autoconf(dev);
2832 }
2833 break;
2834
2835 case ANS:
2836 switch (lp->local_state) {
2837 case 0:
2838 if (lp->timeout < 0) {
2839 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2840 }
2841 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2842 if (cr < 0) {
2843 next_tick = cr & ~TIMER_CB;
2844 } else {
2845 if (cr) {
2846 lp->local_state = 0;
2847 lp->media = SPD_DET;
2848 } else {
2849 lp->local_state++;
2850 }
2851 next_tick = dc21140m_autoconf(dev);
2852 }
2853 break;
2854
2855 case 1:
2856 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2857 next_tick = sr & ~TIMER_CB;
2858 } else {
2859 lp->media = SPD_DET;
2860 lp->local_state = 0;
2861 if (sr) { /* Success! */
2862 lp->tmp = MII_SR_ASSC;
2863 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2864 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2865 if (!(anlpa & MII_ANLPA_RF) &&
2866 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2867 if (cap & MII_ANA_100M) {
2868 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2869 lp->media = _100Mb;
2870 } else if (cap & MII_ANA_10M) {
2871 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2872
2873 lp->media = _10Mb;
2874 }
2875 }
2876 } /* Auto Negotiation failed to finish */
2877 next_tick = dc21140m_autoconf(dev);
2878 } /* Auto Negotiation failed to start */
2879 break;
2880 }
2881 break;
2882
2883 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2884 if (lp->timeout < 0) {
2885 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2886 (~gep_rd(dev) & GEP_LNP));
2887 SET_100Mb_PDET;
2888 }
2889 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2890 next_tick = slnk & ~TIMER_CB;
2891 } else {
2892 if (is_spd_100(dev) && is_100_up(dev)) {
2893 lp->media = _100Mb;
2894 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2895 lp->media = _10Mb;
2896 } else {
2897 lp->media = NC;
2898 }
2899 next_tick = dc21140m_autoconf(dev);
2900 }
2901 break;
2902
2903 case _100Mb: /* Set 100Mb/s */
2904 next_tick = 3000;
2905 if (!lp->tx_enable) {
2906 SET_100Mb;
2907 de4x5_init_connection(dev);
2908 } else {
2909 if (!lp->linkOK && (lp->autosense == AUTO)) {
2910 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2911 lp->media = INIT;
2912 lp->tcount++;
2913 next_tick = DE4X5_AUTOSENSE_MS;
2914 }
2915 }
2916 }
2917 break;
2918
2919 case BNC:
2920 case AUI:
2921 case _10Mb: /* Set 10Mb/s */
2922 next_tick = 3000;
2923 if (!lp->tx_enable) {
2924 SET_10Mb;
2925 de4x5_init_connection(dev);
2926 } else {
2927 if (!lp->linkOK && (lp->autosense == AUTO)) {
2928 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2929 lp->media = INIT;
2930 lp->tcount++;
2931 next_tick = DE4X5_AUTOSENSE_MS;
2932 }
2933 }
2934 }
2935 break;
2936
2937 case NC:
2938 if (lp->media != lp->c_media) {
2939 de4x5_dbg_media(dev);
2940 lp->c_media = lp->media;
2941 }
2942 lp->media = INIT;
2943 lp->tx_enable = FALSE;
2944 break;
2945 }
2946
2947 return next_tick;
2948}
2949
2950/*
2951** This routine may be merged into dc21140m_autoconf() sometime as I'm
2952** changing how I figure out the media - but trying to keep it backwards
2953** compatible with the de500-xa and de500-aa.
2954** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2955** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2956** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2957** active.
2958** When autonegotiation is working, the ANS part searches the SROM for
2959** the highest common speed (TP) link that both can run and if that can
2960** be full duplex. That infoblock is executed and then the link speed set.
2961**
2962** Only _10Mb and _100Mb are tested here.
2963*/
2964static int
2965dc2114x_autoconf(struct net_device *dev)
2966{
2967 struct de4x5_private *lp = netdev_priv(dev);
2968 u_long iobase = dev->base_addr;
2969 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2970 int next_tick = DE4X5_AUTOSENSE_MS;
2971
2972 switch (lp->media) {
2973 case INIT:
2974 if (lp->timeout < 0) {
2975 DISABLE_IRQs;
2976 lp->tx_enable = FALSE;
2977 lp->linkOK = 0;
2978 lp->timeout = -1;
2979 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2980 if (lp->params.autosense & ~AUTO) {
2981 srom_map_media(dev); /* Fixed media requested */
2982 if (lp->media != lp->params.autosense) {
2983 lp->tcount++;
2984 lp->media = INIT;
2985 return next_tick;
2986 }
2987 lp->media = INIT;
2988 }
2989 }
2990 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2991 next_tick &= ~TIMER_CB;
2992 } else {
2993 if (lp->autosense == _100Mb) {
2994 lp->media = _100Mb;
2995 } else if (lp->autosense == _10Mb) {
2996 lp->media = _10Mb;
2997 } else if (lp->autosense == TP) {
2998 lp->media = TP;
2999 } else if (lp->autosense == BNC) {
3000 lp->media = BNC;
3001 } else if (lp->autosense == AUI) {
3002 lp->media = AUI;
3003 } else {
3004 lp->media = SPD_DET;
3005 if ((lp->infoblock_media == ANS) &&
3006 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3007 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3008 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3009 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3010 lp->media = ANS;
3011 }
3012 }
3013 lp->local_state = 0;
3014 next_tick = dc2114x_autoconf(dev);
3015 }
3016 break;
3017
3018 case ANS:
3019 switch (lp->local_state) {
3020 case 0:
3021 if (lp->timeout < 0) {
3022 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3023 }
3024 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3025 if (cr < 0) {
3026 next_tick = cr & ~TIMER_CB;
3027 } else {
3028 if (cr) {
3029 lp->local_state = 0;
3030 lp->media = SPD_DET;
3031 } else {
3032 lp->local_state++;
3033 }
3034 next_tick = dc2114x_autoconf(dev);
3035 }
3036 break;
3037
3038 case 1:
3039 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3040 next_tick = sr & ~TIMER_CB;
3041 } else {
3042 lp->media = SPD_DET;
3043 lp->local_state = 0;
3044 if (sr) { /* Success! */
3045 lp->tmp = MII_SR_ASSC;
3046 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3047 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3048 if (!(anlpa & MII_ANLPA_RF) &&
3049 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3050 if (cap & MII_ANA_100M) {
3051 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3052 lp->media = _100Mb;
3053 } else if (cap & MII_ANA_10M) {
3054 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3055 lp->media = _10Mb;
3056 }
3057 }
3058 } /* Auto Negotiation failed to finish */
3059 next_tick = dc2114x_autoconf(dev);
3060 } /* Auto Negotiation failed to start */
3061 break;
3062 }
3063 break;
3064
3065 case AUI:
3066 if (!lp->tx_enable) {
3067 if (lp->timeout < 0) {
3068 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3069 outl(omr & ~OMR_FDX, DE4X5_OMR);
3070 }
3071 irqs = 0;
3072 irq_mask = 0;
3073 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3074 if (sts < 0) {
3075 next_tick = sts & ~TIMER_CB;
3076 } else {
3077 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3078 lp->media = BNC;
3079 next_tick = dc2114x_autoconf(dev);
3080 } else {
3081 lp->local_state = 1;
3082 de4x5_init_connection(dev);
3083 }
3084 }
3085 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3086 lp->media = AUI_SUSPECT;
3087 next_tick = 3000;
3088 }
3089 break;
3090
3091 case AUI_SUSPECT:
3092 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3093 break;
3094
3095 case BNC:
3096 switch (lp->local_state) {
3097 case 0:
3098 if (lp->timeout < 0) {
3099 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3100 outl(omr & ~OMR_FDX, DE4X5_OMR);
3101 }
3102 irqs = 0;
3103 irq_mask = 0;
3104 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3105 if (sts < 0) {
3106 next_tick = sts & ~TIMER_CB;
3107 } else {
3108 lp->local_state++; /* Ensure media connected */
3109 next_tick = dc2114x_autoconf(dev);
3110 }
3111 break;
3112
3113 case 1:
3114 if (!lp->tx_enable) {
3115 if ((sts = ping_media(dev, 3000)) < 0) {
3116 next_tick = sts & ~TIMER_CB;
3117 } else {
3118 if (sts) {
3119 lp->local_state = 0;
3120 lp->tcount++;
3121 lp->media = INIT;
3122 } else {
3123 de4x5_init_connection(dev);
3124 }
3125 }
3126 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3127 lp->media = BNC_SUSPECT;
3128 next_tick = 3000;
3129 }
3130 break;
3131 }
3132 break;
3133
3134 case BNC_SUSPECT:
3135 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3136 break;
3137
3138 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3139 if (srom_map_media(dev) < 0) {
3140 lp->tcount++;
3141 lp->media = INIT;
3142 return next_tick;
3143 }
3144 if (lp->media == _100Mb) {
3145 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3146 lp->media = SPD_DET;
3147 return (slnk & ~TIMER_CB);
3148 }
3149 } else {
3150 if (wait_for_link(dev) < 0) {
3151 lp->media = SPD_DET;
3152 return PDET_LINK_WAIT;
3153 }
3154 }
3155 if (lp->media == ANS) { /* Do MII parallel detection */
3156 if (is_spd_100(dev)) {
3157 lp->media = _100Mb;
3158 } else {
3159 lp->media = _10Mb;
3160 }
3161 next_tick = dc2114x_autoconf(dev);
3162 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3163 (((lp->media == _10Mb) || (lp->media == TP) ||
3164 (lp->media == BNC) || (lp->media == AUI)) &&
3165 is_10_up(dev))) {
3166 next_tick = dc2114x_autoconf(dev);
3167 } else {
3168 lp->tcount++;
3169 lp->media = INIT;
3170 }
3171 break;
3172
3173 case _10Mb:
3174 next_tick = 3000;
3175 if (!lp->tx_enable) {
3176 SET_10Mb;
3177 de4x5_init_connection(dev);
3178 } else {
3179 if (!lp->linkOK && (lp->autosense == AUTO)) {
3180 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3181 lp->media = INIT;
3182 lp->tcount++;
3183 next_tick = DE4X5_AUTOSENSE_MS;
3184 }
3185 }
3186 }
3187 break;
3188
3189 case _100Mb:
3190 next_tick = 3000;
3191 if (!lp->tx_enable) {
3192 SET_100Mb;
3193 de4x5_init_connection(dev);
3194 } else {
3195 if (!lp->linkOK && (lp->autosense == AUTO)) {
3196 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3197 lp->media = INIT;
3198 lp->tcount++;
3199 next_tick = DE4X5_AUTOSENSE_MS;
3200 }
3201 }
3202 }
3203 break;
3204
3205 default:
3206 lp->tcount++;
3207printk("Huh?: media:%02x\n", lp->media);
3208 lp->media = INIT;
3209 break;
3210 }
3211
3212 return next_tick;
3213}
3214
3215static int
3216srom_autoconf(struct net_device *dev)
3217{
3218 struct de4x5_private *lp = netdev_priv(dev);
3219
3220 return lp->infoleaf_fn(dev);
3221}
3222
3223/*
3224** This mapping keeps the original media codes and FDX flag unchanged.
3225** While it isn't strictly necessary, it helps me for the moment...
3226** The early return avoids a media state / SROM media space clash.
3227*/
3228static int
3229srom_map_media(struct net_device *dev)
3230{
3231 struct de4x5_private *lp = netdev_priv(dev);
3232
3233 lp->fdx = 0;
3234 if (lp->infoblock_media == lp->media)
3235 return 0;
3236
3237 switch(lp->infoblock_media) {
3238 case SROM_10BASETF:
3239 if (!lp->params.fdx) return -1;
3240 lp->fdx = TRUE;
3241 case SROM_10BASET:
3242 if (lp->params.fdx && !lp->fdx) return -1;
3243 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3244 lp->media = _10Mb;
3245 } else {
3246 lp->media = TP;
3247 }
3248 break;
3249
3250 case SROM_10BASE2:
3251 lp->media = BNC;
3252 break;
3253
3254 case SROM_10BASE5:
3255 lp->media = AUI;
3256 break;
3257
3258 case SROM_100BASETF:
3259 if (!lp->params.fdx) return -1;
3260 lp->fdx = TRUE;
3261 case SROM_100BASET:
3262 if (lp->params.fdx && !lp->fdx) return -1;
3263 lp->media = _100Mb;
3264 break;
3265
3266 case SROM_100BASET4:
3267 lp->media = _100Mb;
3268 break;
3269
3270 case SROM_100BASEFF:
3271 if (!lp->params.fdx) return -1;
3272 lp->fdx = TRUE;
3273 case SROM_100BASEF:
3274 if (lp->params.fdx && !lp->fdx) return -1;
3275 lp->media = _100Mb;
3276 break;
3277
3278 case ANS:
3279 lp->media = ANS;
3280 lp->fdx = lp->params.fdx;
3281 break;
3282
3283 default:
3284 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3285 lp->infoblock_media);
3286 return -1;
3287 break;
3288 }
3289
3290 return 0;
3291}
3292
3293static void
3294de4x5_init_connection(struct net_device *dev)
3295{
3296 struct de4x5_private *lp = netdev_priv(dev);
3297 u_long iobase = dev->base_addr;
3298 u_long flags = 0;
3299
3300 if (lp->media != lp->c_media) {
3301 de4x5_dbg_media(dev);
3302 lp->c_media = lp->media; /* Stop scrolling media messages */
3303 }
3304
3305 spin_lock_irqsave(&lp->lock, flags);
3306 de4x5_rst_desc_ring(dev);
3307 de4x5_setup_intr(dev);
3308 lp->tx_enable = YES;
3309 spin_unlock_irqrestore(&lp->lock, flags);
3310 outl(POLL_DEMAND, DE4X5_TPD);
3311
3312 netif_wake_queue(dev);
3313
3314 return;
3315}
3316
3317/*
3318** General PHY reset function. Some MII devices don't reset correctly
3319** since their MII address pins can float at voltages that are dependent
3320** on the signal pin use. Do a double reset to ensure a reset.
3321*/
3322static int
3323de4x5_reset_phy(struct net_device *dev)
3324{
3325 struct de4x5_private *lp = netdev_priv(dev);
3326 u_long iobase = dev->base_addr;
3327 int next_tick = 0;
3328
3329 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3330 if (lp->timeout < 0) {
3331 if (lp->useSROM) {
3332 if (lp->phy[lp->active].rst) {
3333 srom_exec(dev, lp->phy[lp->active].rst);
3334 srom_exec(dev, lp->phy[lp->active].rst);
3335 } else if (lp->rst) { /* Type 5 infoblock reset */
3336 srom_exec(dev, lp->rst);
3337 srom_exec(dev, lp->rst);
3338 }
3339 } else {
3340 PHY_HARD_RESET;
3341 }
3342 if (lp->useMII) {
3343 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3344 }
3345 }
3346 if (lp->useMII) {
3347 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3348 }
3349 } else if (lp->chipset == DC21140) {
3350 PHY_HARD_RESET;
3351 }
3352
3353 return next_tick;
3354}
3355
3356static int
3357test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3358{
3359 struct de4x5_private *lp = netdev_priv(dev);
3360 u_long iobase = dev->base_addr;
3361 s32 sts, csr12;
3362
3363 if (lp->timeout < 0) {
3364 lp->timeout = msec/100;
3365 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3366 reset_init_sia(dev, csr13, csr14, csr15);
3367 }
3368
3369 /* set up the interrupt mask */
3370 outl(irq_mask, DE4X5_IMR);
3371
3372 /* clear all pending interrupts */
3373 sts = inl(DE4X5_STS);
3374 outl(sts, DE4X5_STS);
3375
3376 /* clear csr12 NRA and SRA bits */
3377 if ((lp->chipset == DC21041) || lp->useSROM) {
3378 csr12 = inl(DE4X5_SISR);
3379 outl(csr12, DE4X5_SISR);
3380 }
3381 }
3382
3383 sts = inl(DE4X5_STS) & ~TIMER_CB;
3384
3385 if (!(sts & irqs) && --lp->timeout) {
3386 sts = 100 | TIMER_CB;
3387 } else {
3388 lp->timeout = -1;
3389 }
3390
3391 return sts;
3392}
3393
3394static int
3395test_tp(struct net_device *dev, s32 msec)
3396{
3397 struct de4x5_private *lp = netdev_priv(dev);
3398 u_long iobase = dev->base_addr;
3399 int sisr;
3400
3401 if (lp->timeout < 0) {
3402 lp->timeout = msec/100;
3403 }
3404
3405 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3406
3407 if (sisr && --lp->timeout) {
3408 sisr = 100 | TIMER_CB;
3409 } else {
3410 lp->timeout = -1;
3411 }
3412
3413 return sisr;
3414}
3415
3416/*
3417** Samples the 100Mb Link State Signal. The sample interval is important
3418** because too fast a rate can give erroneous results and confuse the
3419** speed sense algorithm.
3420*/
3421#define SAMPLE_INTERVAL 500 /* ms */
3422#define SAMPLE_DELAY 2000 /* ms */
3423static int
3424test_for_100Mb(struct net_device *dev, int msec)
3425{
3426 struct de4x5_private *lp = netdev_priv(dev);
3427 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3428
3429 if (lp->timeout < 0) {
3430 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3431 if (msec > SAMPLE_DELAY) {
3432 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3433 gep = SAMPLE_DELAY | TIMER_CB;
3434 return gep;
3435 } else {
3436 lp->timeout = msec/SAMPLE_INTERVAL;
3437 }
3438 }
3439
3440 if (lp->phy[lp->active].id || lp->useSROM) {
3441 gep = is_100_up(dev) | is_spd_100(dev);
3442 } else {
3443 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3444 }
3445 if (!(gep & ret) && --lp->timeout) {
3446 gep = SAMPLE_INTERVAL | TIMER_CB;
3447 } else {
3448 lp->timeout = -1;
3449 }
3450
3451 return gep;
3452}
3453
3454static int
3455wait_for_link(struct net_device *dev)
3456{
3457 struct de4x5_private *lp = netdev_priv(dev);
3458
3459 if (lp->timeout < 0) {
3460 lp->timeout = 1;
3461 }
3462
3463 if (lp->timeout--) {
3464 return TIMER_CB;
3465 } else {
3466 lp->timeout = -1;
3467 }
3468
3469 return 0;
3470}
3471
3472/*
3473**
3474**
3475*/
3476static int
3477test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3478{
3479 struct de4x5_private *lp = netdev_priv(dev);
3480 int test;
3481 u_long iobase = dev->base_addr;
3482
3483 if (lp->timeout < 0) {
3484 lp->timeout = msec/100;
3485 }
3486
3487 if (pol) pol = ~0;
3488 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3489 test = (reg ^ pol) & mask;
3490
3491 if (test && --lp->timeout) {
3492 reg = 100 | TIMER_CB;
3493 } else {
3494 lp->timeout = -1;
3495 }
3496
3497 return reg;
3498}
3499
3500static int
3501is_spd_100(struct net_device *dev)
3502{
3503 struct de4x5_private *lp = netdev_priv(dev);
3504 u_long iobase = dev->base_addr;
3505 int spd;
3506
3507 if (lp->useMII) {
3508 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3509 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3510 spd &= lp->phy[lp->active].spd.mask;
3511 } else if (!lp->useSROM) { /* de500-xa */
3512 spd = ((~gep_rd(dev)) & GEP_SLNK);
3513 } else {
3514 if ((lp->ibn == 2) || !lp->asBitValid)
3515 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3516
3517 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3518 (lp->linkOK & ~lp->asBitValid);
3519 }
3520
3521 return spd;
3522}
3523
3524static int
3525is_100_up(struct net_device *dev)
3526{
3527 struct de4x5_private *lp = netdev_priv(dev);
3528 u_long iobase = dev->base_addr;
3529
3530 if (lp->useMII) {
3531 /* Double read for sticky bits & temporary drops */
3532 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3533 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3534 } else if (!lp->useSROM) { /* de500-xa */
3535 return ((~gep_rd(dev)) & GEP_SLNK);
3536 } else {
3537 if ((lp->ibn == 2) || !lp->asBitValid)
3538 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3539
3540 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3541 (lp->linkOK & ~lp->asBitValid));
3542 }
3543}
3544
3545static int
3546is_10_up(struct net_device *dev)
3547{
3548 struct de4x5_private *lp = netdev_priv(dev);
3549 u_long iobase = dev->base_addr;
3550
3551 if (lp->useMII) {
3552 /* Double read for sticky bits & temporary drops */
3553 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3554 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3555 } else if (!lp->useSROM) { /* de500-xa */
3556 return ((~gep_rd(dev)) & GEP_LNP);
3557 } else {
3558 if ((lp->ibn == 2) || !lp->asBitValid)
3559 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3560 (~inl(DE4X5_SISR)&SISR_LS10):
3561 0);
3562
3563 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3564 (lp->linkOK & ~lp->asBitValid));
3565 }
3566}
3567
3568static int
3569is_anc_capable(struct net_device *dev)
3570{
3571 struct de4x5_private *lp = netdev_priv(dev);
3572 u_long iobase = dev->base_addr;
3573
3574 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3575 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3576 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3577 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3578 } else {
3579 return 0;
3580 }
3581}
3582
3583/*
3584** Send a packet onto the media and watch for send errors that indicate the
3585** media is bad or unconnected.
3586*/
3587static int
3588ping_media(struct net_device *dev, int msec)
3589{
3590 struct de4x5_private *lp = netdev_priv(dev);
3591 u_long iobase = dev->base_addr;
3592 int sisr;
3593
3594 if (lp->timeout < 0) {
3595 lp->timeout = msec/100;
3596
3597 lp->tmp = lp->tx_new; /* Remember the ring position */
3598 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3599 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3600 outl(POLL_DEMAND, DE4X5_TPD);
3601 }
3602
3603 sisr = inl(DE4X5_SISR);
3604
3605 if ((!(sisr & SISR_NCR)) &&
3606 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3607 (--lp->timeout)) {
3608 sisr = 100 | TIMER_CB;
3609 } else {
3610 if ((!(sisr & SISR_NCR)) &&
3611 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3612 lp->timeout) {
3613 sisr = 0;
3614 } else {
3615 sisr = 1;
3616 }
3617 lp->timeout = -1;
3618 }
3619
3620 return sisr;
3621}
3622
3623/*
3624** This function does 2 things: on Intels it kmalloc's another buffer to
3625** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3626** into which the packet is copied.
3627*/
3628static struct sk_buff *
3629de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3630{
3631 struct de4x5_private *lp = netdev_priv(dev);
3632 struct sk_buff *p;
3633
3634#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3635 struct sk_buff *ret;
3636 u_long i=0, tmp;
3637
3638 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3639 if (!p) return NULL;
3640
3641 p->dev = dev;
3642 tmp = virt_to_bus(p->data);
3643 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3644 skb_reserve(p, i);
3645 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3646
3647 ret = lp->rx_skb[index];
3648 lp->rx_skb[index] = p;
3649
3650 if ((u_long) ret > 1) {
3651 skb_put(ret, len);
3652 }
3653
3654 return ret;
3655
3656#else
3657 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3658
3659 p = dev_alloc_skb(len + 2);
3660 if (!p) return NULL;
3661
3662 p->dev = dev;
3663 skb_reserve(p, 2); /* Align */
3664 if (index < lp->rx_old) { /* Wrapped buffer */
3665 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3666 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3667 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3668 } else { /* Linear buffer */
3669 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3670 }
3671
3672 return p;
3673#endif
3674}
3675
3676static void
3677de4x5_free_rx_buffs(struct net_device *dev)
3678{
3679 struct de4x5_private *lp = netdev_priv(dev);
3680 int i;
3681
3682 for (i=0; i<lp->rxRingSize; i++) {
3683 if ((u_long) lp->rx_skb[i] > 1) {
3684 dev_kfree_skb(lp->rx_skb[i]);
3685 }
3686 lp->rx_ring[i].status = 0;
3687 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3688 }
3689
3690 return;
3691}
3692
3693static void
3694de4x5_free_tx_buffs(struct net_device *dev)
3695{
3696 struct de4x5_private *lp = netdev_priv(dev);
3697 int i;
3698
3699 for (i=0; i<lp->txRingSize; i++) {
3700 if (lp->tx_skb[i])
3701 de4x5_free_tx_buff(lp, i);
3702 lp->tx_ring[i].status = 0;
3703 }
3704
3705 /* Unload the locally queued packets */
3706 while (lp->cache.skb) {
3707 dev_kfree_skb(de4x5_get_cache(dev));
3708 }
3709
3710 return;
3711}
3712
3713/*
3714** When a user pulls a connection, the DECchip can end up in a
3715** 'running - waiting for end of transmission' state. This means that we
3716** have to perform a chip soft reset to ensure that we can synchronize
3717** the hardware and software and make any media probes using a loopback
3718** packet meaningful.
3719*/
3720static void
3721de4x5_save_skbs(struct net_device *dev)
3722{
3723 struct de4x5_private *lp = netdev_priv(dev);
3724 u_long iobase = dev->base_addr;
3725 s32 omr;
3726
3727 if (!lp->cache.save_cnt) {
3728 STOP_DE4X5;
3729 de4x5_tx(dev); /* Flush any sent skb's */
3730 de4x5_free_tx_buffs(dev);
3731 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3732 de4x5_sw_reset(dev);
3733 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3734 lp->cache.save_cnt++;
3735 START_DE4X5;
3736 }
3737
3738 return;
3739}
3740
3741static void
3742de4x5_rst_desc_ring(struct net_device *dev)
3743{
3744 struct de4x5_private *lp = netdev_priv(dev);
3745 u_long iobase = dev->base_addr;
3746 int i;
3747 s32 omr;
3748
3749 if (lp->cache.save_cnt) {
3750 STOP_DE4X5;
3751 outl(lp->dma_rings, DE4X5_RRBA);
3752 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3753 DE4X5_TRBA);
3754
3755 lp->rx_new = lp->rx_old = 0;
3756 lp->tx_new = lp->tx_old = 0;
3757
3758 for (i = 0; i < lp->rxRingSize; i++) {
3759 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3760 }
3761
3762 for (i = 0; i < lp->txRingSize; i++) {
3763 lp->tx_ring[i].status = cpu_to_le32(0);
3764 }
3765
3766 barrier();
3767 lp->cache.save_cnt--;
3768 START_DE4X5;
3769 }
3770
3771 return;
3772}
3773
3774static void
3775de4x5_cache_state(struct net_device *dev, int flag)
3776{
3777 struct de4x5_private *lp = netdev_priv(dev);
3778 u_long iobase = dev->base_addr;
3779
3780 switch(flag) {
3781 case DE4X5_SAVE_STATE:
3782 lp->cache.csr0 = inl(DE4X5_BMR);
3783 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3784 lp->cache.csr7 = inl(DE4X5_IMR);
3785 break;
3786
3787 case DE4X5_RESTORE_STATE:
3788 outl(lp->cache.csr0, DE4X5_BMR);
3789 outl(lp->cache.csr6, DE4X5_OMR);
3790 outl(lp->cache.csr7, DE4X5_IMR);
3791 if (lp->chipset == DC21140) {
3792 gep_wr(lp->cache.gepc, dev);
3793 gep_wr(lp->cache.gep, dev);
3794 } else {
3795 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3796 lp->cache.csr15);
3797 }
3798 break;
3799 }
3800
3801 return;
3802}
3803
3804static void
3805de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3806{
3807 struct de4x5_private *lp = netdev_priv(dev);
3808 struct sk_buff *p;
3809
3810 if (lp->cache.skb) {
3811 for (p=lp->cache.skb; p->next; p=p->next);
3812 p->next = skb;
3813 } else {
3814 lp->cache.skb = skb;
3815 }
3816 skb->next = NULL;
3817
3818 return;
3819}
3820
3821static void
3822de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3823{
3824 struct de4x5_private *lp = netdev_priv(dev);
3825 struct sk_buff *p = lp->cache.skb;
3826
3827 lp->cache.skb = skb;
3828 skb->next = p;
3829
3830 return;
3831}
3832
3833static struct sk_buff *
3834de4x5_get_cache(struct net_device *dev)
3835{
3836 struct de4x5_private *lp = netdev_priv(dev);
3837 struct sk_buff *p = lp->cache.skb;
3838
3839 if (p) {
3840 lp->cache.skb = p->next;
3841 p->next = NULL;
3842 }
3843
3844 return p;
3845}
3846
3847/*
3848** Check the Auto Negotiation State. Return OK when a link pass interrupt
3849** is received and the auto-negotiation status is NWAY OK.
3850*/
3851static int
3852test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3853{
3854 struct de4x5_private *lp = netdev_priv(dev);
3855 u_long iobase = dev->base_addr;
3856 s32 sts, ans;
3857
3858 if (lp->timeout < 0) {
3859 lp->timeout = msec/100;
3860 outl(irq_mask, DE4X5_IMR);
3861
3862 /* clear all pending interrupts */
3863 sts = inl(DE4X5_STS);
3864 outl(sts, DE4X5_STS);
3865 }
3866
3867 ans = inl(DE4X5_SISR) & SISR_ANS;
3868 sts = inl(DE4X5_STS) & ~TIMER_CB;
3869
3870 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3871 sts = 100 | TIMER_CB;
3872 } else {
3873 lp->timeout = -1;
3874 }
3875
3876 return sts;
3877}
3878
3879static void
3880de4x5_setup_intr(struct net_device *dev)
3881{
3882 struct de4x5_private *lp = netdev_priv(dev);
3883 u_long iobase = dev->base_addr;
3884 s32 imr, sts;
3885
3886 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3887 imr = 0;
3888 UNMASK_IRQs;
3889 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3890 outl(sts, DE4X5_STS);
3891 ENABLE_IRQs;
3892 }
3893
3894 return;
3895}
3896
3897/*
3898**
3899*/
3900static void
3901reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3902{
3903 struct de4x5_private *lp = netdev_priv(dev);
3904 u_long iobase = dev->base_addr;
3905
3906 RESET_SIA;
3907 if (lp->useSROM) {
3908 if (lp->ibn == 3) {
3909 srom_exec(dev, lp->phy[lp->active].rst);
3910 srom_exec(dev, lp->phy[lp->active].gep);
3911 outl(1, DE4X5_SICR);
3912 return;
3913 } else {
3914 csr15 = lp->cache.csr15;
3915 csr14 = lp->cache.csr14;
3916 csr13 = lp->cache.csr13;
3917 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3918 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3919 }
3920 } else {
3921 outl(csr15, DE4X5_SIGR);
3922 }
3923 outl(csr14, DE4X5_STRR);
3924 outl(csr13, DE4X5_SICR);
3925
3926 mdelay(10);
3927
3928 return;
3929}
3930
3931/*
3932** Create a loopback ethernet packet
3933*/
3934static void
3935create_packet(struct net_device *dev, char *frame, int len)
3936{
3937 int i;
3938 char *buf = frame;
3939
3940 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3941 *buf++ = dev->dev_addr[i];
3942 }
3943 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3944 *buf++ = dev->dev_addr[i];
3945 }
3946
3947 *buf++ = 0; /* Packet length (2 bytes) */
3948 *buf++ = 1;
3949
3950 return;
3951}
3952
3953/*
3954** Look for a particular board name in the EISA configuration space
3955*/
3956static int
3957EISA_signature(char *name, struct device *device)
3958{
3959 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3960 struct eisa_device *edev;
3961
3962 *name = '\0';
3963 edev = to_eisa_device (device);
3964 i = edev->id.driver_data;
3965
3966 if (i >= 0 && i < siglen) {
3967 strcpy (name, de4x5_signatures[i]);
3968 status = 1;
3969 }
3970
3971 return status; /* return the device name string */
3972}
3973
3974/*
3975** Look for a particular board name in the PCI configuration space
3976*/
3977static int
3978PCI_signature(char *name, struct de4x5_private *lp)
3979{
3980 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3981
3982 if (lp->chipset == DC21040) {
3983 strcpy(name, "DE434/5");
3984 return status;
3985 } else { /* Search for a DEC name in the SROM */
3986 int i = *((char *)&lp->srom + 19) * 3;
3987 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3988 }
3989 name[8] = '\0';
3990 for (i=0; i<siglen; i++) {
3991 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3992 }
3993 if (i == siglen) {
3994 if (dec_only) {
3995 *name = '\0';
3996 } else { /* Use chip name to avoid confusion */
3997 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3998 ((lp->chipset == DC21041) ? "DC21041" :
3999 ((lp->chipset == DC21140) ? "DC21140" :
4000 ((lp->chipset == DC21142) ? "DC21142" :
4001 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4002 )))))));
4003 }
4004 if (lp->chipset != DC21041) {
4005 lp->useSROM = TRUE; /* card is not recognisably DEC */
4006 }
4007 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4008 lp->useSROM = TRUE;
4009 }
4010
4011 return status;
4012}
4013
4014/*
4015** Set up the Ethernet PROM counter to the start of the Ethernet address on
4016** the DC21040, else read the SROM for the other chips.
4017** The SROM may not be present in a multi-MAC card, so first read the
4018** MAC address and check for a bad address. If there is a bad one then exit
4019** immediately with the prior srom contents intact (the h/w address will
4020** be fixed up later).
4021*/
4022static void
4023DevicePresent(struct net_device *dev, u_long aprom_addr)
4024{
4025 int i, j=0;
4026 struct de4x5_private *lp = netdev_priv(dev);
4027
4028 if (lp->chipset == DC21040) {
4029 if (lp->bus == EISA) {
4030 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4031 } else {
4032 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4033 }
4034 } else { /* Read new srom */
4035 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4036 for (i=0; i<(ETH_ALEN>>1); i++) {
4037 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4038 *p = le16_to_cpu(tmp);
4039 j += *p++;
4040 }
4041 if ((j == 0) || (j == 0x2fffd)) {
4042 return;
4043 }
4044
4045 p=(short *)&lp->srom;
4046 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4047 tmp = srom_rd(aprom_addr, i);
4048 *p++ = le16_to_cpu(tmp);
4049 }
4050 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4051 }
4052
4053 return;
4054}
4055
4056/*
4057** Since the write on the Enet PROM register doesn't seem to reset the PROM
4058** pointer correctly (at least on my DE425 EISA card), this routine should do
4059** it...from depca.c.
4060*/
4061static void
4062enet_addr_rst(u_long aprom_addr)
4063{
4064 union {
4065 struct {
4066 u32 a;
4067 u32 b;
4068 } llsig;
4069 char Sig[sizeof(u32) << 1];
4070 } dev;
4071 short sigLength=0;
4072 s8 data;
4073 int i, j;
4074
4075 dev.llsig.a = ETH_PROM_SIG;
4076 dev.llsig.b = ETH_PROM_SIG;
4077 sigLength = sizeof(u32) << 1;
4078
4079 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4080 data = inb(aprom_addr);
4081 if (dev.Sig[j] == data) { /* track signature */
4082 j++;
4083 } else { /* lost signature; begin search again */
4084 if (data == dev.Sig[0]) { /* rare case.... */
4085 j=1;
4086 } else {
4087 j=0;
4088 }
4089 }
4090 }
4091
4092 return;
4093}
4094
4095/*
4096** For the bad status case and no SROM, then add one to the previous
4097** address. However, need to add one backwards in case we have 0xff
4098** as one or more of the bytes. Only the last 3 bytes should be checked
4099** as the first three are invariant - assigned to an organisation.
4100*/
4101static int
4102get_hw_addr(struct net_device *dev)
4103{
4104 u_long iobase = dev->base_addr;
4105 int broken, i, k, tmp, status = 0;
4106 u_short j,chksum;
4107 struct de4x5_private *lp = netdev_priv(dev);
4108
4109 broken = de4x5_bad_srom(lp);
4110
4111 for (i=0,k=0,j=0;j<3;j++) {
4112 k <<= 1;
4113 if (k > 0xffff) k-=0xffff;
4114
4115 if (lp->bus == PCI) {
4116 if (lp->chipset == DC21040) {
4117 while ((tmp = inl(DE4X5_APROM)) < 0);
4118 k += (u_char) tmp;
4119 dev->dev_addr[i++] = (u_char) tmp;
4120 while ((tmp = inl(DE4X5_APROM)) < 0);
4121 k += (u_short) (tmp << 8);
4122 dev->dev_addr[i++] = (u_char) tmp;
4123 } else if (!broken) {
4124 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4125 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4126 } else if ((broken == SMC) || (broken == ACCTON)) {
4127 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4128 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4129 }
4130 } else {
4131 k += (u_char) (tmp = inb(EISA_APROM));
4132 dev->dev_addr[i++] = (u_char) tmp;
4133 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4134 dev->dev_addr[i++] = (u_char) tmp;
4135 }
4136
4137 if (k > 0xffff) k-=0xffff;
4138 }
4139 if (k == 0xffff) k=0;
4140
4141 if (lp->bus == PCI) {
4142 if (lp->chipset == DC21040) {
4143 while ((tmp = inl(DE4X5_APROM)) < 0);
4144 chksum = (u_char) tmp;
4145 while ((tmp = inl(DE4X5_APROM)) < 0);
4146 chksum |= (u_short) (tmp << 8);
4147 if ((k != chksum) && (dec_only)) status = -1;
4148 }
4149 } else {
4150 chksum = (u_char) inb(EISA_APROM);
4151 chksum |= (u_short) (inb(EISA_APROM) << 8);
4152 if ((k != chksum) && (dec_only)) status = -1;
4153 }
4154
4155 /* If possible, try to fix a broken card - SMC only so far */
4156 srom_repair(dev, broken);
4157
4158#ifdef CONFIG_PPC_MULTIPLATFORM
4159 /*
4160 ** If the address starts with 00 a0, we have to bit-reverse
4161 ** each byte of the address.
4162 */
4163 if ( (_machine & _MACH_Pmac) &&
4164 (dev->dev_addr[0] == 0) &&
4165 (dev->dev_addr[1] == 0xa0) )
4166 {
4167 for (i = 0; i < ETH_ALEN; ++i)
4168 {
4169 int x = dev->dev_addr[i];
4170 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4171 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4172 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4173 }
4174 }
4175#endif /* CONFIG_PPC_MULTIPLATFORM */
4176
4177 /* Test for a bad enet address */
4178 status = test_bad_enet(dev, status);
4179
4180 return status;
4181}
4182
4183/*
4184** Test for enet addresses in the first 32 bytes. The built-in strncmp
4185** didn't seem to work here...?
4186*/
4187static int
4188de4x5_bad_srom(struct de4x5_private *lp)
4189{
4190 int i, status = 0;
4191
4192 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4193 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4194 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4195 if (i == 0) {
4196 status = SMC;
4197 } else if (i == 1) {
4198 status = ACCTON;
4199 }
4200 break;
4201 }
4202 }
4203
4204 return status;
4205}
4206
4207static int
4208de4x5_strncmp(char *a, char *b, int n)
4209{
4210 int ret=0;
4211
4212 for (;n && !ret;n--) {
4213 ret = *a++ - *b++;
4214 }
4215
4216 return ret;
4217}
4218
4219static void
4220srom_repair(struct net_device *dev, int card)
4221{
4222 struct de4x5_private *lp = netdev_priv(dev);
4223
4224 switch(card) {
4225 case SMC:
4226 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4227 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4228 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4229 lp->useSROM = TRUE;
4230 break;
4231 }
4232
4233 return;
4234}
4235
4236/*
4237** Assume that the irq's do not follow the PCI spec - this is seems
4238** to be true so far (2 for 2).
4239*/
4240static int
4241test_bad_enet(struct net_device *dev, int status)
4242{
4243 struct de4x5_private *lp = netdev_priv(dev);
4244 int i, tmp;
4245
4246 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4247 if ((tmp == 0) || (tmp == 0x5fa)) {
4248 if ((lp->chipset == last.chipset) &&
4249 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4250 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4251 for (i=ETH_ALEN-1; i>2; --i) {
4252 dev->dev_addr[i] += 1;
4253 if (dev->dev_addr[i] != 0) break;
4254 }
4255 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4256 if (!an_exception(lp)) {
4257 dev->irq = last.irq;
4258 }
4259
4260 status = 0;
4261 }
4262 } else if (!status) {
4263 last.chipset = lp->chipset;
4264 last.bus = lp->bus_num;
4265 last.irq = dev->irq;
4266 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4267 }
4268
4269 return status;
4270}
4271
4272/*
4273** List of board exceptions with correctly wired IRQs
4274*/
4275static int
4276an_exception(struct de4x5_private *lp)
4277{
4278 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4279 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4280 return -1;
4281 }
4282
4283 return 0;
4284}
4285
4286/*
4287** SROM Read
4288*/
4289static short
4290srom_rd(u_long addr, u_char offset)
4291{
4292 sendto_srom(SROM_RD | SROM_SR, addr);
4293
4294 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4295 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4296 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4297
4298 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4299}
4300
4301static void
4302srom_latch(u_int command, u_long addr)
4303{
4304 sendto_srom(command, addr);
4305 sendto_srom(command | DT_CLK, addr);
4306 sendto_srom(command, addr);
4307
4308 return;
4309}
4310
4311static void
4312srom_command(u_int command, u_long addr)
4313{
4314 srom_latch(command, addr);
4315 srom_latch(command, addr);
4316 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4317
4318 return;
4319}
4320
4321static void
4322srom_address(u_int command, u_long addr, u_char offset)
4323{
4324 int i, a;
4325
4326 a = offset << 2;
4327 for (i=0; i<6; i++, a <<= 1) {
4328 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4329 }
4330 udelay(1);
4331
4332 i = (getfrom_srom(addr) >> 3) & 0x01;
4333
4334 return;
4335}
4336
4337static short
4338srom_data(u_int command, u_long addr)
4339{
4340 int i;
4341 short word = 0;
4342 s32 tmp;
4343
4344 for (i=0; i<16; i++) {
4345 sendto_srom(command | DT_CLK, addr);
4346 tmp = getfrom_srom(addr);
4347 sendto_srom(command, addr);
4348
4349 word = (word << 1) | ((tmp >> 3) & 0x01);
4350 }
4351
4352 sendto_srom(command & 0x0000ff00, addr);
4353
4354 return word;
4355}
4356
4357/*
4358static void
4359srom_busy(u_int command, u_long addr)
4360{
4361 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4362
4363 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4364 mdelay(1);
4365 }
4366
4367 sendto_srom(command & 0x0000ff00, addr);
4368
4369 return;
4370}
4371*/
4372
4373static void
4374sendto_srom(u_int command, u_long addr)
4375{
4376 outl(command, addr);
4377 udelay(1);
4378
4379 return;
4380}
4381
4382static int
4383getfrom_srom(u_long addr)
4384{
4385 s32 tmp;
4386
4387 tmp = inl(addr);
4388 udelay(1);
4389
4390 return tmp;
4391}
4392
4393static int
4394srom_infoleaf_info(struct net_device *dev)
4395{
4396 struct de4x5_private *lp = netdev_priv(dev);
4397 int i, count;
4398 u_char *p;
4399
4400 /* Find the infoleaf decoder function that matches this chipset */
4401 for (i=0; i<INFOLEAF_SIZE; i++) {
4402 if (lp->chipset == infoleaf_array[i].chipset) break;
4403 }
4404 if (i == INFOLEAF_SIZE) {
4405 lp->useSROM = FALSE;
4406 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4407 dev->name);
4408 return -ENXIO;
4409 }
4410
4411 lp->infoleaf_fn = infoleaf_array[i].fn;
4412
4413 /* Find the information offset that this function should use */
4414 count = *((u_char *)&lp->srom + 19);
4415 p = (u_char *)&lp->srom + 26;
4416
4417 if (count > 1) {
4418 for (i=count; i; --i, p+=3) {
4419 if (lp->device == *p) break;
4420 }
4421 if (i == 0) {
4422 lp->useSROM = FALSE;
4423 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4424 dev->name, lp->device);
4425 return -ENXIO;
4426 }
4427 }
4428
4429 lp->infoleaf_offset = TWIDDLE(p+1);
4430
4431 return 0;
4432}
4433
4434/*
4435** This routine loads any type 1 or 3 MII info into the mii device
4436** struct and executes any type 5 code to reset PHY devices for this
4437** controller.
4438** The info for the MII devices will be valid since the index used
4439** will follow the discovery process from MII address 1-31 then 0.
4440*/
4441static void
4442srom_init(struct net_device *dev)
4443{
4444 struct de4x5_private *lp = netdev_priv(dev);
4445 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4446 u_char count;
4447
4448 p+=2;
4449 if (lp->chipset == DC21140) {
4450 lp->cache.gepc = (*p++ | GEP_CTRL);
4451 gep_wr(lp->cache.gepc, dev);
4452 }
4453
4454 /* Block count */
4455 count = *p++;
4456
4457 /* Jump the infoblocks to find types */
4458 for (;count; --count) {
4459 if (*p < 128) {
4460 p += COMPACT_LEN;
4461 } else if (*(p+1) == 5) {
4462 type5_infoblock(dev, 1, p);
4463 p += ((*p & BLOCK_LEN) + 1);
4464 } else if (*(p+1) == 4) {
4465 p += ((*p & BLOCK_LEN) + 1);
4466 } else if (*(p+1) == 3) {
4467 type3_infoblock(dev, 1, p);
4468 p += ((*p & BLOCK_LEN) + 1);
4469 } else if (*(p+1) == 2) {
4470 p += ((*p & BLOCK_LEN) + 1);
4471 } else if (*(p+1) == 1) {
4472 type1_infoblock(dev, 1, p);
4473 p += ((*p & BLOCK_LEN) + 1);
4474 } else {
4475 p += ((*p & BLOCK_LEN) + 1);
4476 }
4477 }
4478
4479 return;
4480}
4481
4482/*
4483** A generic routine that writes GEP control, data and reset information
4484** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4485*/
4486static void
4487srom_exec(struct net_device *dev, u_char *p)
4488{
4489 struct de4x5_private *lp = netdev_priv(dev);
4490 u_long iobase = dev->base_addr;
4491 u_char count = (p ? *p++ : 0);
4492 u_short *w = (u_short *)p;
4493
4494 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4495
4496 if (lp->chipset != DC21140) RESET_SIA;
4497
4498 while (count--) {
4499 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4500 *p++ : TWIDDLE(w++)), dev);
4501 mdelay(2); /* 2ms per action */
4502 }
4503
4504 if (lp->chipset != DC21140) {
4505 outl(lp->cache.csr14, DE4X5_STRR);
4506 outl(lp->cache.csr13, DE4X5_SICR);
4507 }
4508
4509 return;
4510}
4511
4512/*
4513** Basically this function is a NOP since it will never be called,
4514** unless I implement the DC21041 SROM functions. There's no need
4515** since the existing code will be satisfactory for all boards.
4516*/
4517static int
4518dc21041_infoleaf(struct net_device *dev)
4519{
4520 return DE4X5_AUTOSENSE_MS;
4521}
4522
4523static int
4524dc21140_infoleaf(struct net_device *dev)
4525{
4526 struct de4x5_private *lp = netdev_priv(dev);
4527 u_char count = 0;
4528 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4529 int next_tick = DE4X5_AUTOSENSE_MS;
4530
4531 /* Read the connection type */
4532 p+=2;
4533
4534 /* GEP control */
4535 lp->cache.gepc = (*p++ | GEP_CTRL);
4536
4537 /* Block count */
4538 count = *p++;
4539
4540 /* Recursively figure out the info blocks */
4541 if (*p < 128) {
4542 next_tick = dc_infoblock[COMPACT](dev, count, p);
4543 } else {
4544 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4545 }
4546
4547 if (lp->tcount == count) {
4548 lp->media = NC;
4549 if (lp->media != lp->c_media) {
4550 de4x5_dbg_media(dev);
4551 lp->c_media = lp->media;
4552 }
4553 lp->media = INIT;
4554 lp->tcount = 0;
4555 lp->tx_enable = FALSE;
4556 }
4557
4558 return next_tick & ~TIMER_CB;
4559}
4560
4561static int
4562dc21142_infoleaf(struct net_device *dev)
4563{
4564 struct de4x5_private *lp = netdev_priv(dev);
4565 u_char count = 0;
4566 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4567 int next_tick = DE4X5_AUTOSENSE_MS;
4568
4569 /* Read the connection type */
4570 p+=2;
4571
4572 /* Block count */
4573 count = *p++;
4574
4575 /* Recursively figure out the info blocks */
4576 if (*p < 128) {
4577 next_tick = dc_infoblock[COMPACT](dev, count, p);
4578 } else {
4579 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4580 }
4581
4582 if (lp->tcount == count) {
4583 lp->media = NC;
4584 if (lp->media != lp->c_media) {
4585 de4x5_dbg_media(dev);
4586 lp->c_media = lp->media;
4587 }
4588 lp->media = INIT;
4589 lp->tcount = 0;
4590 lp->tx_enable = FALSE;
4591 }
4592
4593 return next_tick & ~TIMER_CB;
4594}
4595
4596static int
4597dc21143_infoleaf(struct net_device *dev)
4598{
4599 struct de4x5_private *lp = netdev_priv(dev);
4600 u_char count = 0;
4601 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4602 int next_tick = DE4X5_AUTOSENSE_MS;
4603
4604 /* Read the connection type */
4605 p+=2;
4606
4607 /* Block count */
4608 count = *p++;
4609
4610 /* Recursively figure out the info blocks */
4611 if (*p < 128) {
4612 next_tick = dc_infoblock[COMPACT](dev, count, p);
4613 } else {
4614 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4615 }
4616 if (lp->tcount == count) {
4617 lp->media = NC;
4618 if (lp->media != lp->c_media) {
4619 de4x5_dbg_media(dev);
4620 lp->c_media = lp->media;
4621 }
4622 lp->media = INIT;
4623 lp->tcount = 0;
4624 lp->tx_enable = FALSE;
4625 }
4626
4627 return next_tick & ~TIMER_CB;
4628}
4629
4630/*
4631** The compact infoblock is only designed for DC21140[A] chips, so
4632** we'll reuse the dc21140m_autoconf function. Non MII media only.
4633*/
4634static int
4635compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4636{
4637 struct de4x5_private *lp = netdev_priv(dev);
4638 u_char flags, csr6;
4639
4640 /* Recursively figure out the info blocks */
4641 if (--count > lp->tcount) {
4642 if (*(p+COMPACT_LEN) < 128) {
4643 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4644 } else {
4645 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4646 }
4647 }
4648
4649 if ((lp->media == INIT) && (lp->timeout < 0)) {
4650 lp->ibn = COMPACT;
4651 lp->active = 0;
4652 gep_wr(lp->cache.gepc, dev);
4653 lp->infoblock_media = (*p++) & COMPACT_MC;
4654 lp->cache.gep = *p++;
4655 csr6 = *p++;
4656 flags = *p++;
4657
4658 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4659 lp->defMedium = (flags & 0x40) ? -1 : 0;
4660 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4661 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4662 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4663 lp->useMII = FALSE;
4664
4665 de4x5_switch_mac_port(dev);
4666 }
4667
4668 return dc21140m_autoconf(dev);
4669}
4670
4671/*
4672** This block describes non MII media for the DC21140[A] only.
4673*/
4674static int
4675type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4676{
4677 struct de4x5_private *lp = netdev_priv(dev);
4678 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4679
4680 /* Recursively figure out the info blocks */
4681 if (--count > lp->tcount) {
4682 if (*(p+len) < 128) {
4683 return dc_infoblock[COMPACT](dev, count, p+len);
4684 } else {
4685 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4686 }
4687 }
4688
4689 if ((lp->media == INIT) && (lp->timeout < 0)) {
4690 lp->ibn = 0;
4691 lp->active = 0;
4692 gep_wr(lp->cache.gepc, dev);
4693 p+=2;
4694 lp->infoblock_media = (*p++) & BLOCK0_MC;
4695 lp->cache.gep = *p++;
4696 csr6 = *p++;
4697 flags = *p++;
4698
4699 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4700 lp->defMedium = (flags & 0x40) ? -1 : 0;
4701 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4702 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4703 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4704 lp->useMII = FALSE;
4705
4706 de4x5_switch_mac_port(dev);
4707 }
4708
4709 return dc21140m_autoconf(dev);
4710}
4711
4712/* These functions are under construction! */
4713
4714static int
4715type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4716{
4717 struct de4x5_private *lp = netdev_priv(dev);
4718 u_char len = (*p & BLOCK_LEN)+1;
4719
4720 /* Recursively figure out the info blocks */
4721 if (--count > lp->tcount) {
4722 if (*(p+len) < 128) {
4723 return dc_infoblock[COMPACT](dev, count, p+len);
4724 } else {
4725 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4726 }
4727 }
4728
4729 p += 2;
4730 if (lp->state == INITIALISED) {
4731 lp->ibn = 1;
4732 lp->active = *p++;
4733 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4734 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4735 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4736 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4737 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4738 lp->phy[lp->active].ttm = TWIDDLE(p);
4739 return 0;
4740 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4741 lp->ibn = 1;
4742 lp->active = *p;
4743 lp->infoblock_csr6 = OMR_MII_100;
4744 lp->useMII = TRUE;
4745 lp->infoblock_media = ANS;
4746
4747 de4x5_switch_mac_port(dev);
4748 }
4749
4750 return dc21140m_autoconf(dev);
4751}
4752
4753static int
4754type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4755{
4756 struct de4x5_private *lp = netdev_priv(dev);
4757 u_char len = (*p & BLOCK_LEN)+1;
4758
4759 /* Recursively figure out the info blocks */
4760 if (--count > lp->tcount) {
4761 if (*(p+len) < 128) {
4762 return dc_infoblock[COMPACT](dev, count, p+len);
4763 } else {
4764 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4765 }
4766 }
4767
4768 if ((lp->media == INIT) && (lp->timeout < 0)) {
4769 lp->ibn = 2;
4770 lp->active = 0;
4771 p += 2;
4772 lp->infoblock_media = (*p) & MEDIA_CODE;
4773
4774 if ((*p++) & EXT_FIELD) {
4775 lp->cache.csr13 = TWIDDLE(p); p += 2;
4776 lp->cache.csr14 = TWIDDLE(p); p += 2;
4777 lp->cache.csr15 = TWIDDLE(p); p += 2;
4778 } else {
4779 lp->cache.csr13 = CSR13;
4780 lp->cache.csr14 = CSR14;
4781 lp->cache.csr15 = CSR15;
4782 }
4783 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4784 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4785 lp->infoblock_csr6 = OMR_SIA;
4786 lp->useMII = FALSE;
4787
4788 de4x5_switch_mac_port(dev);
4789 }
4790
4791 return dc2114x_autoconf(dev);
4792}
4793
4794static int
4795type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4796{
4797 struct de4x5_private *lp = netdev_priv(dev);
4798 u_char len = (*p & BLOCK_LEN)+1;
4799
4800 /* Recursively figure out the info blocks */
4801 if (--count > lp->tcount) {
4802 if (*(p+len) < 128) {
4803 return dc_infoblock[COMPACT](dev, count, p+len);
4804 } else {
4805 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4806 }
4807 }
4808
4809 p += 2;
4810 if (lp->state == INITIALISED) {
4811 lp->ibn = 3;
4812 lp->active = *p++;
4813 if (MOTO_SROM_BUG) lp->active = 0;
4814 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4815 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4816 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4817 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4818 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4819 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4820 lp->phy[lp->active].mci = *p;
4821 return 0;
4822 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4823 lp->ibn = 3;
4824 lp->active = *p;
4825 if (MOTO_SROM_BUG) lp->active = 0;
4826 lp->infoblock_csr6 = OMR_MII_100;
4827 lp->useMII = TRUE;
4828 lp->infoblock_media = ANS;
4829
4830 de4x5_switch_mac_port(dev);
4831 }
4832
4833 return dc2114x_autoconf(dev);
4834}
4835
4836static int
4837type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4838{
4839 struct de4x5_private *lp = netdev_priv(dev);
4840 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4841
4842 /* Recursively figure out the info blocks */
4843 if (--count > lp->tcount) {
4844 if (*(p+len) < 128) {
4845 return dc_infoblock[COMPACT](dev, count, p+len);
4846 } else {
4847 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4848 }
4849 }
4850
4851 if ((lp->media == INIT) && (lp->timeout < 0)) {
4852 lp->ibn = 4;
4853 lp->active = 0;
4854 p+=2;
4855 lp->infoblock_media = (*p++) & MEDIA_CODE;
4856 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4857 lp->cache.csr14 = CSR14;
4858 lp->cache.csr15 = CSR15;
4859 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4860 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4861 csr6 = *p++;
4862 flags = *p++;
4863
4864 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4865 lp->defMedium = (flags & 0x40) ? -1 : 0;
4866 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4867 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4868 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4869 lp->useMII = FALSE;
4870
4871 de4x5_switch_mac_port(dev);
4872 }
4873
4874 return dc2114x_autoconf(dev);
4875}
4876
4877/*
4878** This block type provides information for resetting external devices
4879** (chips) through the General Purpose Register.
4880*/
4881static int
4882type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4883{
4884 struct de4x5_private *lp = netdev_priv(dev);
4885 u_char len = (*p & BLOCK_LEN)+1;
4886
4887 /* Recursively figure out the info blocks */
4888 if (--count > lp->tcount) {
4889 if (*(p+len) < 128) {
4890 return dc_infoblock[COMPACT](dev, count, p+len);
4891 } else {
4892 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4893 }
4894 }
4895
4896 /* Must be initializing to run this code */
4897 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4898 p+=2;
4899 lp->rst = p;
4900 srom_exec(dev, lp->rst);
4901 }
4902
4903 return DE4X5_AUTOSENSE_MS;
4904}
4905
4906/*
4907** MII Read/Write
4908*/
4909
4910static int
4911mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4912{
4913 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4914 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4915 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4916 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4917 mii_address(phyreg, ioaddr); /* PHY Register to read */
4918 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4919
4920 return mii_rdata(ioaddr); /* Read data */
4921}
4922
4923static void
4924mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4925{
4926 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4927 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4928 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4929 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4930 mii_address(phyreg, ioaddr); /* PHY Register to write */
4931 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4932 data = mii_swap(data, 16); /* Swap data bit ordering */
4933 mii_wdata(data, 16, ioaddr); /* Write data */
4934
4935 return;
4936}
4937
4938static int
4939mii_rdata(u_long ioaddr)
4940{
4941 int i;
4942 s32 tmp = 0;
4943
4944 for (i=0; i<16; i++) {
4945 tmp <<= 1;
4946 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4947 }
4948
4949 return tmp;
4950}
4951
4952static void
4953mii_wdata(int data, int len, u_long ioaddr)
4954{
4955 int i;
4956
4957 for (i=0; i<len; i++) {
4958 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4959 data >>= 1;
4960 }
4961
4962 return;
4963}
4964
4965static void
4966mii_address(u_char addr, u_long ioaddr)
4967{
4968 int i;
4969
4970 addr = mii_swap(addr, 5);
4971 for (i=0; i<5; i++) {
4972 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4973 addr >>= 1;
4974 }
4975
4976 return;
4977}
4978
4979static void
4980mii_ta(u_long rw, u_long ioaddr)
4981{
4982 if (rw == MII_STWR) {
4983 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4984 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4985 } else {
4986 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4987 }
4988
4989 return;
4990}
4991
4992static int
4993mii_swap(int data, int len)
4994{
4995 int i, tmp = 0;
4996
4997 for (i=0; i<len; i++) {
4998 tmp <<= 1;
4999 tmp |= (data & 1);
5000 data >>= 1;
5001 }
5002
5003 return tmp;
5004}
5005
5006static void
5007sendto_mii(u32 command, int data, u_long ioaddr)
5008{
5009 u32 j;
5010
5011 j = (data & 1) << 17;
5012 outl(command | j, ioaddr);
5013 udelay(1);
5014 outl(command | MII_MDC | j, ioaddr);
5015 udelay(1);
5016
5017 return;
5018}
5019
5020static int
5021getfrom_mii(u32 command, u_long ioaddr)
5022{
5023 outl(command, ioaddr);
5024 udelay(1);
5025 outl(command | MII_MDC, ioaddr);
5026 udelay(1);
5027
5028 return ((inl(ioaddr) >> 19) & 1);
5029}
5030
5031/*
5032** Here's 3 ways to calculate the OUI from the ID registers.
5033*/
5034static int
5035mii_get_oui(u_char phyaddr, u_long ioaddr)
5036{
5037/*
5038 union {
5039 u_short reg;
5040 u_char breg[2];
5041 } a;
5042 int i, r2, r3, ret=0;*/
5043 int r2, r3;
5044
5045 /* Read r2 and r3 */
5046 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5047 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5048 /* SEEQ and Cypress way * /
5049 / * Shuffle r2 and r3 * /
5050 a.reg=0;
5051 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5052 r2 = ((r2>>2)&0x3fff);
5053
5054 / * Bit reverse r3 * /
5055 for (i=0;i<8;i++) {
5056 ret<<=1;
5057 ret |= (r3&1);
5058 r3>>=1;
5059 }
5060
5061 / * Bit reverse r2 * /
5062 for (i=0;i<16;i++) {
5063 a.reg<<=1;
5064 a.reg |= (r2&1);
5065 r2>>=1;
5066 }
5067
5068 / * Swap r2 bytes * /
5069 i=a.breg[0];
5070 a.breg[0]=a.breg[1];
5071 a.breg[1]=i;
5072
5073 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5074/* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5075 return r2; /* (I did it) My way */
5076}
5077
5078/*
5079** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5080*/
5081static int
5082mii_get_phy(struct net_device *dev)
5083{
5084 struct de4x5_private *lp = netdev_priv(dev);
5085 u_long iobase = dev->base_addr;
5086 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5087 int id;
5088
5089 lp->active = 0;
5090 lp->useMII = TRUE;
5091
5092 /* Search the MII address space for possible PHY devices */
5093 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5094 lp->phy[lp->active].addr = i;
5095 if (i==0) n++; /* Count cycles */
5096 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5097 id = mii_get_oui(i, DE4X5_MII);
5098 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5099 for (j=0; j<limit; j++) { /* Search PHY table */
5100 if (id != phy_info[j].id) continue; /* ID match? */
5101 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5102 if (k < DE4X5_MAX_PHY) {
5103 memcpy((char *)&lp->phy[k],
5104 (char *)&phy_info[j], sizeof(struct phy_table));
5105 lp->phy[k].addr = i;
5106 lp->mii_cnt++;
5107 lp->active++;
5108 } else {
5109 goto purgatory; /* Stop the search */
5110 }
5111 break;
5112 }
5113 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5114 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5115 lp->phy[k].addr = i;
5116 lp->phy[k].id = id;
5117 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5118 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5119 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5120 lp->mii_cnt++;
5121 lp->active++;
5122 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5123 j = de4x5_debug;
5124 de4x5_debug |= DEBUG_MII;
5125 de4x5_dbg_mii(dev, k);
5126 de4x5_debug = j;
5127 printk("\n");
5128 }
5129 }
5130 purgatory:
5131 lp->active = 0;
5132 if (lp->phy[0].id) { /* Reset the PHY devices */
5133 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5134 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5135 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5136
5137 de4x5_dbg_mii(dev, k);
5138 }
5139 }
5140 if (!lp->mii_cnt) lp->useMII = FALSE;
5141
5142 return lp->mii_cnt;
5143}
5144
5145static char *
5146build_setup_frame(struct net_device *dev, int mode)
5147{
5148 struct de4x5_private *lp = netdev_priv(dev);
5149 int i;
5150 char *pa = lp->setup_frame;
5151
5152 /* Initialise the setup frame */
5153 if (mode == ALL) {
5154 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5155 }
5156
5157 if (lp->setup_f == HASH_PERF) {
5158 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5159 *(pa + i) = dev->dev_addr[i]; /* Host address */
5160 if (i & 0x01) pa += 2;
5161 }
5162 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5163 } else {
5164 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5165 *(pa + (i&1)) = dev->dev_addr[i];
5166 if (i & 0x01) pa += 4;
5167 }
5168 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5169 *(pa + (i&1)) = (char) 0xff;
5170 if (i & 0x01) pa += 4;
5171 }
5172 }
5173
5174 return pa; /* Points to the next entry */
5175}
5176
5177static void
5178enable_ast(struct net_device *dev, u32 time_out)
5179{
5180 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5181
5182 return;
5183}
5184
5185static void
5186disable_ast(struct net_device *dev)
5187{
5188 struct de4x5_private *lp = netdev_priv(dev);
5189
5190 del_timer(&lp->timer);
5191
5192 return;
5193}
5194
5195static long
5196de4x5_switch_mac_port(struct net_device *dev)
5197{
5198 struct de4x5_private *lp = netdev_priv(dev);
5199 u_long iobase = dev->base_addr;
5200 s32 omr;
5201
5202 STOP_DE4X5;
5203
5204 /* Assert the OMR_PS bit in CSR6 */
5205 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5206 OMR_FDX));
5207 omr |= lp->infoblock_csr6;
5208 if (omr & OMR_PS) omr |= OMR_HBD;
5209 outl(omr, DE4X5_OMR);
5210
5211 /* Soft Reset */
5212 RESET_DE4X5;
5213
5214 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5215 if (lp->chipset == DC21140) {
5216 gep_wr(lp->cache.gepc, dev);
5217 gep_wr(lp->cache.gep, dev);
5218 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5219 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5220 }
5221
5222 /* Restore CSR6 */
5223 outl(omr, DE4X5_OMR);
5224
5225 /* Reset CSR8 */
5226 inl(DE4X5_MFC);
5227
5228 return omr;
5229}
5230
5231static void
5232gep_wr(s32 data, struct net_device *dev)
5233{
5234 struct de4x5_private *lp = netdev_priv(dev);
5235 u_long iobase = dev->base_addr;
5236
5237 if (lp->chipset == DC21140) {
5238 outl(data, DE4X5_GEP);
5239 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5240 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5241 }
5242
5243 return;
5244}
5245
5246static int
5247gep_rd(struct net_device *dev)
5248{
5249 struct de4x5_private *lp = netdev_priv(dev);
5250 u_long iobase = dev->base_addr;
5251
5252 if (lp->chipset == DC21140) {
5253 return inl(DE4X5_GEP);
5254 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5255 return (inl(DE4X5_SIGR) & 0x000fffff);
5256 }
5257
5258 return 0;
5259}
5260
5261static void
5262timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5263{
5264 struct de4x5_private *lp = netdev_priv(dev);
5265 int dt;
5266
5267 /* First, cancel any pending timer events */
5268 del_timer(&lp->timer);
5269
5270 /* Convert msec to ticks */
5271 dt = (msec * HZ) / 1000;
5272 if (dt==0) dt=1;
5273
5274 /* Set up timer */
5275 init_timer(&lp->timer);
5276 lp->timer.expires = jiffies + dt;
5277 lp->timer.function = fn;
5278 lp->timer.data = data;
5279 add_timer(&lp->timer);
5280
5281 return;
5282}
5283
5284static void
5285yawn(struct net_device *dev, int state)
5286{
5287 struct de4x5_private *lp = netdev_priv(dev);
5288 u_long iobase = dev->base_addr;
5289
5290 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5291
5292 if(lp->bus == EISA) {
5293 switch(state) {
5294 case WAKEUP:
5295 outb(WAKEUP, PCI_CFPM);
5296 mdelay(10);
5297 break;
5298
5299 case SNOOZE:
5300 outb(SNOOZE, PCI_CFPM);
5301 break;
5302
5303 case SLEEP:
5304 outl(0, DE4X5_SICR);
5305 outb(SLEEP, PCI_CFPM);
5306 break;
5307 }
5308 } else {
5309 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5310 switch(state) {
5311 case WAKEUP:
5312 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5313 mdelay(10);
5314 break;
5315
5316 case SNOOZE:
5317 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5318 break;
5319
5320 case SLEEP:
5321 outl(0, DE4X5_SICR);
5322 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5323 break;
5324 }
5325 }
5326
5327 return;
5328}
5329
5330static void
5331de4x5_parse_params(struct net_device *dev)
5332{
5333 struct de4x5_private *lp = netdev_priv(dev);
5334 char *p, *q, t;
5335
5336 lp->params.fdx = 0;
5337 lp->params.autosense = AUTO;
5338
5339 if (args == NULL) return;
5340
5341 if ((p = strstr(args, dev->name))) {
5342 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5343 t = *q;
5344 *q = '\0';
5345
5346 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5347
5348 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5349 if (strstr(p, "TP")) {
5350 lp->params.autosense = TP;
5351 } else if (strstr(p, "TP_NW")) {
5352 lp->params.autosense = TP_NW;
5353 } else if (strstr(p, "BNC")) {
5354 lp->params.autosense = BNC;
5355 } else if (strstr(p, "AUI")) {
5356 lp->params.autosense = AUI;
5357 } else if (strstr(p, "BNC_AUI")) {
5358 lp->params.autosense = BNC;
5359 } else if (strstr(p, "10Mb")) {
5360 lp->params.autosense = _10Mb;
5361 } else if (strstr(p, "100Mb")) {
5362 lp->params.autosense = _100Mb;
5363 } else if (strstr(p, "AUTO")) {
5364 lp->params.autosense = AUTO;
5365 }
5366 }
5367 *q = t;
5368 }
5369
5370 return;
5371}
5372
5373static void
5374de4x5_dbg_open(struct net_device *dev)
5375{
5376 struct de4x5_private *lp = netdev_priv(dev);
5377 int i;
5378
5379 if (de4x5_debug & DEBUG_OPEN) {
5380 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5381 printk("\tphysical address: ");
5382 for (i=0;i<6;i++) {
5383 printk("%2.2x:",(short)dev->dev_addr[i]);
5384 }
5385 printk("\n");
5386 printk("Descriptor head addresses:\n");
5387 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5388 printk("Descriptor addresses:\nRX: ");
5389 for (i=0;i<lp->rxRingSize-1;i++){
5390 if (i < 3) {
5391 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5392 }
5393 }
5394 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5395 printk("TX: ");
5396 for (i=0;i<lp->txRingSize-1;i++){
5397 if (i < 3) {
5398 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5399 }
5400 }
5401 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5402 printk("Descriptor buffers:\nRX: ");
5403 for (i=0;i<lp->rxRingSize-1;i++){
5404 if (i < 3) {
5405 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5406 }
5407 }
5408 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5409 printk("TX: ");
5410 for (i=0;i<lp->txRingSize-1;i++){
5411 if (i < 3) {
5412 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5413 }
5414 }
5415 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5416 printk("Ring size: \nRX: %d\nTX: %d\n",
5417 (short)lp->rxRingSize,
5418 (short)lp->txRingSize);
5419 }
5420
5421 return;
5422}
5423
5424static void
5425de4x5_dbg_mii(struct net_device *dev, int k)
5426{
5427 struct de4x5_private *lp = netdev_priv(dev);
5428 u_long iobase = dev->base_addr;
5429
5430 if (de4x5_debug & DEBUG_MII) {
5431 printk("\nMII device address: %d\n", lp->phy[k].addr);
5432 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5435 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5436 if (lp->phy[k].id != BROADCOM_T4) {
5437 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5438 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5439 }
5440 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5441 if (lp->phy[k].id != BROADCOM_T4) {
5442 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5443 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5444 } else {
5445 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5446 }
5447 }
5448
5449 return;
5450}
5451
5452static void
5453de4x5_dbg_media(struct net_device *dev)
5454{
5455 struct de4x5_private *lp = netdev_priv(dev);
5456
5457 if (lp->media != lp->c_media) {
5458 if (de4x5_debug & DEBUG_MEDIA) {
5459 printk("%s: media is %s%s\n", dev->name,
5460 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5461 (lp->media == TP ? "TP" :
5462 (lp->media == ANS ? "TP/Nway" :
5463 (lp->media == BNC ? "BNC" :
5464 (lp->media == AUI ? "AUI" :
5465 (lp->media == BNC_AUI ? "BNC/AUI" :
5466 (lp->media == EXT_SIA ? "EXT SIA" :
5467 (lp->media == _100Mb ? "100Mb/s" :
5468 (lp->media == _10Mb ? "10Mb/s" :
5469 "???"
5470 ))))))))), (lp->fdx?" full duplex.":"."));
5471 }
5472 lp->c_media = lp->media;
5473 }
5474
5475 return;
5476}
5477
5478static void
5479de4x5_dbg_srom(struct de4x5_srom *p)
5480{
5481 int i;
5482
5483 if (de4x5_debug & DEBUG_SROM) {
5484 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5485 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5486 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5487 printk("SROM version: %02x\n", (u_char)(p->version));
5488 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5489
5490 printk("Hardware Address: ");
5491 for (i=0;i<ETH_ALEN-1;i++) {
5492 printk("%02x:", (u_char)*(p->ieee_addr+i));
5493 }
5494 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5495 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5496 for (i=0; i<64; i++) {
5497 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5498 }
5499 }
5500
5501 return;
5502}
5503
5504static void
5505de4x5_dbg_rx(struct sk_buff *skb, int len)
5506{
5507 int i, j;
5508
5509 if (de4x5_debug & DEBUG_RX) {
5510 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5511 (u_char)skb->data[0],
5512 (u_char)skb->data[1],
5513 (u_char)skb->data[2],
5514 (u_char)skb->data[3],
5515 (u_char)skb->data[4],
5516 (u_char)skb->data[5],
5517 (u_char)skb->data[6],
5518 (u_char)skb->data[7],
5519 (u_char)skb->data[8],
5520 (u_char)skb->data[9],
5521 (u_char)skb->data[10],
5522 (u_char)skb->data[11],
5523 (u_char)skb->data[12],
5524 (u_char)skb->data[13],
5525 len);
5526 for (j=0; len>0;j+=16, len-=16) {
5527 printk(" %03x: ",j);
5528 for (i=0; i<16 && i<len; i++) {
5529 printk("%02x ",(u_char)skb->data[i+j]);
5530 }
5531 printk("\n");
5532 }
5533 }
5534
5535 return;
5536}
5537
5538/*
5539** Perform IOCTL call functions here. Some are privileged operations and the
5540** effective uid is checked in those cases. In the normal course of events
5541** this function is only used for my testing.
5542*/
5543static int
5544de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5545{
5546 struct de4x5_private *lp = netdev_priv(dev);
5547 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5548 u_long iobase = dev->base_addr;
5549 int i, j, status = 0;
5550 s32 omr;
5551 union {
5552 u8 addr[144];
5553 u16 sval[72];
5554 u32 lval[36];
5555 } tmp;
5556 u_long flags = 0;
5557
5558 switch(ioc->cmd) {
5559 case DE4X5_GET_HWADDR: /* Get the hardware address */
5560 ioc->len = ETH_ALEN;
5561 for (i=0; i<ETH_ALEN; i++) {
5562 tmp.addr[i] = dev->dev_addr[i];
5563 }
5564 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5565 break;
5566
5567 case DE4X5_SET_HWADDR: /* Set the hardware address */
5568 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5569 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5570 if (netif_queue_stopped(dev))
5571 return -EBUSY;
5572 netif_stop_queue(dev);
5573 for (i=0; i<ETH_ALEN; i++) {
5574 dev->dev_addr[i] = tmp.addr[i];
5575 }
5576 build_setup_frame(dev, PHYS_ADDR_ONLY);
5577 /* Set up the descriptor and give ownership to the card */
5578 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5579 SETUP_FRAME_LEN, (struct sk_buff *)1);
5580 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5581 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5582 netif_wake_queue(dev); /* Unlock the TX ring */
5583 break;
5584
5585 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5586 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5587 omr = inl(DE4X5_OMR);
5588 omr |= OMR_PR;
5589 outl(omr, DE4X5_OMR);
5590 dev->flags |= IFF_PROMISC;
5591 break;
5592
5593 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5594 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5595 omr = inl(DE4X5_OMR);
5596 omr &= ~OMR_PR;
5597 outl(omr, DE4X5_OMR);
5598 dev->flags &= ~IFF_PROMISC;
5599 break;
5600
5601 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5602 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5603 printk("%s: Boo!\n", dev->name);
5604 break;
5605
5606 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5607 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5608 omr = inl(DE4X5_OMR);
5609 omr |= OMR_PM;
5610 outl(omr, DE4X5_OMR);
5611 break;
5612
5613 case DE4X5_GET_STATS: /* Get the driver statistics */
5614 {
5615 struct pkt_stats statbuf;
5616 ioc->len = sizeof(statbuf);
5617 spin_lock_irqsave(&lp->lock, flags);
5618 memcpy(&statbuf, &lp->pktStats, ioc->len);
5619 spin_unlock_irqrestore(&lp->lock, flags);
5620 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5621 return -EFAULT;
5622 break;
5623 }
5624 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5625 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5626 spin_lock_irqsave(&lp->lock, flags);
5627 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5628 spin_unlock_irqrestore(&lp->lock, flags);
5629 break;
5630
5631 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5632 tmp.addr[0] = inl(DE4X5_OMR);
5633 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5634 break;
5635
5636 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5637 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5638 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5639 outl(tmp.addr[0], DE4X5_OMR);
5640 break;
5641
5642 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5643 j = 0;
5644 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5645 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5646 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5647 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5648 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5649 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5650 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5651 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5652 ioc->len = j;
5653 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5654 break;
5655
5656#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5657/*
5658 case DE4X5_DUMP:
5659 j = 0;
5660 tmp.addr[j++] = dev->irq;
5661 for (i=0; i<ETH_ALEN; i++) {
5662 tmp.addr[j++] = dev->dev_addr[i];
5663 }
5664 tmp.addr[j++] = lp->rxRingSize;
5665 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5666 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5667
5668 for (i=0;i<lp->rxRingSize-1;i++){
5669 if (i < 3) {
5670 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5671 }
5672 }
5673 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5674 for (i=0;i<lp->txRingSize-1;i++){
5675 if (i < 3) {
5676 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5677 }
5678 }
5679 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5680
5681 for (i=0;i<lp->rxRingSize-1;i++){
5682 if (i < 3) {
5683 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5684 }
5685 }
5686 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5687 for (i=0;i<lp->txRingSize-1;i++){
5688 if (i < 3) {
5689 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5690 }
5691 }
5692 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5693
5694 for (i=0;i<lp->rxRingSize;i++){
5695 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5696 }
5697 for (i=0;i<lp->txRingSize;i++){
5698 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5699 }
5700
5701 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5703 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5705 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5706 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5708 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5709 tmp.lval[j>>2] = lp->chipset; j+=4;
5710 if (lp->chipset == DC21140) {
5711 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5712 } else {
5713 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5714 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5715 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5716 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5717 }
5718 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5719 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5720 tmp.lval[j>>2] = lp->active; j+=4;
5721 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5722 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5725 if (lp->phy[lp->active].id != BROADCOM_T4) {
5726 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5727 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5728 }
5729 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5730 if (lp->phy[lp->active].id != BROADCOM_T4) {
5731 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5732 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5733 } else {
5734 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5735 }
5736 }
5737
5738 tmp.addr[j++] = lp->txRingSize;
5739 tmp.addr[j++] = netif_queue_stopped(dev);
5740
5741 ioc->len = j;
5742 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5743 break;
5744
5745*/
5746 default:
5747 return -EOPNOTSUPP;
5748 }
5749
5750 return status;
5751}
5752
5753static int __init de4x5_module_init (void)
5754{
5755 int err = 0;
5756
5757#ifdef CONFIG_PCI
5758 err = pci_module_init (&de4x5_pci_driver);
5759#endif
5760#ifdef CONFIG_EISA
5761 err |= eisa_driver_register (&de4x5_eisa_driver);
5762#endif
5763
5764 return err;
5765}
5766
5767static void __exit de4x5_module_exit (void)
5768{
5769#ifdef CONFIG_PCI
5770 pci_unregister_driver (&de4x5_pci_driver);
5771#endif
5772#ifdef CONFIG_EISA
5773 eisa_driver_unregister (&de4x5_eisa_driver);
5774#endif
5775}
5776
5777module_init (de4x5_module_init);
5778module_exit (de4x5_module_exit);
diff --git a/drivers/net/tulip/de4x5.h b/drivers/net/tulip/de4x5.h
new file mode 100644
index 000000000000..ad37a4074302
--- /dev/null
+++ b/drivers/net/tulip/de4x5.h
@@ -0,0 +1,1029 @@
1/*
2 Copyright 1994 Digital Equipment Corporation.
3
4 This software may be used and distributed according to the terms of the
5 GNU General Public License, incorporated herein by reference.
6
7 The author may be reached as davies@wanton.lkg.dec.com or Digital
8 Equipment Corporation, 550 King Street, Littleton MA 01460.
9
10 =========================================================================
11*/
12
13/*
14** DC21040 CSR<1..15> Register Address Map
15*/
16#define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17#define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18#define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19#define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20#define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21#define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22#define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23#define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24#define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25#define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
26#define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */
27#define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */
28#define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
29#define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */
30#define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */
31#define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/
32#define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */
33#define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */
34#define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */
35#define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */
36#define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */
37
38/*
39** EISA Register Address Map
40*/
41#define EISA_ID iobase+0x0c80 /* EISA ID Registers */
42#define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */
43#define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */
44#define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */
45#define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */
46#define EISA_CR iobase+0x0c84 /* EISA Control Register */
47#define EISA_REG0 iobase+0x0c88 /* EISA Configuration Register 0 */
48#define EISA_REG1 iobase+0x0c89 /* EISA Configuration Register 1 */
49#define EISA_REG2 iobase+0x0c8a /* EISA Configuration Register 2 */
50#define EISA_REG3 iobase+0x0c8f /* EISA Configuration Register 3 */
51#define EISA_APROM iobase+0x0c90 /* Ethernet Address PROM */
52
53/*
54** PCI/EISA Configuration Registers Address Map
55*/
56#define PCI_CFID iobase+0x0008 /* PCI Configuration ID Register */
57#define PCI_CFCS iobase+0x000c /* PCI Command/Status Register */
58#define PCI_CFRV iobase+0x0018 /* PCI Revision Register */
59#define PCI_CFLT iobase+0x001c /* PCI Latency Timer Register */
60#define PCI_CBIO iobase+0x0028 /* PCI Base I/O Register */
61#define PCI_CBMA iobase+0x002c /* PCI Base Memory Address Register */
62#define PCI_CBER iobase+0x0030 /* PCI Expansion ROM Base Address Reg. */
63#define PCI_CFIT iobase+0x003c /* PCI Configuration Interrupt Register */
64#define PCI_CFDA iobase+0x0040 /* PCI Driver Area Register */
65#define PCI_CFDD iobase+0x0041 /* PCI Driver Dependent Area Register */
66#define PCI_CFPM iobase+0x0043 /* PCI Power Management Area Register */
67
68/*
69** EISA Configuration Register 0 bit definitions
70*/
71#define ER0_BSW 0x80 /* EISA Bus Slave Width, 1: 32 bits */
72#define ER0_BMW 0x40 /* EISA Bus Master Width, 1: 32 bits */
73#define ER0_EPT 0x20 /* EISA PREEMPT Time, 0: 23 BCLKs */
74#define ER0_ISTS 0x10 /* Interrupt Status (X) */
75#define ER0_LI 0x08 /* Latch Interrupts */
76#define ER0_INTL 0x06 /* INTerrupt Level */
77#define ER0_INTT 0x01 /* INTerrupt Type, 0: Level, 1: Edge */
78
79/*
80** EISA Configuration Register 1 bit definitions
81*/
82#define ER1_IAM 0xe0 /* ISA Address Mode */
83#define ER1_IAE 0x10 /* ISA Addressing Enable */
84#define ER1_UPIN 0x0f /* User Pins */
85
86/*
87** EISA Configuration Register 2 bit definitions
88*/
89#define ER2_BRS 0xc0 /* Boot ROM Size */
90#define ER2_BRA 0x3c /* Boot ROM Address <16:13> */
91
92/*
93** EISA Configuration Register 3 bit definitions
94*/
95#define ER3_BWE 0x40 /* Burst Write Enable */
96#define ER3_BRE 0x04 /* Burst Read Enable */
97#define ER3_LSR 0x02 /* Local Software Reset */
98
99/*
100** PCI Configuration ID Register (PCI_CFID). The Device IDs are left
101** shifted 8 bits to allow detection of DC21142 and DC21143 variants with
102** the configuration revision register step number.
103*/
104#define CFID_DID 0xff00 /* Device ID */
105#define CFID_VID 0x00ff /* Vendor ID */
106#define DC21040_DID 0x0200 /* Unique Device ID # */
107#define DC21040_VID 0x1011 /* DC21040 Manufacturer */
108#define DC21041_DID 0x1400 /* Unique Device ID # */
109#define DC21041_VID 0x1011 /* DC21041 Manufacturer */
110#define DC21140_DID 0x0900 /* Unique Device ID # */
111#define DC21140_VID 0x1011 /* DC21140 Manufacturer */
112#define DC2114x_DID 0x1900 /* Unique Device ID # */
113#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */
114
115/*
116** Chipset defines
117*/
118#define DC21040 DC21040_DID
119#define DC21041 DC21041_DID
120#define DC21140 DC21140_DID
121#define DC2114x DC2114x_DID
122#define DC21142 (DC2114x_DID | 0x0010)
123#define DC21143 (DC2114x_DID | 0x0030)
124#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
125
126#define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID))
127#define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID))
128#define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID))
129#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID))
130#define is_DC21142 ((vendor == DC2114x_VID) && (device == DC21142))
131#define is_DC21143 ((vendor == DC2114x_VID) && (device == DC21143))
132
133/*
134** PCI Configuration Command/Status Register (PCI_CFCS)
135*/
136#define CFCS_DPE 0x80000000 /* Detected Parity Error (S) */
137#define CFCS_SSE 0x40000000 /* Signal System Error (S) */
138#define CFCS_RMA 0x20000000 /* Receive Master Abort (S) */
139#define CFCS_RTA 0x10000000 /* Receive Target Abort (S) */
140#define CFCS_DST 0x06000000 /* DEVSEL Timing (S) */
141#define CFCS_DPR 0x01000000 /* Data Parity Report (S) */
142#define CFCS_FBB 0x00800000 /* Fast Back-To-Back (S) */
143#define CFCS_SEE 0x00000100 /* System Error Enable (C) */
144#define CFCS_PER 0x00000040 /* Parity Error Response (C) */
145#define CFCS_MO 0x00000004 /* Master Operation (C) */
146#define CFCS_MSA 0x00000002 /* Memory Space Access (C) */
147#define CFCS_IOSA 0x00000001 /* I/O Space Access (C) */
148
149/*
150** PCI Configuration Revision Register (PCI_CFRV)
151*/
152#define CFRV_BC 0xff000000 /* Base Class */
153#define CFRV_SC 0x00ff0000 /* Subclass */
154#define CFRV_RN 0x000000f0 /* Revision Number */
155#define CFRV_SN 0x0000000f /* Step Number */
156#define BASE_CLASS 0x02000000 /* Indicates Network Controller */
157#define SUB_CLASS 0x00000000 /* Indicates Ethernet Controller */
158#define STEP_NUMBER 0x00000020 /* Increments for future chips */
159#define REV_NUMBER 0x00000003 /* 0x00, 0x01, 0x02, 0x03: Rev in Step */
160#define CFRV_MASK 0xffff0000 /* Register mask */
161
162/*
163** PCI Configuration Latency Timer Register (PCI_CFLT)
164*/
165#define CFLT_BC 0x0000ff00 /* Latency Timer bits */
166
167/*
168** PCI Configuration Base I/O Address Register (PCI_CBIO)
169*/
170#define CBIO_MASK -128 /* Base I/O Address Mask */
171#define CBIO_IOSI 0x00000001 /* I/O Space Indicator (RO, value is 1) */
172
173/*
174** PCI Configuration Card Information Structure Register (PCI_CCIS)
175*/
176#define CCIS_ROMI 0xf0000000 /* ROM Image */
177#define CCIS_ASO 0x0ffffff8 /* Address Space Offset */
178#define CCIS_ASI 0x00000007 /* Address Space Indicator */
179
180/*
181** PCI Configuration Subsystem ID Register (PCI_SSID)
182*/
183#define SSID_SSID 0xffff0000 /* Subsystem ID */
184#define SSID_SVID 0x0000ffff /* Subsystem Vendor ID */
185
186/*
187** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
188*/
189#define CBER_MASK 0xfffffc00 /* Expansion ROM Base Address Mask */
190#define CBER_ROME 0x00000001 /* ROM Enable */
191
192/*
193** PCI Configuration Interrupt Register (PCI_CFIT)
194*/
195#define CFIT_MXLT 0xff000000 /* MAX_LAT Value (0.25us periods) */
196#define CFIT_MNGT 0x00ff0000 /* MIN_GNT Value (0.25us periods) */
197#define CFIT_IRQP 0x0000ff00 /* Interrupt Pin */
198#define CFIT_IRQL 0x000000ff /* Interrupt Line */
199
200/*
201** PCI Configuration Power Management Area Register (PCI_CFPM)
202*/
203#define SLEEP 0x80 /* Power Saving Sleep Mode */
204#define SNOOZE 0x40 /* Power Saving Snooze Mode */
205#define WAKEUP 0x00 /* Power Saving Wakeup */
206
207#define PCI_CFDA_DSU 0x41 /* 8 bit Configuration Space Address */
208#define PCI_CFDA_PSM 0x43 /* 8 bit Configuration Space Address */
209
210/*
211** DC21040 Bus Mode Register (DE4X5_BMR)
212*/
213#define BMR_RML 0x00200000 /* [Memory] Read Multiple */
214#define BMR_DBO 0x00100000 /* Descriptor Byte Ordering (Endian) */
215#define BMR_TAP 0x000e0000 /* Transmit Automatic Polling */
216#define BMR_DAS 0x00010000 /* Diagnostic Address Space */
217#define BMR_CAL 0x0000c000 /* Cache Alignment */
218#define BMR_PBL 0x00003f00 /* Programmable Burst Length */
219#define BMR_BLE 0x00000080 /* Big/Little Endian */
220#define BMR_DSL 0x0000007c /* Descriptor Skip Length */
221#define BMR_BAR 0x00000002 /* Bus ARbitration */
222#define BMR_SWR 0x00000001 /* Software Reset */
223
224 /* Timings here are for 10BASE-T/AUI only*/
225#define TAP_NOPOLL 0x00000000 /* No automatic polling */
226#define TAP_200US 0x00020000 /* TX automatic polling every 200us */
227#define TAP_800US 0x00040000 /* TX automatic polling every 800us */
228#define TAP_1_6MS 0x00060000 /* TX automatic polling every 1.6ms */
229#define TAP_12_8US 0x00080000 /* TX automatic polling every 12.8us */
230#define TAP_25_6US 0x000a0000 /* TX automatic polling every 25.6us */
231#define TAP_51_2US 0x000c0000 /* TX automatic polling every 51.2us */
232#define TAP_102_4US 0x000e0000 /* TX automatic polling every 102.4us */
233
234#define CAL_NOUSE 0x00000000 /* Not used */
235#define CAL_8LONG 0x00004000 /* 8-longword alignment */
236#define CAL_16LONG 0x00008000 /* 16-longword alignment */
237#define CAL_32LONG 0x0000c000 /* 32-longword alignment */
238
239#define PBL_0 0x00000000 /* DMA burst length = amount in RX FIFO */
240#define PBL_1 0x00000100 /* 1 longword DMA burst length */
241#define PBL_2 0x00000200 /* 2 longwords DMA burst length */
242#define PBL_4 0x00000400 /* 4 longwords DMA burst length */
243#define PBL_8 0x00000800 /* 8 longwords DMA burst length */
244#define PBL_16 0x00001000 /* 16 longwords DMA burst length */
245#define PBL_32 0x00002000 /* 32 longwords DMA burst length */
246
247#define DSL_0 0x00000000 /* 0 longword / descriptor */
248#define DSL_1 0x00000004 /* 1 longword / descriptor */
249#define DSL_2 0x00000008 /* 2 longwords / descriptor */
250#define DSL_4 0x00000010 /* 4 longwords / descriptor */
251#define DSL_8 0x00000020 /* 8 longwords / descriptor */
252#define DSL_16 0x00000040 /* 16 longwords / descriptor */
253#define DSL_32 0x00000080 /* 32 longwords / descriptor */
254
255/*
256** DC21040 Transmit Poll Demand Register (DE4X5_TPD)
257*/
258#define TPD 0x00000001 /* Transmit Poll Demand */
259
260/*
261** DC21040 Receive Poll Demand Register (DE4X5_RPD)
262*/
263#define RPD 0x00000001 /* Receive Poll Demand */
264
265/*
266** DC21040 Receive Ring Base Address Register (DE4X5_RRBA)
267*/
268#define RRBA 0xfffffffc /* RX Descriptor List Start Address */
269
270/*
271** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA)
272*/
273#define TRBA 0xfffffffc /* TX Descriptor List Start Address */
274
275/*
276** Status Register (DE4X5_STS)
277*/
278#define STS_GPI 0x04000000 /* General Purpose Port Interrupt */
279#define STS_BE 0x03800000 /* Bus Error Bits */
280#define STS_TS 0x00700000 /* Transmit Process State */
281#define STS_RS 0x000e0000 /* Receive Process State */
282#define STS_NIS 0x00010000 /* Normal Interrupt Summary */
283#define STS_AIS 0x00008000 /* Abnormal Interrupt Summary */
284#define STS_ER 0x00004000 /* Early Receive */
285#define STS_FBE 0x00002000 /* Fatal Bus Error */
286#define STS_SE 0x00002000 /* System Error */
287#define STS_LNF 0x00001000 /* Link Fail */
288#define STS_FD 0x00000800 /* Full-Duplex Short Frame Received */
289#define STS_TM 0x00000800 /* Timer Expired (DC21041) */
290#define STS_ETI 0x00000400 /* Early Transmit Interrupt */
291#define STS_AT 0x00000400 /* AUI/TP Pin */
292#define STS_RWT 0x00000200 /* Receive Watchdog Time-Out */
293#define STS_RPS 0x00000100 /* Receive Process Stopped */
294#define STS_RU 0x00000080 /* Receive Buffer Unavailable */
295#define STS_RI 0x00000040 /* Receive Interrupt */
296#define STS_UNF 0x00000020 /* Transmit Underflow */
297#define STS_LNP 0x00000010 /* Link Pass */
298#define STS_ANC 0x00000010 /* Autonegotiation Complete */
299#define STS_TJT 0x00000008 /* Transmit Jabber Time-Out */
300#define STS_TU 0x00000004 /* Transmit Buffer Unavailable */
301#define STS_TPS 0x00000002 /* Transmit Process Stopped */
302#define STS_TI 0x00000001 /* Transmit Interrupt */
303
304#define EB_PAR 0x00000000 /* Parity Error */
305#define EB_MA 0x00800000 /* Master Abort */
306#define EB_TA 0x01000000 /* Target Abort */
307#define EB_RES0 0x01800000 /* Reserved */
308#define EB_RES1 0x02000000 /* Reserved */
309
310#define TS_STOP 0x00000000 /* Stopped */
311#define TS_FTD 0x00100000 /* Fetch Transmit Descriptor */
312#define TS_WEOT 0x00200000 /* Wait for End Of Transmission */
313#define TS_QDAT 0x00300000 /* Queue skb data into TX FIFO */
314#define TS_RES 0x00400000 /* Reserved */
315#define TS_SPKT 0x00500000 /* Setup Packet */
316#define TS_SUSP 0x00600000 /* Suspended */
317#define TS_CLTD 0x00700000 /* Close Transmit Descriptor */
318
319#define RS_STOP 0x00000000 /* Stopped */
320#define RS_FRD 0x00020000 /* Fetch Receive Descriptor */
321#define RS_CEOR 0x00040000 /* Check for End of Receive Packet */
322#define RS_WFRP 0x00060000 /* Wait for Receive Packet */
323#define RS_SUSP 0x00080000 /* Suspended */
324#define RS_CLRD 0x000a0000 /* Close Receive Descriptor */
325#define RS_FLUSH 0x000c0000 /* Flush RX FIFO */
326#define RS_QRFS 0x000e0000 /* Queue RX FIFO into RX Skb */
327
328#define INT_CANCEL 0x0001ffff /* For zeroing all interrupt sources */
329
330/*
331** Operation Mode Register (DE4X5_OMR)
332*/
333#define OMR_SC 0x80000000 /* Special Capture Effect Enable */
334#define OMR_RA 0x40000000 /* Receive All */
335#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
336#define OMR_SCR 0x01000000 /* Scrambler Mode */
337#define OMR_PCS 0x00800000 /* PCS Function */
338#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
339#define OMR_SF 0x00200000 /* Store and Forward */
340#define OMR_HBD 0x00080000 /* HeartBeat Disable */
341#define OMR_PS 0x00040000 /* Port Select */
342#define OMR_CA 0x00020000 /* Capture Effect Enable */
343#define OMR_BP 0x00010000 /* Back Pressure */
344#define OMR_TR 0x0000c000 /* Threshold Control Bits */
345#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
346#define OMR_FC 0x00001000 /* Force Collision Mode */
347#define OMR_OM 0x00000c00 /* Operating Mode */
348#define OMR_FDX 0x00000200 /* Full Duplex Mode */
349#define OMR_FKD 0x00000100 /* Flaky Oscillator Disable */
350#define OMR_PM 0x00000080 /* Pass All Multicast */
351#define OMR_PR 0x00000040 /* Promiscuous Mode */
352#define OMR_SB 0x00000020 /* Start/Stop Backoff Counter */
353#define OMR_IF 0x00000010 /* Inverse Filtering */
354#define OMR_PB 0x00000008 /* Pass Bad Frames */
355#define OMR_HO 0x00000004 /* Hash Only Filtering Mode */
356#define OMR_SR 0x00000002 /* Start/Stop Receive */
357#define OMR_HP 0x00000001 /* Hash/Perfect Receive Filtering Mode */
358
359#define TR_72 0x00000000 /* Threshold set to 72 (128) bytes */
360#define TR_96 0x00004000 /* Threshold set to 96 (256) bytes */
361#define TR_128 0x00008000 /* Threshold set to 128 (512) bytes */
362#define TR_160 0x0000c000 /* Threshold set to 160 (1024) bytes */
363
364#define OMR_DEF (OMR_SDP)
365#define OMR_SIA (OMR_SDP | OMR_TTM)
366#define OMR_SYM (OMR_SDP | OMR_SCR | OMR_PCS | OMR_HBD | OMR_PS)
367#define OMR_MII_10 (OMR_SDP | OMR_TTM | OMR_PS)
368#define OMR_MII_100 (OMR_SDP | OMR_HBD | OMR_PS)
369
370/*
371** DC21040 Interrupt Mask Register (DE4X5_IMR)
372*/
373#define IMR_GPM 0x04000000 /* General Purpose Port Mask */
374#define IMR_NIM 0x00010000 /* Normal Interrupt Summary Mask */
375#define IMR_AIM 0x00008000 /* Abnormal Interrupt Summary Mask */
376#define IMR_ERM 0x00004000 /* Early Receive Mask */
377#define IMR_FBM 0x00002000 /* Fatal Bus Error Mask */
378#define IMR_SEM 0x00002000 /* System Error Mask */
379#define IMR_LFM 0x00001000 /* Link Fail Mask */
380#define IMR_FDM 0x00000800 /* Full-Duplex (Short Frame) Mask */
381#define IMR_TMM 0x00000800 /* Timer Expired Mask (DC21041) */
382#define IMR_ETM 0x00000400 /* Early Transmit Interrupt Mask */
383#define IMR_ATM 0x00000400 /* AUI/TP Switch Mask */
384#define IMR_RWM 0x00000200 /* Receive Watchdog Time-Out Mask */
385#define IMR_RSM 0x00000100 /* Receive Stopped Mask */
386#define IMR_RUM 0x00000080 /* Receive Buffer Unavailable Mask */
387#define IMR_RIM 0x00000040 /* Receive Interrupt Mask */
388#define IMR_UNM 0x00000020 /* Underflow Interrupt Mask */
389#define IMR_ANM 0x00000010 /* Autonegotiation Complete Mask */
390#define IMR_LPM 0x00000010 /* Link Pass */
391#define IMR_TJM 0x00000008 /* Transmit Time-Out Jabber Mask */
392#define IMR_TUM 0x00000004 /* Transmit Buffer Unavailable Mask */
393#define IMR_TSM 0x00000002 /* Transmission Stopped Mask */
394#define IMR_TIM 0x00000001 /* Transmit Interrupt Mask */
395
396/*
397** Missed Frames and FIFO Overflow Counters (DE4X5_MFC)
398*/
399#define MFC_FOCO 0x10000000 /* FIFO Overflow Counter Overflow Bit */
400#define MFC_FOC 0x0ffe0000 /* FIFO Overflow Counter Bits */
401#define MFC_OVFL 0x00010000 /* Missed Frames Counter Overflow Bit */
402#define MFC_CNTR 0x0000ffff /* Missed Frames Counter Bits */
403#define MFC_FOCM 0x1ffe0000 /* FIFO Overflow Counter Mask */
404
405/*
406** DC21040 Ethernet Address PROM (DE4X5_APROM)
407*/
408#define APROM_DN 0x80000000 /* Data Not Valid */
409#define APROM_DT 0x000000ff /* Address Byte */
410
411/*
412** DC21041 Boot/Ethernet Address ROM (DE4X5_BROM)
413*/
414#define BROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */
415#define BROM_RD 0x00004000 /* Read from Boot ROM */
416#define BROM_WR 0x00002000 /* Write to Boot ROM */
417#define BROM_BR 0x00001000 /* Select Boot ROM when set */
418#define BROM_SR 0x00000800 /* Select Serial ROM when set */
419#define BROM_REG 0x00000400 /* External Register Select */
420#define BROM_DT 0x000000ff /* Data Byte */
421
422/*
423** DC21041 Serial/Ethernet Address ROM (DE4X5_SROM, DE4X5_MII)
424*/
425#define MII_MDI 0x00080000 /* MII Management Data In */
426#define MII_MDO 0x00060000 /* MII Management Mode/Data Out */
427#define MII_MRD 0x00040000 /* MII Management Define Read Mode */
428#define MII_MWR 0x00000000 /* MII Management Define Write Mode */
429#define MII_MDT 0x00020000 /* MII Management Data Out */
430#define MII_MDC 0x00010000 /* MII Management Clock */
431#define MII_RD 0x00004000 /* Read from MII */
432#define MII_WR 0x00002000 /* Write to MII */
433#define MII_SEL 0x00000800 /* Select MII when RESET */
434
435#define SROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */
436#define SROM_RD 0x00004000 /* Read from Boot ROM */
437#define SROM_WR 0x00002000 /* Write to Boot ROM */
438#define SROM_BR 0x00001000 /* Select Boot ROM when set */
439#define SROM_SR 0x00000800 /* Select Serial ROM when set */
440#define SROM_REG 0x00000400 /* External Register Select */
441#define SROM_DT 0x000000ff /* Data Byte */
442
443#define DT_OUT 0x00000008 /* Serial Data Out */
444#define DT_IN 0x00000004 /* Serial Data In */
445#define DT_CLK 0x00000002 /* Serial ROM Clock */
446#define DT_CS 0x00000001 /* Serial ROM Chip Select */
447
448#define MII_PREAMBLE 0xffffffff /* MII Management Preamble */
449#define MII_TEST 0xaaaaaaaa /* MII Test Signal */
450#define MII_STRD 0x06 /* Start of Frame+Op Code: use low nibble */
451#define MII_STWR 0x0a /* Start of Frame+Op Code: use low nibble */
452
453#define MII_CR 0x00 /* MII Management Control Register */
454#define MII_SR 0x01 /* MII Management Status Register */
455#define MII_ID0 0x02 /* PHY Identifier Register 0 */
456#define MII_ID1 0x03 /* PHY Identifier Register 1 */
457#define MII_ANA 0x04 /* Auto Negotiation Advertisement */
458#define MII_ANLPA 0x05 /* Auto Negotiation Link Partner Ability */
459#define MII_ANE 0x06 /* Auto Negotiation Expansion */
460#define MII_ANP 0x07 /* Auto Negotiation Next Page TX */
461
462#define DE4X5_MAX_MII 32 /* Maximum address of MII PHY devices */
463
464/*
465** MII Management Control Register
466*/
467#define MII_CR_RST 0x8000 /* RESET the PHY chip */
468#define MII_CR_LPBK 0x4000 /* Loopback enable */
469#define MII_CR_SPD 0x2000 /* 0: 10Mb/s; 1: 100Mb/s */
470#define MII_CR_10 0x0000 /* Set 10Mb/s */
471#define MII_CR_100 0x2000 /* Set 100Mb/s */
472#define MII_CR_ASSE 0x1000 /* Auto Speed Select Enable */
473#define MII_CR_PD 0x0800 /* Power Down */
474#define MII_CR_ISOL 0x0400 /* Isolate Mode */
475#define MII_CR_RAN 0x0200 /* Restart Auto Negotiation */
476#define MII_CR_FDM 0x0100 /* Full Duplex Mode */
477#define MII_CR_CTE 0x0080 /* Collision Test Enable */
478
479/*
480** MII Management Status Register
481*/
482#define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */
483#define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */
484#define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */
485#define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */
486#define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */
487#define MII_SR_ASSC 0x0020 /* Auto Speed Selection Complete*/
488#define MII_SR_RFD 0x0010 /* Remote Fault Detected */
489#define MII_SR_ANC 0x0008 /* Auto Negotiation capable */
490#define MII_SR_LKS 0x0004 /* Link Status */
491#define MII_SR_JABD 0x0002 /* Jabber Detect */
492#define MII_SR_XC 0x0001 /* Extended Capabilities */
493
494/*
495** MII Management Auto Negotiation Advertisement Register
496*/
497#define MII_ANA_TAF 0x03e0 /* Technology Ability Field */
498#define MII_ANA_T4AM 0x0200 /* T4 Technology Ability Mask */
499#define MII_ANA_TXAM 0x0180 /* TX Technology Ability Mask */
500#define MII_ANA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
501#define MII_ANA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
502#define MII_ANA_100M 0x0380 /* 100Mb Technology Ability Mask */
503#define MII_ANA_10M 0x0060 /* 10Mb Technology Ability Mask */
504#define MII_ANA_CSMA 0x0001 /* CSMA-CD Capable */
505
506/*
507** MII Management Auto Negotiation Remote End Register
508*/
509#define MII_ANLPA_NP 0x8000 /* Next Page (Enable) */
510#define MII_ANLPA_ACK 0x4000 /* Remote Acknowledge */
511#define MII_ANLPA_RF 0x2000 /* Remote Fault */
512#define MII_ANLPA_TAF 0x03e0 /* Technology Ability Field */
513#define MII_ANLPA_T4AM 0x0200 /* T4 Technology Ability Mask */
514#define MII_ANLPA_TXAM 0x0180 /* TX Technology Ability Mask */
515#define MII_ANLPA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
516#define MII_ANLPA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
517#define MII_ANLPA_100M 0x0380 /* 100Mb Technology Ability Mask */
518#define MII_ANLPA_10M 0x0060 /* 10Mb Technology Ability Mask */
519#define MII_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */
520
521/*
522** SROM Media Definitions (ABG SROM Section)
523*/
524#define MEDIA_NWAY 0x0080 /* Nway (Auto Negotiation) on PHY */
525#define MEDIA_MII 0x0040 /* MII Present on the adapter */
526#define MEDIA_FIBRE 0x0008 /* Fibre Media present */
527#define MEDIA_AUI 0x0004 /* AUI Media present */
528#define MEDIA_TP 0x0002 /* TP Media present */
529#define MEDIA_BNC 0x0001 /* BNC Media present */
530
531/*
532** SROM Definitions (Digital Semiconductor Format)
533*/
534#define SROM_SSVID 0x0000 /* Sub-system Vendor ID offset */
535#define SROM_SSID 0x0002 /* Sub-system ID offset */
536#define SROM_CISPL 0x0004 /* CardBus CIS Pointer low offset */
537#define SROM_CISPH 0x0006 /* CardBus CIS Pointer high offset */
538#define SROM_IDCRC 0x0010 /* ID Block CRC offset*/
539#define SROM_RSVD2 0x0011 /* ID Reserved 2 offset */
540#define SROM_SFV 0x0012 /* SROM Format Version offset */
541#define SROM_CCNT 0x0013 /* Controller Count offset */
542#define SROM_HWADD 0x0014 /* Hardware Address offset */
543#define SROM_MRSVD 0x007c /* Manufacturer Reserved offset*/
544#define SROM_CRC 0x007e /* SROM CRC offset */
545
546/*
547** SROM Media Connection Definitions
548*/
549#define SROM_10BT 0x0000 /* 10BASE-T half duplex */
550#define SROM_10BTN 0x0100 /* 10BASE-T with Nway */
551#define SROM_10BTF 0x0204 /* 10BASE-T full duplex */
552#define SROM_10BTNLP 0x0400 /* 10BASE-T without Link Pass test */
553#define SROM_10B2 0x0001 /* 10BASE-2 (BNC) */
554#define SROM_10B5 0x0002 /* 10BASE-5 (AUI) */
555#define SROM_100BTH 0x0003 /* 100BASE-T half duplex */
556#define SROM_100BTF 0x0205 /* 100BASE-T full duplex */
557#define SROM_100BT4 0x0006 /* 100BASE-T4 */
558#define SROM_100BFX 0x0007 /* 100BASE-FX half duplex (Fiber) */
559#define SROM_M10BT 0x0009 /* MII 10BASE-T half duplex */
560#define SROM_M10BTF 0x020a /* MII 10BASE-T full duplex */
561#define SROM_M100BT 0x000d /* MII 100BASE-T half duplex */
562#define SROM_M100BTF 0x020e /* MII 100BASE-T full duplex */
563#define SROM_M100BT4 0x000f /* MII 100BASE-T4 */
564#define SROM_M100BF 0x0010 /* MII 100BASE-FX half duplex */
565#define SROM_M100BFF 0x0211 /* MII 100BASE-FX full duplex */
566#define SROM_PDA 0x0800 /* Powerup & Dynamic Autosense */
567#define SROM_PAO 0x8800 /* Powerup Autosense Only */
568#define SROM_NSMI 0xffff /* No Selected Media Information */
569
570/*
571** SROM Media Definitions
572*/
573#define SROM_10BASET 0x0000 /* 10BASE-T half duplex */
574#define SROM_10BASE2 0x0001 /* 10BASE-2 (BNC) */
575#define SROM_10BASE5 0x0002 /* 10BASE-5 (AUI) */
576#define SROM_100BASET 0x0003 /* 100BASE-T half duplex */
577#define SROM_10BASETF 0x0004 /* 10BASE-T full duplex */
578#define SROM_100BASETF 0x0005 /* 100BASE-T full duplex */
579#define SROM_100BASET4 0x0006 /* 100BASE-T4 */
580#define SROM_100BASEF 0x0007 /* 100BASE-FX half duplex */
581#define SROM_100BASEFF 0x0008 /* 100BASE-FX full duplex */
582
583#define BLOCK_LEN 0x7f /* Extended blocks length mask */
584#define EXT_FIELD 0x40 /* Extended blocks extension field bit */
585#define MEDIA_CODE 0x3f /* Extended blocks media code mask */
586
587/*
588** SROM Compact Format Block Masks
589*/
590#define COMPACT_FI 0x80 /* Format Indicator */
591#define COMPACT_LEN 0x04 /* Length */
592#define COMPACT_MC 0x3f /* Media Code */
593
594/*
595** SROM Extended Format Block Type 0 Masks
596*/
597#define BLOCK0_FI 0x80 /* Format Indicator */
598#define BLOCK0_MCS 0x80 /* Media Code byte Sign */
599#define BLOCK0_MC 0x3f /* Media Code */
600
601/*
602** DC21040 Full Duplex Register (DE4X5_FDR)
603*/
604#define FDR_FDACV 0x0000ffff /* Full Duplex Auto Configuration Value */
605
606/*
607** DC21041 General Purpose Timer Register (DE4X5_GPT)
608*/
609#define GPT_CON 0x00010000 /* One shot: 0, Continuous: 1 */
610#define GPT_VAL 0x0000ffff /* Timer Value */
611
612/*
613** DC21140 General Purpose Register (DE4X5_GEP) (hardware dependent bits)
614*/
615/* Valid ONLY for DE500 hardware */
616#define GEP_LNP 0x00000080 /* Link Pass (input) */
617#define GEP_SLNK 0x00000040 /* SYM LINK (input) */
618#define GEP_SDET 0x00000020 /* Signal Detect (input) */
619#define GEP_HRST 0x00000010 /* Hard RESET (to PHY) (output) */
620#define GEP_FDXD 0x00000008 /* Full Duplex Disable (output) */
621#define GEP_PHYL 0x00000004 /* PHY Loopback (output) */
622#define GEP_FLED 0x00000002 /* Force Activity LED on (output) */
623#define GEP_MODE 0x00000001 /* 0: 10Mb/s, 1: 100Mb/s */
624#define GEP_INIT 0x0000011f /* Setup inputs (0) and outputs (1) */
625#define GEP_CTRL 0x00000100 /* GEP control bit */
626
627/*
628** SIA Register Defaults
629*/
630#define CSR13 0x00000001
631#define CSR14 0x0003ff7f /* Autonegotiation disabled */
632#define CSR15 0x00000008
633
634/*
635** SIA Status Register (DE4X5_SISR)
636*/
637#define SISR_LPC 0xffff0000 /* Link Partner's Code Word */
638#define SISR_LPN 0x00008000 /* Link Partner Negotiable */
639#define SISR_ANS 0x00007000 /* Auto Negotiation Arbitration State */
640#define SISR_NSN 0x00000800 /* Non Stable NLPs Detected (DC21041) */
641#define SISR_TRF 0x00000800 /* Transmit Remote Fault */
642#define SISR_NSND 0x00000400 /* Non Stable NLPs Detected (DC21142) */
643#define SISR_ANR_FDS 0x00000400 /* Auto Negotiate Restart/Full Duplex Sel.*/
644#define SISR_TRA 0x00000200 /* 10BASE-T Receive Port Activity */
645#define SISR_NRA 0x00000200 /* Non Selected Port Receive Activity */
646#define SISR_ARA 0x00000100 /* AUI Receive Port Activity */
647#define SISR_SRA 0x00000100 /* Selected Port Receive Activity */
648#define SISR_DAO 0x00000080 /* PLL All One */
649#define SISR_DAZ 0x00000040 /* PLL All Zero */
650#define SISR_DSP 0x00000020 /* PLL Self-Test Pass */
651#define SISR_DSD 0x00000010 /* PLL Self-Test Done */
652#define SISR_APS 0x00000008 /* Auto Polarity State */
653#define SISR_LKF 0x00000004 /* Link Fail Status */
654#define SISR_LS10 0x00000004 /* 10Mb/s Link Fail Status */
655#define SISR_NCR 0x00000002 /* Network Connection Error */
656#define SISR_LS100 0x00000002 /* 100Mb/s Link Fail Status */
657#define SISR_PAUI 0x00000001 /* AUI_TP Indication */
658#define SISR_MRA 0x00000001 /* MII Receive Port Activity */
659
660#define ANS_NDIS 0x00000000 /* Nway disable */
661#define ANS_TDIS 0x00001000 /* Transmit Disable */
662#define ANS_ADET 0x00002000 /* Ability Detect */
663#define ANS_ACK 0x00003000 /* Acknowledge */
664#define ANS_CACK 0x00004000 /* Complete Acknowledge */
665#define ANS_NWOK 0x00005000 /* Nway OK - FLP Link Good */
666#define ANS_LCHK 0x00006000 /* Link Check */
667
668#define SISR_RST 0x00000301 /* CSR12 reset */
669#define SISR_ANR 0x00001301 /* Autonegotiation restart */
670
671/*
672** SIA Connectivity Register (DE4X5_SICR)
673*/
674#define SICR_SDM 0xffff0000 /* SIA Diagnostics Mode */
675#define SICR_OE57 0x00008000 /* Output Enable 5 6 7 */
676#define SICR_OE24 0x00004000 /* Output Enable 2 4 */
677#define SICR_OE13 0x00002000 /* Output Enable 1 3 */
678#define SICR_IE 0x00001000 /* Input Enable */
679#define SICR_EXT 0x00000000 /* SIA MUX Select External SIA Mode */
680#define SICR_D_SIA 0x00000400 /* SIA MUX Select Diagnostics - SIA Sigs */
681#define SICR_DPLL 0x00000800 /* SIA MUX Select Diagnostics - DPLL Sigs*/
682#define SICR_APLL 0x00000a00 /* SIA MUX Select Diagnostics - DPLL Sigs*/
683#define SICR_D_RxM 0x00000c00 /* SIA MUX Select Diagnostics - RxM Sigs */
684#define SICR_M_RxM 0x00000d00 /* SIA MUX Select Diagnostics - RxM Sigs */
685#define SICR_LNKT 0x00000e00 /* SIA MUX Select Diagnostics - Link Test*/
686#define SICR_SEL 0x00000f00 /* SIA MUX Select AUI or TP with LEDs */
687#define SICR_ASE 0x00000080 /* APLL Start Enable*/
688#define SICR_SIM 0x00000040 /* Serial Interface Input Multiplexer */
689#define SICR_ENI 0x00000020 /* Encoder Input Multiplexer */
690#define SICR_EDP 0x00000010 /* SIA PLL External Input Enable */
691#define SICR_AUI 0x00000008 /* 10Base-T (0) or AUI (1) */
692#define SICR_CAC 0x00000004 /* CSR Auto Configuration */
693#define SICR_PS 0x00000002 /* Pin AUI/TP Selection */
694#define SICR_SRL 0x00000001 /* SIA Reset */
695#define SIA_RESET 0x00000000 /* SIA Reset Value */
696
697/*
698** SIA Transmit and Receive Register (DE4X5_STRR)
699*/
700#define STRR_TAS 0x00008000 /* 10Base-T/AUI Autosensing Enable */
701#define STRR_SPP 0x00004000 /* Set Polarity Plus */
702#define STRR_APE 0x00002000 /* Auto Polarity Enable */
703#define STRR_LTE 0x00001000 /* Link Test Enable */
704#define STRR_SQE 0x00000800 /* Signal Quality Enable */
705#define STRR_CLD 0x00000400 /* Collision Detect Enable */
706#define STRR_CSQ 0x00000200 /* Collision Squelch Enable */
707#define STRR_RSQ 0x00000100 /* Receive Squelch Enable */
708#define STRR_ANE 0x00000080 /* Auto Negotiate Enable */
709#define STRR_HDE 0x00000040 /* Half Duplex Enable */
710#define STRR_CPEN 0x00000030 /* Compensation Enable */
711#define STRR_LSE 0x00000008 /* Link Pulse Send Enable */
712#define STRR_DREN 0x00000004 /* Driver Enable */
713#define STRR_LBK 0x00000002 /* Loopback Enable */
714#define STRR_ECEN 0x00000001 /* Encoder Enable */
715#define STRR_RESET 0xffffffff /* Reset value for STRR */
716
717/*
718** SIA General Register (DE4X5_SIGR)
719*/
720#define SIGR_RMI 0x40000000 /* Receive Match Interrupt */
721#define SIGR_GI1 0x20000000 /* General Port Interrupt 1 */
722#define SIGR_GI0 0x10000000 /* General Port Interrupt 0 */
723#define SIGR_CWE 0x08000000 /* Control Write Enable */
724#define SIGR_RME 0x04000000 /* Receive Match Enable */
725#define SIGR_GEI1 0x02000000 /* GEP Interrupt Enable on Port 1 */
726#define SIGR_GEI0 0x01000000 /* GEP Interrupt Enable on Port 0 */
727#define SIGR_LGS3 0x00800000 /* LED/GEP3 Select */
728#define SIGR_LGS2 0x00400000 /* LED/GEP2 Select */
729#define SIGR_LGS1 0x00200000 /* LED/GEP1 Select */
730#define SIGR_LGS0 0x00100000 /* LED/GEP0 Select */
731#define SIGR_MD 0x000f0000 /* General Purpose Mode and Data */
732#define SIGR_LV2 0x00008000 /* General Purpose LED2 value */
733#define SIGR_LE2 0x00004000 /* General Purpose LED2 enable */
734#define SIGR_FRL 0x00002000 /* Force Receiver Low */
735#define SIGR_DPST 0x00001000 /* PLL Self Test Start */
736#define SIGR_LSD 0x00000800 /* LED Stretch Disable */
737#define SIGR_FLF 0x00000400 /* Force Link Fail */
738#define SIGR_FUSQ 0x00000200 /* Force Unsquelch */
739#define SIGR_TSCK 0x00000100 /* Test Clock */
740#define SIGR_LV1 0x00000080 /* General Purpose LED1 value */
741#define SIGR_LE1 0x00000040 /* General Purpose LED1 enable */
742#define SIGR_RWR 0x00000020 /* Receive Watchdog Release */
743#define SIGR_RWD 0x00000010 /* Receive Watchdog Disable */
744#define SIGR_ABM 0x00000008 /* BNC: 0, AUI:1 */
745#define SIGR_JCK 0x00000004 /* Jabber Clock */
746#define SIGR_HUJ 0x00000002 /* Host Unjab */
747#define SIGR_JBD 0x00000001 /* Jabber Disable */
748#define SIGR_RESET 0xffff0000 /* Reset value for SIGR */
749
750/*
751** Receive Descriptor Bit Summary
752*/
753#define R_OWN 0x80000000 /* Own Bit */
754#define RD_FF 0x40000000 /* Filtering Fail */
755#define RD_FL 0x3fff0000 /* Frame Length */
756#define RD_ES 0x00008000 /* Error Summary */
757#define RD_LE 0x00004000 /* Length Error */
758#define RD_DT 0x00003000 /* Data Type */
759#define RD_RF 0x00000800 /* Runt Frame */
760#define RD_MF 0x00000400 /* Multicast Frame */
761#define RD_FS 0x00000200 /* First Descriptor */
762#define RD_LS 0x00000100 /* Last Descriptor */
763#define RD_TL 0x00000080 /* Frame Too Long */
764#define RD_CS 0x00000040 /* Collision Seen */
765#define RD_FT 0x00000020 /* Frame Type */
766#define RD_RJ 0x00000010 /* Receive Watchdog */
767#define RD_RE 0x00000008 /* Report on MII Error */
768#define RD_DB 0x00000004 /* Dribbling Bit */
769#define RD_CE 0x00000002 /* CRC Error */
770#define RD_OF 0x00000001 /* Overflow */
771
772#define RD_RER 0x02000000 /* Receive End Of Ring */
773#define RD_RCH 0x01000000 /* Second Address Chained */
774#define RD_RBS2 0x003ff800 /* Buffer 2 Size */
775#define RD_RBS1 0x000007ff /* Buffer 1 Size */
776
777/*
778** Transmit Descriptor Bit Summary
779*/
780#define T_OWN 0x80000000 /* Own Bit */
781#define TD_ES 0x00008000 /* Error Summary */
782#define TD_TO 0x00004000 /* Transmit Jabber Time-Out */
783#define TD_LO 0x00000800 /* Loss Of Carrier */
784#define TD_NC 0x00000400 /* No Carrier */
785#define TD_LC 0x00000200 /* Late Collision */
786#define TD_EC 0x00000100 /* Excessive Collisions */
787#define TD_HF 0x00000080 /* Heartbeat Fail */
788#define TD_CC 0x00000078 /* Collision Counter */
789#define TD_LF 0x00000004 /* Link Fail */
790#define TD_UF 0x00000002 /* Underflow Error */
791#define TD_DE 0x00000001 /* Deferred */
792
793#define TD_IC 0x80000000 /* Interrupt On Completion */
794#define TD_LS 0x40000000 /* Last Segment */
795#define TD_FS 0x20000000 /* First Segment */
796#define TD_FT1 0x10000000 /* Filtering Type */
797#define TD_SET 0x08000000 /* Setup Packet */
798#define TD_AC 0x04000000 /* Add CRC Disable */
799#define TD_TER 0x02000000 /* Transmit End Of Ring */
800#define TD_TCH 0x01000000 /* Second Address Chained */
801#define TD_DPD 0x00800000 /* Disabled Padding */
802#define TD_FT0 0x00400000 /* Filtering Type */
803#define TD_TBS2 0x003ff800 /* Buffer 2 Size */
804#define TD_TBS1 0x000007ff /* Buffer 1 Size */
805
806#define PERFECT_F 0x00000000
807#define HASH_F TD_FT0
808#define INVERSE_F TD_FT1
809#define HASH_O_F (TD_FT1 | TD_F0)
810
811/*
812** Media / mode state machine definitions
813** User selectable:
814*/
815#define TP 0x0040 /* 10Base-T (now equiv to _10Mb) */
816#define TP_NW 0x0002 /* 10Base-T with Nway */
817#define BNC 0x0004 /* Thinwire */
818#define AUI 0x0008 /* Thickwire */
819#define BNC_AUI 0x0010 /* BNC/AUI on DC21040 indistinguishable */
820#define _10Mb 0x0040 /* 10Mb/s Ethernet */
821#define _100Mb 0x0080 /* 100Mb/s Ethernet */
822#define AUTO 0x4000 /* Auto sense the media or speed */
823
824/*
825** Internal states
826*/
827#define NC 0x0000 /* No Connection */
828#define ANS 0x0020 /* Intermediate AutoNegotiation State */
829#define SPD_DET 0x0100 /* Parallel speed detection */
830#define INIT 0x0200 /* Initial state */
831#define EXT_SIA 0x0400 /* External SIA for motherboard chip */
832#define ANS_SUSPECT 0x0802 /* Suspect the ANS (TP) port is down */
833#define TP_SUSPECT 0x0803 /* Suspect the TP port is down */
834#define BNC_AUI_SUSPECT 0x0804 /* Suspect the BNC or AUI port is down */
835#define EXT_SIA_SUSPECT 0x0805 /* Suspect the EXT SIA port is down */
836#define BNC_SUSPECT 0x0806 /* Suspect the BNC port is down */
837#define AUI_SUSPECT 0x0807 /* Suspect the AUI port is down */
838#define MII 0x1000 /* MII on the 21143 */
839
840#define TIMER_CB 0x80000000 /* Timer callback detection */
841
842/*
843** DE4X5 DEBUG Options
844*/
845#define DEBUG_NONE 0x0000 /* No DEBUG messages */
846#define DEBUG_VERSION 0x0001 /* Print version message */
847#define DEBUG_MEDIA 0x0002 /* Print media messages */
848#define DEBUG_TX 0x0004 /* Print TX (queue_pkt) messages */
849#define DEBUG_RX 0x0008 /* Print RX (de4x5_rx) messages */
850#define DEBUG_SROM 0x0010 /* Print SROM messages */
851#define DEBUG_MII 0x0020 /* Print MII messages */
852#define DEBUG_OPEN 0x0040 /* Print de4x5_open() messages */
853#define DEBUG_CLOSE 0x0080 /* Print de4x5_close() messages */
854#define DEBUG_PCICFG 0x0100
855#define DEBUG_ALL 0x01ff
856
857/*
858** Miscellaneous
859*/
860#define PCI 0
861#define EISA 1
862
863#define HASH_TABLE_LEN 512 /* Bits */
864#define HASH_BITS 0x01ff /* 9 LS bits */
865
866#define SETUP_FRAME_LEN 192 /* Bytes */
867#define IMPERF_PA_OFFSET 156 /* Bytes */
868
869#define POLL_DEMAND 1
870
871#define LOST_MEDIA_THRESHOLD 3
872
873#define MASK_INTERRUPTS 1
874#define UNMASK_INTERRUPTS 0
875
876#define DE4X5_STRLEN 8
877
878#define DE4X5_INIT 0 /* Initialisation time */
879#define DE4X5_RUN 1 /* Run time */
880
881#define DE4X5_SAVE_STATE 0
882#define DE4X5_RESTORE_STATE 1
883
884/*
885** Address Filtering Modes
886*/
887#define PERFECT 0 /* 16 perfect physical addresses */
888#define HASH_PERF 1 /* 1 perfect, 512 multicast addresses */
889#define PERFECT_REJ 2 /* Reject 16 perfect physical addresses */
890#define ALL_HASH 3 /* Hashes all physical & multicast addrs */
891
892#define ALL 0 /* Clear out all the setup frame */
893#define PHYS_ADDR_ONLY 1 /* Update the physical address only */
894
895/*
896** Booleans
897*/
898#define NO 0
899#define FALSE 0
900
901#define YES ~0
902#define TRUE ~0
903
904/*
905** Adapter state
906*/
907#define INITIALISED 0 /* After h/w initialised and mem alloc'd */
908#define CLOSED 1 /* Ready for opening */
909#define OPEN 2 /* Running */
910
911/*
912** Various wait times
913*/
914#define PDET_LINK_WAIT 1200 /* msecs to wait for link detect bits */
915#define ANS_FINISH_WAIT 1000 /* msecs to wait for link detect bits */
916
917/*
918** IEEE OUIs for various PHY vendor/chip combos - Reg 2 values only. Since
919** the vendors seem split 50-50 on how to calculate the OUI register values
920** anyway, just reading Reg2 seems reasonable for now [see de4x5_get_oui()].
921*/
922#define NATIONAL_TX 0x2000
923#define BROADCOM_T4 0x03e0
924#define SEEQ_T4 0x0016
925#define CYPRESS_T4 0x0014
926
927/*
928** Speed Selection stuff
929*/
930#define SET_10Mb {\
931 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
932 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\
933 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
934 mii_wr(MII_CR_10|(lp->fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
935 }\
936 omr |= ((lp->fdx ? OMR_FDX : 0) | OMR_TTM);\
937 outl(omr, DE4X5_OMR);\
938 if (!lp->useSROM) lp->cache.gep = 0;\
939 } else if (lp->useSROM && !lp->useMII) {\
940 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
941 omr |= (lp->fdx ? OMR_FDX : 0);\
942 outl(omr | (lp->infoblock_csr6 & ~(OMR_SCR | OMR_HBD)), DE4X5_OMR);\
943 } else {\
944 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
945 omr |= (lp->fdx ? OMR_FDX : 0);\
946 outl(omr | OMR_SDP | OMR_TTM, DE4X5_OMR);\
947 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD);\
948 gep_wr(lp->cache.gep, dev);\
949 }\
950}
951
952#define SET_100Mb {\
953 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
954 int fdx=0;\
955 if (lp->phy[lp->active].id == NATIONAL_TX) {\
956 mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
957 0x18, lp->phy[lp->active].addr, DE4X5_MII);\
958 }\
959 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\
960 sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\
961 if (!(sr & MII_ANA_T4AM) && lp->fdx) fdx=1;\
962 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
963 mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
964 }\
965 if (fdx) omr |= OMR_FDX;\
966 outl(omr, DE4X5_OMR);\
967 if (!lp->useSROM) lp->cache.gep = 0;\
968 } else if (lp->useSROM && !lp->useMII) {\
969 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
970 omr |= (lp->fdx ? OMR_FDX : 0);\
971 outl(omr | lp->infoblock_csr6, DE4X5_OMR);\
972 } else {\
973 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
974 omr |= (lp->fdx ? OMR_FDX : 0);\
975 outl(omr | OMR_SDP | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);\
976 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD) | GEP_MODE;\
977 gep_wr(lp->cache.gep, dev);\
978 }\
979}
980
981/* FIX ME so I don't jam 10Mb networks */
982#define SET_100Mb_PDET {\
983 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
984 mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
985 omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
986 outl(omr, DE4X5_OMR);\
987 } else if (lp->useSROM && !lp->useMII) {\
988 omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
989 outl(omr, DE4X5_OMR);\
990 } else {\
991 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
992 outl(omr | OMR_SDP | OMR_PS | OMR_HBD | OMR_PCS, DE4X5_OMR);\
993 lp->cache.gep = (GEP_FDXD | GEP_MODE);\
994 gep_wr(lp->cache.gep, dev);\
995 }\
996}
997
998/*
999** Include the IOCTL stuff
1000*/
1001#include <linux/sockios.h>
1002
1003#define DE4X5IOCTL SIOCDEVPRIVATE
1004
1005struct de4x5_ioctl {
1006 unsigned short cmd; /* Command to run */
1007 unsigned short len; /* Length of the data buffer */
1008 unsigned char __user *data; /* Pointer to the data buffer */
1009};
1010
1011/*
1012** Recognised commands for the driver
1013*/
1014#define DE4X5_GET_HWADDR 0x01 /* Get the hardware address */
1015#define DE4X5_SET_HWADDR 0x02 /* Set the hardware address */
1016#define DE4X5_SET_PROM 0x03 /* Set Promiscuous Mode */
1017#define DE4X5_CLR_PROM 0x04 /* Clear Promiscuous Mode */
1018#define DE4X5_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */
1019#define DE4X5_GET_MCA 0x06 /* Get a multicast address */
1020#define DE4X5_SET_MCA 0x07 /* Set a multicast address */
1021#define DE4X5_CLR_MCA 0x08 /* Clear a multicast address */
1022#define DE4X5_MCA_EN 0x09 /* Enable a multicast address group */
1023#define DE4X5_GET_STATS 0x0a /* Get the driver statistics */
1024#define DE4X5_CLR_STATS 0x0b /* Zero out the driver statistics */
1025#define DE4X5_GET_OMR 0x0c /* Get the OMR Register contents */
1026#define DE4X5_SET_OMR 0x0d /* Set the OMR Register contents */
1027#define DE4X5_GET_REG 0x0e /* Get the DE4X5 Registers */
1028
1029#define MOTO_SROM_BUG ((lp->active == 8) && (((le32_to_cpu(get_unaligned(((s32 *)dev->dev_addr))))&0x00ffffff)==0x3e0008))
diff --git a/drivers/net/tulip/dmfe.c b/drivers/net/tulip/dmfe.c
new file mode 100644
index 000000000000..e25f33df223e
--- /dev/null
+++ b/drivers/net/tulip/dmfe.c
@@ -0,0 +1,2066 @@
1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65*/
66
67#define DRV_NAME "dmfe"
68#define DRV_VERSION "1.36.4"
69#define DRV_RELDATE "2002-01-17"
70
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/ptrace.h>
76#include <linux/errno.h>
77#include <linux/ioport.h>
78#include <linux/slab.h>
79#include <linux/interrupt.h>
80#include <linux/pci.h>
81#include <linux/init.h>
82#include <linux/netdevice.h>
83#include <linux/etherdevice.h>
84#include <linux/ethtool.h>
85#include <linux/skbuff.h>
86#include <linux/delay.h>
87#include <linux/spinlock.h>
88#include <linux/crc32.h>
89#include <linux/bitops.h>
90
91#include <asm/processor.h>
92#include <asm/io.h>
93#include <asm/dma.h>
94#include <asm/uaccess.h>
95#include <asm/irq.h>
96
97
98/* Board/System/Debug information/definition ---------------- */
99#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
100#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
101#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
102#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
103
104#define DM9102_IO_SIZE 0x80
105#define DM9102A_IO_SIZE 0x100
106#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
107#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
108#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
109#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
110#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
111#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
112#define TX_BUF_ALLOC 0x600
113#define RX_ALLOC_SIZE 0x620
114#define DM910X_RESET 1
115#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
116#define CR6_DEFAULT 0x00080000 /* HD */
117#define CR7_DEFAULT 0x180c1
118#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
119#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
120#define MAX_PACKET_SIZE 1514
121#define DMFE_MAX_MULTICAST 14
122#define RX_COPY_SIZE 100
123#define MAX_CHECK_PACKET 0x8000
124#define DM9801_NOISE_FLOOR 8
125#define DM9802_NOISE_FLOOR 5
126
127#define DMFE_10MHF 0
128#define DMFE_100MHF 1
129#define DMFE_10MFD 4
130#define DMFE_100MFD 5
131#define DMFE_AUTO 8
132#define DMFE_1M_HPNA 0x10
133
134#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
135#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
136#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
137#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
138#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
139#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
140
141#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
142#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
143#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
144
145#define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
146
147#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
148
149
150/* CR9 definition: SROM/MII */
151#define CR9_SROM_READ 0x4800
152#define CR9_SRCS 0x1
153#define CR9_SRCLK 0x2
154#define CR9_CRDOUT 0x8
155#define SROM_DATA_0 0x0
156#define SROM_DATA_1 0x4
157#define PHY_DATA_1 0x20000
158#define PHY_DATA_0 0x00000
159#define MDCLKH 0x10000
160
161#define PHY_POWER_DOWN 0x800
162
163#define SROM_V41_CODE 0x14
164
165#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
166
167#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
168#define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
169
170/* Sten Check */
171#define DEVICE net_device
172
173/* Structure/enum declaration ------------------------------- */
174struct tx_desc {
175 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
176 char *tx_buf_ptr; /* Data for us */
177 struct tx_desc *next_tx_desc;
178} __attribute__(( aligned(32) ));
179
180struct rx_desc {
181 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
182 struct sk_buff *rx_skb_ptr; /* Data for us */
183 struct rx_desc *next_rx_desc;
184} __attribute__(( aligned(32) ));
185
186struct dmfe_board_info {
187 u32 chip_id; /* Chip vendor/Device ID */
188 u32 chip_revision; /* Chip revision */
189 struct DEVICE *next_dev; /* next device */
190 struct pci_dev *pdev; /* PCI device */
191 spinlock_t lock;
192
193 long ioaddr; /* I/O base address */
194 u32 cr0_data;
195 u32 cr5_data;
196 u32 cr6_data;
197 u32 cr7_data;
198 u32 cr15_data;
199
200 /* pointer for memory physical address */
201 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
202 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
203 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
204 dma_addr_t first_tx_desc_dma;
205 dma_addr_t first_rx_desc_dma;
206
207 /* descriptor pointer */
208 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
209 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
210 unsigned char *desc_pool_ptr; /* descriptor pool memory */
211 struct tx_desc *first_tx_desc;
212 struct tx_desc *tx_insert_ptr;
213 struct tx_desc *tx_remove_ptr;
214 struct rx_desc *first_rx_desc;
215 struct rx_desc *rx_insert_ptr;
216 struct rx_desc *rx_ready_ptr; /* packet come pointer */
217 unsigned long tx_packet_cnt; /* transmitted packet count */
218 unsigned long tx_queue_cnt; /* wait to send packet count */
219 unsigned long rx_avail_cnt; /* available rx descriptor count */
220 unsigned long interval_rx_cnt; /* rx packet count a callback time */
221
222 u16 HPNA_command; /* For HPNA register 16 */
223 u16 HPNA_timer; /* For HPNA remote device check */
224 u16 dbug_cnt;
225 u16 NIC_capability; /* NIC media capability */
226 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
227
228 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
229 u8 chip_type; /* Keep DM9102A chip type */
230 u8 media_mode; /* user specify media mode */
231 u8 op_mode; /* real work media mode */
232 u8 phy_addr;
233 u8 link_failed; /* Ever link failed */
234 u8 wait_reset; /* Hardware failed, need to reset */
235 u8 dm910x_chk_mode; /* Operating mode check */
236 u8 first_in_callback; /* Flag to record state */
237 struct timer_list timer;
238
239 /* System defined statistic counter */
240 struct net_device_stats stats;
241
242 /* Driver defined statistic counter */
243 unsigned long tx_fifo_underrun;
244 unsigned long tx_loss_carrier;
245 unsigned long tx_no_carrier;
246 unsigned long tx_late_collision;
247 unsigned long tx_excessive_collision;
248 unsigned long tx_jabber_timeout;
249 unsigned long reset_count;
250 unsigned long reset_cr8;
251 unsigned long reset_fatal;
252 unsigned long reset_TXtimeout;
253
254 /* NIC SROM data */
255 unsigned char srom[128];
256};
257
258enum dmfe_offsets {
259 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
260 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
261 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
262 DCR15 = 0x78
263};
264
265enum dmfe_CR6_bits {
266 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
267 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
268 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
269};
270
271/* Global variable declaration ----------------------------- */
272static int __devinitdata printed_version;
273static char version[] __devinitdata =
274 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
275 DRV_VERSION " (" DRV_RELDATE ")\n";
276
277static int dmfe_debug;
278static unsigned char dmfe_media_mode = DMFE_AUTO;
279static u32 dmfe_cr6_user_set;
280
281/* For module input parameter */
282static int debug;
283static u32 cr6set;
284static unsigned char mode = 8;
285static u8 chkmode = 1;
286static u8 HPNA_mode; /* Default: Low Power/High Speed */
287static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
288static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
289static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
290static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
291 4: TX pause packet */
292
293
294/* function declaration ------------------------------------- */
295static int dmfe_open(struct DEVICE *);
296static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
297static int dmfe_stop(struct DEVICE *);
298static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
299static void dmfe_set_filter_mode(struct DEVICE *);
300static struct ethtool_ops netdev_ethtool_ops;
301static u16 read_srom_word(long ,int);
302static irqreturn_t dmfe_interrupt(int , void *, struct pt_regs *);
303#ifdef CONFIG_NET_POLL_CONTROLLER
304static void poll_dmfe (struct net_device *dev);
305#endif
306static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
307static void allocate_rx_buffer(struct dmfe_board_info *);
308static void update_cr6(u32, unsigned long);
309static void send_filter_frame(struct DEVICE * ,int);
310static void dm9132_id_table(struct DEVICE * ,int);
311static u16 phy_read(unsigned long, u8, u8, u32);
312static void phy_write(unsigned long, u8, u8, u16, u32);
313static void phy_write_1bit(unsigned long, u32);
314static u16 phy_read_1bit(unsigned long);
315static u8 dmfe_sense_speed(struct dmfe_board_info *);
316static void dmfe_process_mode(struct dmfe_board_info *);
317static void dmfe_timer(unsigned long);
318static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
319static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
320static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
321static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
322static void dmfe_dynamic_reset(struct DEVICE *);
323static void dmfe_free_rxbuffer(struct dmfe_board_info *);
324static void dmfe_init_dm910x(struct DEVICE *);
325static void dmfe_parse_srom(struct dmfe_board_info *);
326static void dmfe_program_DM9801(struct dmfe_board_info *, int);
327static void dmfe_program_DM9802(struct dmfe_board_info *);
328static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
329static void dmfe_set_phyxcer(struct dmfe_board_info *);
330
331/* DM910X network baord routine ---------------------------- */
332
333/*
334 * Search DM910X board ,allocate space and register it
335 */
336
337static int __devinit dmfe_init_one (struct pci_dev *pdev,
338 const struct pci_device_id *ent)
339{
340 struct dmfe_board_info *db; /* board information structure */
341 struct net_device *dev;
342 u32 dev_rev, pci_pmr;
343 int i, err;
344
345 DMFE_DBUG(0, "dmfe_init_one()", 0);
346
347 if (!printed_version++)
348 printk(version);
349
350 /* Init network device */
351 dev = alloc_etherdev(sizeof(*db));
352 if (dev == NULL)
353 return -ENOMEM;
354 SET_MODULE_OWNER(dev);
355 SET_NETDEV_DEV(dev, &pdev->dev);
356
357 if (pci_set_dma_mask(pdev, 0xffffffff)) {
358 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
359 err = -ENODEV;
360 goto err_out_free;
361 }
362
363 /* Enable Master/IO access, Disable memory access */
364 err = pci_enable_device(pdev);
365 if (err)
366 goto err_out_free;
367
368 if (!pci_resource_start(pdev, 0)) {
369 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
370 err = -ENODEV;
371 goto err_out_disable;
372 }
373
374 /* Read Chip revision */
375 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
376
377 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
378 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
379 err = -ENODEV;
380 goto err_out_disable;
381 }
382
383#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
384
385 /* Set Latency Timer 80h */
386 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
387 Need a PCI quirk.. */
388
389 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
390#endif
391
392 if (pci_request_regions(pdev, DRV_NAME)) {
393 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
394 err = -ENODEV;
395 goto err_out_disable;
396 }
397
398 /* Init system & device */
399 db = netdev_priv(dev);
400
401 /* Allocate Tx/Rx descriptor memory */
402 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
403 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
404
405 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
406 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
407 db->buf_pool_start = db->buf_pool_ptr;
408 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
409
410 db->chip_id = ent->driver_data;
411 db->ioaddr = pci_resource_start(pdev, 0);
412 db->chip_revision = dev_rev;
413
414 db->pdev = pdev;
415
416 dev->base_addr = db->ioaddr;
417 dev->irq = pdev->irq;
418 pci_set_drvdata(pdev, dev);
419 dev->open = &dmfe_open;
420 dev->hard_start_xmit = &dmfe_start_xmit;
421 dev->stop = &dmfe_stop;
422 dev->get_stats = &dmfe_get_stats;
423 dev->set_multicast_list = &dmfe_set_filter_mode;
424#ifdef CONFIG_NET_POLL_CONTROLLER
425 dev->poll_controller = &poll_dmfe;
426#endif
427 dev->ethtool_ops = &netdev_ethtool_ops;
428 spin_lock_init(&db->lock);
429
430 pci_read_config_dword(pdev, 0x50, &pci_pmr);
431 pci_pmr &= 0x70000;
432 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
433 db->chip_type = 1; /* DM9102A E3 */
434 else
435 db->chip_type = 0;
436
437 /* read 64 word srom data */
438 for (i = 0; i < 64; i++)
439 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
440
441 /* Set Node address */
442 for (i = 0; i < 6; i++)
443 dev->dev_addr[i] = db->srom[20 + i];
444
445 err = register_netdev (dev);
446 if (err)
447 goto err_out_res;
448
449 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
450 dev->name,
451 ent->driver_data >> 16,
452 pci_name(pdev));
453 for (i = 0; i < 6; i++)
454 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
455 printk(", irq %d.\n", dev->irq);
456
457 pci_set_master(pdev);
458
459 return 0;
460
461err_out_res:
462 pci_release_regions(pdev);
463err_out_disable:
464 pci_disable_device(pdev);
465err_out_free:
466 pci_set_drvdata(pdev, NULL);
467 free_netdev(dev);
468
469 return err;
470}
471
472
473static void __devexit dmfe_remove_one (struct pci_dev *pdev)
474{
475 struct net_device *dev = pci_get_drvdata(pdev);
476 struct dmfe_board_info *db = netdev_priv(dev);
477
478 DMFE_DBUG(0, "dmfe_remove_one()", 0);
479
480 if (dev) {
481 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
482 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
483 db->desc_pool_dma_ptr);
484 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
485 db->buf_pool_ptr, db->buf_pool_dma_ptr);
486 unregister_netdev(dev);
487 pci_release_regions(pdev);
488 free_netdev(dev); /* free board information */
489 pci_set_drvdata(pdev, NULL);
490 }
491
492 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
493}
494
495
496/*
497 * Open the interface.
498 * The interface is opened whenever "ifconfig" actives it.
499 */
500
501static int dmfe_open(struct DEVICE *dev)
502{
503 int ret;
504 struct dmfe_board_info *db = netdev_priv(dev);
505
506 DMFE_DBUG(0, "dmfe_open", 0);
507
508 ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
509 if (ret)
510 return ret;
511
512 /* system variable init */
513 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
514 db->tx_packet_cnt = 0;
515 db->tx_queue_cnt = 0;
516 db->rx_avail_cnt = 0;
517 db->link_failed = 1;
518 db->wait_reset = 0;
519
520 db->first_in_callback = 0;
521 db->NIC_capability = 0xf; /* All capability*/
522 db->PHY_reg4 = 0x1e0;
523
524 /* CR6 operation mode decision */
525 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
526 (db->chip_revision >= 0x02000030) ) {
527 db->cr6_data |= DMFE_TXTH_256;
528 db->cr0_data = CR0_DEFAULT;
529 db->dm910x_chk_mode=4; /* Enter the normal mode */
530 } else {
531 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
532 db->cr0_data = 0;
533 db->dm910x_chk_mode = 1; /* Enter the check mode */
534 }
535
536 /* Initilize DM910X board */
537 dmfe_init_dm910x(dev);
538
539 /* Active System Interface */
540 netif_wake_queue(dev);
541
542 /* set and active a timer process */
543 init_timer(&db->timer);
544 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
545 db->timer.data = (unsigned long)dev;
546 db->timer.function = &dmfe_timer;
547 add_timer(&db->timer);
548
549 return 0;
550}
551
552
553/* Initilize DM910X board
554 * Reset DM910X board
555 * Initilize TX/Rx descriptor chain structure
556 * Send the set-up frame
557 * Enable Tx/Rx machine
558 */
559
560static void dmfe_init_dm910x(struct DEVICE *dev)
561{
562 struct dmfe_board_info *db = netdev_priv(dev);
563 unsigned long ioaddr = db->ioaddr;
564
565 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
566
567 /* Reset DM910x MAC controller */
568 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
569 udelay(100);
570 outl(db->cr0_data, ioaddr + DCR0);
571 udelay(5);
572
573 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
574 db->phy_addr = 1;
575
576 /* Parser SROM and media mode */
577 dmfe_parse_srom(db);
578 db->media_mode = dmfe_media_mode;
579
580 /* RESET Phyxcer Chip by GPR port bit 7 */
581 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
582 if (db->chip_id == PCI_DM9009_ID) {
583 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
584 mdelay(300); /* Delay 300 ms */
585 }
586 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
587
588 /* Process Phyxcer Media Mode */
589 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
590 dmfe_set_phyxcer(db);
591
592 /* Media Mode Process */
593 if ( !(db->media_mode & DMFE_AUTO) )
594 db->op_mode = db->media_mode; /* Force Mode */
595
596 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
597 dmfe_descriptor_init(db, ioaddr);
598
599 /* Init CR6 to program DM910x operation */
600 update_cr6(db->cr6_data, ioaddr);
601
602 /* Send setup frame */
603 if (db->chip_id == PCI_DM9132_ID)
604 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
605 else
606 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
607
608 /* Init CR7, interrupt active bit */
609 db->cr7_data = CR7_DEFAULT;
610 outl(db->cr7_data, ioaddr + DCR7);
611
612 /* Init CR15, Tx jabber and Rx watchdog timer */
613 outl(db->cr15_data, ioaddr + DCR15);
614
615 /* Enable DM910X Tx/Rx function */
616 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
617 update_cr6(db->cr6_data, ioaddr);
618}
619
620
621/*
622 * Hardware start transmission.
623 * Send a packet to media from the upper layer.
624 */
625
626static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
627{
628 struct dmfe_board_info *db = netdev_priv(dev);
629 struct tx_desc *txptr;
630 unsigned long flags;
631
632 DMFE_DBUG(0, "dmfe_start_xmit", 0);
633
634 /* Resource flag check */
635 netif_stop_queue(dev);
636
637 /* Too large packet check */
638 if (skb->len > MAX_PACKET_SIZE) {
639 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
640 dev_kfree_skb(skb);
641 return 0;
642 }
643
644 spin_lock_irqsave(&db->lock, flags);
645
646 /* No Tx resource check, it never happen nromally */
647 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
648 spin_unlock_irqrestore(&db->lock, flags);
649 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
650 return 1;
651 }
652
653 /* Disable NIC interrupt */
654 outl(0, dev->base_addr + DCR7);
655
656 /* transmit this packet */
657 txptr = db->tx_insert_ptr;
658 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
659 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
660
661 /* Point to next transmit free descriptor */
662 db->tx_insert_ptr = txptr->next_tx_desc;
663
664 /* Transmit Packet Process */
665 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
666 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
667 db->tx_packet_cnt++; /* Ready to send */
668 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
669 dev->trans_start = jiffies; /* saved time stamp */
670 } else {
671 db->tx_queue_cnt++; /* queue TX packet */
672 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
673 }
674
675 /* Tx resource check */
676 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
677 netif_wake_queue(dev);
678
679 /* Restore CR7 to enable interrupt */
680 spin_unlock_irqrestore(&db->lock, flags);
681 outl(db->cr7_data, dev->base_addr + DCR7);
682
683 /* free this SKB */
684 dev_kfree_skb(skb);
685
686 return 0;
687}
688
689
690/*
691 * Stop the interface.
692 * The interface is stopped when it is brought.
693 */
694
695static int dmfe_stop(struct DEVICE *dev)
696{
697 struct dmfe_board_info *db = netdev_priv(dev);
698 unsigned long ioaddr = dev->base_addr;
699
700 DMFE_DBUG(0, "dmfe_stop", 0);
701
702 /* disable system */
703 netif_stop_queue(dev);
704
705 /* deleted timer */
706 del_timer_sync(&db->timer);
707
708 /* Reset & stop DM910X board */
709 outl(DM910X_RESET, ioaddr + DCR0);
710 udelay(5);
711 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
712
713 /* free interrupt */
714 free_irq(dev->irq, dev);
715
716 /* free allocated rx buffer */
717 dmfe_free_rxbuffer(db);
718
719#if 0
720 /* show statistic counter */
721 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
722 db->tx_fifo_underrun, db->tx_excessive_collision,
723 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
724 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
725 db->reset_fatal, db->reset_TXtimeout);
726#endif
727
728 return 0;
729}
730
731
732/*
733 * DM9102 insterrupt handler
734 * receive the packet to upper layer, free the transmitted packet
735 */
736
737static irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
738{
739 struct DEVICE *dev = dev_id;
740 struct dmfe_board_info *db = netdev_priv(dev);
741 unsigned long ioaddr = dev->base_addr;
742 unsigned long flags;
743
744 DMFE_DBUG(0, "dmfe_interrupt()", 0);
745
746 if (!dev) {
747 DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0);
748 return IRQ_NONE;
749 }
750
751 spin_lock_irqsave(&db->lock, flags);
752
753 /* Got DM910X status */
754 db->cr5_data = inl(ioaddr + DCR5);
755 outl(db->cr5_data, ioaddr + DCR5);
756 if ( !(db->cr5_data & 0xc1) ) {
757 spin_unlock_irqrestore(&db->lock, flags);
758 return IRQ_HANDLED;
759 }
760
761 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
762 outl(0, ioaddr + DCR7);
763
764 /* Check system status */
765 if (db->cr5_data & 0x2000) {
766 /* system bus error happen */
767 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
768 db->reset_fatal++;
769 db->wait_reset = 1; /* Need to RESET */
770 spin_unlock_irqrestore(&db->lock, flags);
771 return IRQ_HANDLED;
772 }
773
774 /* Received the coming packet */
775 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
776 dmfe_rx_packet(dev, db);
777
778 /* reallocate rx descriptor buffer */
779 if (db->rx_avail_cnt<RX_DESC_CNT)
780 allocate_rx_buffer(db);
781
782 /* Free the transmitted descriptor */
783 if ( db->cr5_data & 0x01)
784 dmfe_free_tx_pkt(dev, db);
785
786 /* Mode Check */
787 if (db->dm910x_chk_mode & 0x2) {
788 db->dm910x_chk_mode = 0x4;
789 db->cr6_data |= 0x100;
790 update_cr6(db->cr6_data, db->ioaddr);
791 }
792
793 /* Restore CR7 to enable interrupt mask */
794 outl(db->cr7_data, ioaddr + DCR7);
795
796 spin_unlock_irqrestore(&db->lock, flags);
797 return IRQ_HANDLED;
798}
799
800
801#ifdef CONFIG_NET_POLL_CONTROLLER
802/*
803 * Polling 'interrupt' - used by things like netconsole to send skbs
804 * without having to re-enable interrupts. It's not called while
805 * the interrupt routine is executing.
806 */
807
808static void poll_dmfe (struct net_device *dev)
809{
810 /* disable_irq here is not very nice, but with the lockless
811 interrupt handler we have no other choice. */
812 disable_irq(dev->irq);
813 dmfe_interrupt (dev->irq, dev, NULL);
814 enable_irq(dev->irq);
815}
816#endif
817
818/*
819 * Free TX resource after TX complete
820 */
821
822static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
823{
824 struct tx_desc *txptr;
825 unsigned long ioaddr = dev->base_addr;
826 u32 tdes0;
827
828 txptr = db->tx_remove_ptr;
829 while(db->tx_packet_cnt) {
830 tdes0 = le32_to_cpu(txptr->tdes0);
831 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
832 if (tdes0 & 0x80000000)
833 break;
834
835 /* A packet sent completed */
836 db->tx_packet_cnt--;
837 db->stats.tx_packets++;
838
839 /* Transmit statistic counter */
840 if ( tdes0 != 0x7fffffff ) {
841 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
842 db->stats.collisions += (tdes0 >> 3) & 0xf;
843 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
844 if (tdes0 & TDES0_ERR_MASK) {
845 db->stats.tx_errors++;
846
847 if (tdes0 & 0x0002) { /* UnderRun */
848 db->tx_fifo_underrun++;
849 if ( !(db->cr6_data & CR6_SFT) ) {
850 db->cr6_data = db->cr6_data | CR6_SFT;
851 update_cr6(db->cr6_data, db->ioaddr);
852 }
853 }
854 if (tdes0 & 0x0100)
855 db->tx_excessive_collision++;
856 if (tdes0 & 0x0200)
857 db->tx_late_collision++;
858 if (tdes0 & 0x0400)
859 db->tx_no_carrier++;
860 if (tdes0 & 0x0800)
861 db->tx_loss_carrier++;
862 if (tdes0 & 0x4000)
863 db->tx_jabber_timeout++;
864 }
865 }
866
867 txptr = txptr->next_tx_desc;
868 }/* End of while */
869
870 /* Update TX remove pointer to next */
871 db->tx_remove_ptr = txptr;
872
873 /* Send the Tx packet in queue */
874 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
875 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
876 db->tx_packet_cnt++; /* Ready to send */
877 db->tx_queue_cnt--;
878 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
879 dev->trans_start = jiffies; /* saved time stamp */
880 }
881
882 /* Resource available check */
883 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
884 netif_wake_queue(dev); /* Active upper layer, send again */
885}
886
887
888/*
889 * Calculate the CRC valude of the Rx packet
890 * flag = 1 : return the reverse CRC (for the received packet CRC)
891 * 0 : return the normal CRC (for Hash Table index)
892 */
893
894static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
895{
896 u32 crc = crc32(~0, Data, Len);
897 if (flag) crc = ~crc;
898 return crc;
899}
900
901
902/*
903 * Receive the come packet and pass to upper layer
904 */
905
906static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
907{
908 struct rx_desc *rxptr;
909 struct sk_buff *skb;
910 int rxlen;
911 u32 rdes0;
912
913 rxptr = db->rx_ready_ptr;
914
915 while(db->rx_avail_cnt) {
916 rdes0 = le32_to_cpu(rxptr->rdes0);
917 if (rdes0 & 0x80000000) /* packet owner check */
918 break;
919
920 db->rx_avail_cnt--;
921 db->interval_rx_cnt++;
922
923 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
924 if ( (rdes0 & 0x300) != 0x300) {
925 /* A packet without First/Last flag */
926 /* reuse this SKB */
927 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
928 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
929 } else {
930 /* A packet with First/Last flag */
931 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
932
933 /* error summary bit check */
934 if (rdes0 & 0x8000) {
935 /* This is a error packet */
936 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
937 db->stats.rx_errors++;
938 if (rdes0 & 1)
939 db->stats.rx_fifo_errors++;
940 if (rdes0 & 2)
941 db->stats.rx_crc_errors++;
942 if (rdes0 & 0x80)
943 db->stats.rx_length_errors++;
944 }
945
946 if ( !(rdes0 & 0x8000) ||
947 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
948 skb = rxptr->rx_skb_ptr;
949
950 /* Received Packet CRC check need or not */
951 if ( (db->dm910x_chk_mode & 1) &&
952 (cal_CRC(skb->tail, rxlen, 1) !=
953 (*(u32 *) (skb->tail+rxlen) ))) { /* FIXME (?) */
954 /* Found a error received packet */
955 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
956 db->dm910x_chk_mode = 3;
957 } else {
958 /* Good packet, send to upper layer */
959 /* Shorst packet used new SKB */
960 if ( (rxlen < RX_COPY_SIZE) &&
961 ( (skb = dev_alloc_skb(rxlen + 2) )
962 != NULL) ) {
963 /* size less than COPY_SIZE, allocate a rxlen SKB */
964 skb->dev = dev;
965 skb_reserve(skb, 2); /* 16byte align */
966 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen);
967 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
968 } else {
969 skb->dev = dev;
970 skb_put(skb, rxlen);
971 }
972 skb->protocol = eth_type_trans(skb, dev);
973 netif_rx(skb);
974 dev->last_rx = jiffies;
975 db->stats.rx_packets++;
976 db->stats.rx_bytes += rxlen;
977 }
978 } else {
979 /* Reuse SKB buffer when the packet is error */
980 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
981 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
982 }
983 }
984
985 rxptr = rxptr->next_rx_desc;
986 }
987
988 db->rx_ready_ptr = rxptr;
989}
990
991
992/*
993 * Get statistics from driver.
994 */
995
996static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
997{
998 struct dmfe_board_info *db = netdev_priv(dev);
999
1000 DMFE_DBUG(0, "dmfe_get_stats", 0);
1001 return &db->stats;
1002}
1003
1004
1005/*
1006 * Set DM910X multicast address
1007 */
1008
1009static void dmfe_set_filter_mode(struct DEVICE * dev)
1010{
1011 struct dmfe_board_info *db = netdev_priv(dev);
1012 unsigned long flags;
1013
1014 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1015 spin_lock_irqsave(&db->lock, flags);
1016
1017 if (dev->flags & IFF_PROMISC) {
1018 DMFE_DBUG(0, "Enable PROM Mode", 0);
1019 db->cr6_data |= CR6_PM | CR6_PBF;
1020 update_cr6(db->cr6_data, db->ioaddr);
1021 spin_unlock_irqrestore(&db->lock, flags);
1022 return;
1023 }
1024
1025 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1026 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1027 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1028 db->cr6_data |= CR6_PAM;
1029 spin_unlock_irqrestore(&db->lock, flags);
1030 return;
1031 }
1032
1033 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1034 if (db->chip_id == PCI_DM9132_ID)
1035 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1036 else
1037 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1038 spin_unlock_irqrestore(&db->lock, flags);
1039}
1040
1041static void netdev_get_drvinfo(struct net_device *dev,
1042 struct ethtool_drvinfo *info)
1043{
1044 struct dmfe_board_info *np = netdev_priv(dev);
1045
1046 strcpy(info->driver, DRV_NAME);
1047 strcpy(info->version, DRV_VERSION);
1048 if (np->pdev)
1049 strcpy(info->bus_info, pci_name(np->pdev));
1050 else
1051 sprintf(info->bus_info, "EISA 0x%lx %d",
1052 dev->base_addr, dev->irq);
1053}
1054
1055static struct ethtool_ops netdev_ethtool_ops = {
1056 .get_drvinfo = netdev_get_drvinfo,
1057};
1058
1059/*
1060 * A periodic timer routine
1061 * Dynamic media sense, allocate Rx buffer...
1062 */
1063
1064static void dmfe_timer(unsigned long data)
1065{
1066 u32 tmp_cr8;
1067 unsigned char tmp_cr12;
1068 struct DEVICE *dev = (struct DEVICE *) data;
1069 struct dmfe_board_info *db = netdev_priv(dev);
1070 unsigned long flags;
1071
1072 DMFE_DBUG(0, "dmfe_timer()", 0);
1073 spin_lock_irqsave(&db->lock, flags);
1074
1075 /* Media mode process when Link OK before enter this route */
1076 if (db->first_in_callback == 0) {
1077 db->first_in_callback = 1;
1078 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1079 db->cr6_data &= ~0x40000;
1080 update_cr6(db->cr6_data, db->ioaddr);
1081 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1082 db->cr6_data |= 0x40000;
1083 update_cr6(db->cr6_data, db->ioaddr);
1084 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1085 add_timer(&db->timer);
1086 spin_unlock_irqrestore(&db->lock, flags);
1087 return;
1088 }
1089 }
1090
1091
1092 /* Operating Mode Check */
1093 if ( (db->dm910x_chk_mode & 0x1) &&
1094 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1095 db->dm910x_chk_mode = 0x4;
1096
1097 /* Dynamic reset DM910X : system error or transmit time-out */
1098 tmp_cr8 = inl(db->ioaddr + DCR8);
1099 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1100 db->reset_cr8++;
1101 db->wait_reset = 1;
1102 }
1103 db->interval_rx_cnt = 0;
1104
1105 /* TX polling kick monitor */
1106 if ( db->tx_packet_cnt &&
1107 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1108 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1109
1110 /* TX Timeout */
1111 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1112 db->reset_TXtimeout++;
1113 db->wait_reset = 1;
1114 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1115 dev->name);
1116 }
1117 }
1118
1119 if (db->wait_reset) {
1120 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1121 db->reset_count++;
1122 dmfe_dynamic_reset(dev);
1123 db->first_in_callback = 0;
1124 db->timer.expires = DMFE_TIMER_WUT;
1125 add_timer(&db->timer);
1126 spin_unlock_irqrestore(&db->lock, flags);
1127 return;
1128 }
1129
1130 /* Link status check, Dynamic media type change */
1131 if (db->chip_id == PCI_DM9132_ID)
1132 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1133 else
1134 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1135
1136 if ( ((db->chip_id == PCI_DM9102_ID) &&
1137 (db->chip_revision == 0x02000030)) ||
1138 ((db->chip_id == PCI_DM9132_ID) &&
1139 (db->chip_revision == 0x02000010)) ) {
1140 /* DM9102A Chip */
1141 if (tmp_cr12 & 2)
1142 tmp_cr12 = 0x0; /* Link failed */
1143 else
1144 tmp_cr12 = 0x3; /* Link OK */
1145 }
1146
1147 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1148 /* Link Failed */
1149 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1150 db->link_failed = 1;
1151
1152 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1153 /* AUTO or force 1M Homerun/Longrun don't need */
1154 if ( !(db->media_mode & 0x38) )
1155 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1156
1157 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1158 if (db->media_mode & DMFE_AUTO) {
1159 /* 10/100M link failed, used 1M Home-Net */
1160 db->cr6_data|=0x00040000; /* bit18=1, MII */
1161 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1162 update_cr6(db->cr6_data, db->ioaddr);
1163 }
1164 } else
1165 if ((tmp_cr12 & 0x3) && db->link_failed) {
1166 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1167 db->link_failed = 0;
1168
1169 /* Auto Sense Speed */
1170 if ( (db->media_mode & DMFE_AUTO) &&
1171 dmfe_sense_speed(db) )
1172 db->link_failed = 1;
1173 dmfe_process_mode(db);
1174 /* SHOW_MEDIA_TYPE(db->op_mode); */
1175 }
1176
1177 /* HPNA remote command check */
1178 if (db->HPNA_command & 0xf00) {
1179 db->HPNA_timer--;
1180 if (!db->HPNA_timer)
1181 dmfe_HPNA_remote_cmd_chk(db);
1182 }
1183
1184 /* Timer active again */
1185 db->timer.expires = DMFE_TIMER_WUT;
1186 add_timer(&db->timer);
1187 spin_unlock_irqrestore(&db->lock, flags);
1188}
1189
1190
1191/*
1192 * Dynamic reset the DM910X board
1193 * Stop DM910X board
1194 * Free Tx/Rx allocated memory
1195 * Reset DM910X board
1196 * Re-initilize DM910X board
1197 */
1198
1199static void dmfe_dynamic_reset(struct DEVICE *dev)
1200{
1201 struct dmfe_board_info *db = netdev_priv(dev);
1202
1203 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1204
1205 /* Sopt MAC controller */
1206 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1207 update_cr6(db->cr6_data, dev->base_addr);
1208 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1209 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1210
1211 /* Disable upper layer interface */
1212 netif_stop_queue(dev);
1213
1214 /* Free Rx Allocate buffer */
1215 dmfe_free_rxbuffer(db);
1216
1217 /* system variable init */
1218 db->tx_packet_cnt = 0;
1219 db->tx_queue_cnt = 0;
1220 db->rx_avail_cnt = 0;
1221 db->link_failed = 1;
1222 db->wait_reset = 0;
1223
1224 /* Re-initilize DM910X board */
1225 dmfe_init_dm910x(dev);
1226
1227 /* Restart upper layer interface */
1228 netif_wake_queue(dev);
1229}
1230
1231
1232/*
1233 * free all allocated rx buffer
1234 */
1235
1236static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1237{
1238 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1239
1240 /* free allocated rx buffer */
1241 while (db->rx_avail_cnt) {
1242 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1243 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1244 db->rx_avail_cnt--;
1245 }
1246}
1247
1248
1249/*
1250 * Reuse the SK buffer
1251 */
1252
1253static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1254{
1255 struct rx_desc *rxptr = db->rx_insert_ptr;
1256
1257 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1258 rxptr->rx_skb_ptr = skb;
1259 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1260 wmb();
1261 rxptr->rdes0 = cpu_to_le32(0x80000000);
1262 db->rx_avail_cnt++;
1263 db->rx_insert_ptr = rxptr->next_rx_desc;
1264 } else
1265 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1266}
1267
1268
1269/*
1270 * Initialize transmit/Receive descriptor
1271 * Using Chain structure, and allocate Tx/Rx buffer
1272 */
1273
1274static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1275{
1276 struct tx_desc *tmp_tx;
1277 struct rx_desc *tmp_rx;
1278 unsigned char *tmp_buf;
1279 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1280 dma_addr_t tmp_buf_dma;
1281 int i;
1282
1283 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1284
1285 /* tx descriptor start pointer */
1286 db->tx_insert_ptr = db->first_tx_desc;
1287 db->tx_remove_ptr = db->first_tx_desc;
1288 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1289
1290 /* rx descriptor start pointer */
1291 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1292 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1293 db->rx_insert_ptr = db->first_rx_desc;
1294 db->rx_ready_ptr = db->first_rx_desc;
1295 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1296
1297 /* Init Transmit chain */
1298 tmp_buf = db->buf_pool_start;
1299 tmp_buf_dma = db->buf_pool_dma_start;
1300 tmp_tx_dma = db->first_tx_desc_dma;
1301 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1302 tmp_tx->tx_buf_ptr = tmp_buf;
1303 tmp_tx->tdes0 = cpu_to_le32(0);
1304 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1305 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1306 tmp_tx_dma += sizeof(struct tx_desc);
1307 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1308 tmp_tx->next_tx_desc = tmp_tx + 1;
1309 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1310 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1311 }
1312 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1313 tmp_tx->next_tx_desc = db->first_tx_desc;
1314
1315 /* Init Receive descriptor chain */
1316 tmp_rx_dma=db->first_rx_desc_dma;
1317 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1318 tmp_rx->rdes0 = cpu_to_le32(0);
1319 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1320 tmp_rx_dma += sizeof(struct rx_desc);
1321 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1322 tmp_rx->next_rx_desc = tmp_rx + 1;
1323 }
1324 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1325 tmp_rx->next_rx_desc = db->first_rx_desc;
1326
1327 /* pre-allocate Rx buffer */
1328 allocate_rx_buffer(db);
1329}
1330
1331
1332/*
1333 * Update CR6 value
1334 * Firstly stop DM910X , then written value and start
1335 */
1336
1337static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1338{
1339 u32 cr6_tmp;
1340
1341 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1342 outl(cr6_tmp, ioaddr + DCR6);
1343 udelay(5);
1344 outl(cr6_data, ioaddr + DCR6);
1345 udelay(5);
1346}
1347
1348
1349/*
1350 * Send a setup frame for DM9132
1351 * This setup frame initilize DM910X address filter mode
1352*/
1353
1354static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1355{
1356 struct dev_mc_list *mcptr;
1357 u16 * addrptr;
1358 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1359 u32 hash_val;
1360 u16 i, hash_table[4];
1361
1362 DMFE_DBUG(0, "dm9132_id_table()", 0);
1363
1364 /* Node address */
1365 addrptr = (u16 *) dev->dev_addr;
1366 outw(addrptr[0], ioaddr);
1367 ioaddr += 4;
1368 outw(addrptr[1], ioaddr);
1369 ioaddr += 4;
1370 outw(addrptr[2], ioaddr);
1371 ioaddr += 4;
1372
1373 /* Clear Hash Table */
1374 for (i = 0; i < 4; i++)
1375 hash_table[i] = 0x0;
1376
1377 /* broadcast address */
1378 hash_table[3] = 0x8000;
1379
1380 /* the multicast address in Hash Table : 64 bits */
1381 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1382 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1383 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1384 }
1385
1386 /* Write the hash table to MAC MD table */
1387 for (i = 0; i < 4; i++, ioaddr += 4)
1388 outw(hash_table[i], ioaddr);
1389}
1390
1391
1392/*
1393 * Send a setup frame for DM9102/DM9102A
1394 * This setup frame initilize DM910X address filter mode
1395 */
1396
1397static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1398{
1399 struct dmfe_board_info *db = netdev_priv(dev);
1400 struct dev_mc_list *mcptr;
1401 struct tx_desc *txptr;
1402 u16 * addrptr;
1403 u32 * suptr;
1404 int i;
1405
1406 DMFE_DBUG(0, "send_filter_frame()", 0);
1407
1408 txptr = db->tx_insert_ptr;
1409 suptr = (u32 *) txptr->tx_buf_ptr;
1410
1411 /* Node address */
1412 addrptr = (u16 *) dev->dev_addr;
1413 *suptr++ = addrptr[0];
1414 *suptr++ = addrptr[1];
1415 *suptr++ = addrptr[2];
1416
1417 /* broadcast address */
1418 *suptr++ = 0xffff;
1419 *suptr++ = 0xffff;
1420 *suptr++ = 0xffff;
1421
1422 /* fit the multicast address */
1423 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1424 addrptr = (u16 *) mcptr->dmi_addr;
1425 *suptr++ = addrptr[0];
1426 *suptr++ = addrptr[1];
1427 *suptr++ = addrptr[2];
1428 }
1429
1430 for (; i<14; i++) {
1431 *suptr++ = 0xffff;
1432 *suptr++ = 0xffff;
1433 *suptr++ = 0xffff;
1434 }
1435
1436 /* prepare the setup frame */
1437 db->tx_insert_ptr = txptr->next_tx_desc;
1438 txptr->tdes1 = cpu_to_le32(0x890000c0);
1439
1440 /* Resource Check and Send the setup packet */
1441 if (!db->tx_packet_cnt) {
1442 /* Resource Empty */
1443 db->tx_packet_cnt++;
1444 txptr->tdes0 = cpu_to_le32(0x80000000);
1445 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1446 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1447 update_cr6(db->cr6_data, dev->base_addr);
1448 dev->trans_start = jiffies;
1449 } else
1450 db->tx_queue_cnt++; /* Put in TX queue */
1451}
1452
1453
1454/*
1455 * Allocate rx buffer,
1456 * As possible as allocate maxiumn Rx buffer
1457 */
1458
1459static void allocate_rx_buffer(struct dmfe_board_info *db)
1460{
1461 struct rx_desc *rxptr;
1462 struct sk_buff *skb;
1463
1464 rxptr = db->rx_insert_ptr;
1465
1466 while(db->rx_avail_cnt < RX_DESC_CNT) {
1467 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1468 break;
1469 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1470 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1471 wmb();
1472 rxptr->rdes0 = cpu_to_le32(0x80000000);
1473 rxptr = rxptr->next_rx_desc;
1474 db->rx_avail_cnt++;
1475 }
1476
1477 db->rx_insert_ptr = rxptr;
1478}
1479
1480
1481/*
1482 * Read one word data from the serial ROM
1483 */
1484
1485static u16 read_srom_word(long ioaddr, int offset)
1486{
1487 int i;
1488 u16 srom_data = 0;
1489 long cr9_ioaddr = ioaddr + DCR9;
1490
1491 outl(CR9_SROM_READ, cr9_ioaddr);
1492 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1493
1494 /* Send the Read Command 110b */
1495 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1496 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1497 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1498
1499 /* Send the offset */
1500 for (i = 5; i >= 0; i--) {
1501 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1502 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1503 }
1504
1505 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1506
1507 for (i = 16; i > 0; i--) {
1508 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1509 udelay(5);
1510 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1511 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1512 udelay(5);
1513 }
1514
1515 outl(CR9_SROM_READ, cr9_ioaddr);
1516 return srom_data;
1517}
1518
1519
1520/*
1521 * Auto sense the media mode
1522 */
1523
1524static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1525{
1526 u8 ErrFlag = 0;
1527 u16 phy_mode;
1528
1529 /* CR6 bit18=0, select 10/100M */
1530 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1531
1532 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1533 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1534
1535 if ( (phy_mode & 0x24) == 0x24 ) {
1536 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1537 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1538 else /* DM9102/DM9102A */
1539 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1540 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1541 switch (phy_mode) {
1542 case 0x1000: db->op_mode = DMFE_10MHF; break;
1543 case 0x2000: db->op_mode = DMFE_10MFD; break;
1544 case 0x4000: db->op_mode = DMFE_100MHF; break;
1545 case 0x8000: db->op_mode = DMFE_100MFD; break;
1546 default: db->op_mode = DMFE_10MHF;
1547 ErrFlag = 1;
1548 break;
1549 }
1550 } else {
1551 db->op_mode = DMFE_10MHF;
1552 DMFE_DBUG(0, "Link Failed :", phy_mode);
1553 ErrFlag = 1;
1554 }
1555
1556 return ErrFlag;
1557}
1558
1559
1560/*
1561 * Set 10/100 phyxcer capability
1562 * AUTO mode : phyxcer register4 is NIC capability
1563 * Force mode: phyxcer register4 is the force media
1564 */
1565
1566static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1567{
1568 u16 phy_reg;
1569
1570 /* Select 10/100M phyxcer */
1571 db->cr6_data &= ~0x40000;
1572 update_cr6(db->cr6_data, db->ioaddr);
1573
1574 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1575 if (db->chip_id == PCI_DM9009_ID) {
1576 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1577 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1578 }
1579
1580 /* Phyxcer capability setting */
1581 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1582
1583 if (db->media_mode & DMFE_AUTO) {
1584 /* AUTO Mode */
1585 phy_reg |= db->PHY_reg4;
1586 } else {
1587 /* Force Mode */
1588 switch(db->media_mode) {
1589 case DMFE_10MHF: phy_reg |= 0x20; break;
1590 case DMFE_10MFD: phy_reg |= 0x40; break;
1591 case DMFE_100MHF: phy_reg |= 0x80; break;
1592 case DMFE_100MFD: phy_reg |= 0x100; break;
1593 }
1594 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1595 }
1596
1597 /* Write new capability to Phyxcer Reg4 */
1598 if ( !(phy_reg & 0x01e0)) {
1599 phy_reg|=db->PHY_reg4;
1600 db->media_mode|=DMFE_AUTO;
1601 }
1602 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1603
1604 /* Restart Auto-Negotiation */
1605 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1606 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1607 if ( !db->chip_type )
1608 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1609}
1610
1611
1612/*
1613 * Process op-mode
1614 * AUTO mode : PHY controller in Auto-negotiation Mode
1615 * Force mode: PHY controller in force mode with HUB
1616 * N-way force capability with SWITCH
1617 */
1618
1619static void dmfe_process_mode(struct dmfe_board_info *db)
1620{
1621 u16 phy_reg;
1622
1623 /* Full Duplex Mode Check */
1624 if (db->op_mode & 0x4)
1625 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1626 else
1627 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1628
1629 /* Transciver Selection */
1630 if (db->op_mode & 0x10) /* 1M HomePNA */
1631 db->cr6_data |= 0x40000;/* External MII select */
1632 else
1633 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1634
1635 update_cr6(db->cr6_data, db->ioaddr);
1636
1637 /* 10/100M phyxcer force mode need */
1638 if ( !(db->media_mode & 0x18)) {
1639 /* Forece Mode */
1640 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1641 if ( !(phy_reg & 0x1) ) {
1642 /* parter without N-Way capability */
1643 phy_reg = 0x0;
1644 switch(db->op_mode) {
1645 case DMFE_10MHF: phy_reg = 0x0; break;
1646 case DMFE_10MFD: phy_reg = 0x100; break;
1647 case DMFE_100MHF: phy_reg = 0x2000; break;
1648 case DMFE_100MFD: phy_reg = 0x2100; break;
1649 }
1650 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1651 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1652 mdelay(20);
1653 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1654 }
1655 }
1656}
1657
1658
1659/*
1660 * Write a word to Phy register
1661 */
1662
1663static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1664{
1665 u16 i;
1666 unsigned long ioaddr;
1667
1668 if (chip_id == PCI_DM9132_ID) {
1669 ioaddr = iobase + 0x80 + offset * 4;
1670 outw(phy_data, ioaddr);
1671 } else {
1672 /* DM9102/DM9102A Chip */
1673 ioaddr = iobase + DCR9;
1674
1675 /* Send 33 synchronization clock to Phy controller */
1676 for (i = 0; i < 35; i++)
1677 phy_write_1bit(ioaddr, PHY_DATA_1);
1678
1679 /* Send start command(01) to Phy */
1680 phy_write_1bit(ioaddr, PHY_DATA_0);
1681 phy_write_1bit(ioaddr, PHY_DATA_1);
1682
1683 /* Send write command(01) to Phy */
1684 phy_write_1bit(ioaddr, PHY_DATA_0);
1685 phy_write_1bit(ioaddr, PHY_DATA_1);
1686
1687 /* Send Phy address */
1688 for (i = 0x10; i > 0; i = i >> 1)
1689 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1690
1691 /* Send register address */
1692 for (i = 0x10; i > 0; i = i >> 1)
1693 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1694
1695 /* written trasnition */
1696 phy_write_1bit(ioaddr, PHY_DATA_1);
1697 phy_write_1bit(ioaddr, PHY_DATA_0);
1698
1699 /* Write a word data to PHY controller */
1700 for ( i = 0x8000; i > 0; i >>= 1)
1701 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1702 }
1703}
1704
1705
1706/*
1707 * Read a word data from phy register
1708 */
1709
1710static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1711{
1712 int i;
1713 u16 phy_data;
1714 unsigned long ioaddr;
1715
1716 if (chip_id == PCI_DM9132_ID) {
1717 /* DM9132 Chip */
1718 ioaddr = iobase + 0x80 + offset * 4;
1719 phy_data = inw(ioaddr);
1720 } else {
1721 /* DM9102/DM9102A Chip */
1722 ioaddr = iobase + DCR9;
1723
1724 /* Send 33 synchronization clock to Phy controller */
1725 for (i = 0; i < 35; i++)
1726 phy_write_1bit(ioaddr, PHY_DATA_1);
1727
1728 /* Send start command(01) to Phy */
1729 phy_write_1bit(ioaddr, PHY_DATA_0);
1730 phy_write_1bit(ioaddr, PHY_DATA_1);
1731
1732 /* Send read command(10) to Phy */
1733 phy_write_1bit(ioaddr, PHY_DATA_1);
1734 phy_write_1bit(ioaddr, PHY_DATA_0);
1735
1736 /* Send Phy address */
1737 for (i = 0x10; i > 0; i = i >> 1)
1738 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1739
1740 /* Send register address */
1741 for (i = 0x10; i > 0; i = i >> 1)
1742 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1743
1744 /* Skip transition state */
1745 phy_read_1bit(ioaddr);
1746
1747 /* read 16bit data */
1748 for (phy_data = 0, i = 0; i < 16; i++) {
1749 phy_data <<= 1;
1750 phy_data |= phy_read_1bit(ioaddr);
1751 }
1752 }
1753
1754 return phy_data;
1755}
1756
1757
1758/*
1759 * Write one bit data to Phy Controller
1760 */
1761
1762static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1763{
1764 outl(phy_data, ioaddr); /* MII Clock Low */
1765 udelay(1);
1766 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1767 udelay(1);
1768 outl(phy_data, ioaddr); /* MII Clock Low */
1769 udelay(1);
1770}
1771
1772
1773/*
1774 * Read one bit phy data from PHY controller
1775 */
1776
1777static u16 phy_read_1bit(unsigned long ioaddr)
1778{
1779 u16 phy_data;
1780
1781 outl(0x50000, ioaddr);
1782 udelay(1);
1783 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1784 outl(0x40000, ioaddr);
1785 udelay(1);
1786
1787 return phy_data;
1788}
1789
1790
1791/*
1792 * Parser SROM and media mode
1793 */
1794
1795static void dmfe_parse_srom(struct dmfe_board_info * db)
1796{
1797 char * srom = db->srom;
1798 int dmfe_mode, tmp_reg;
1799
1800 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1801
1802 /* Init CR15 */
1803 db->cr15_data = CR15_DEFAULT;
1804
1805 /* Check SROM Version */
1806 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1807 /* SROM V4.01 */
1808 /* Get NIC support media mode */
1809 db->NIC_capability = le16_to_cpup(srom + 34);
1810 db->PHY_reg4 = 0;
1811 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1812 switch( db->NIC_capability & tmp_reg ) {
1813 case 0x1: db->PHY_reg4 |= 0x0020; break;
1814 case 0x2: db->PHY_reg4 |= 0x0040; break;
1815 case 0x4: db->PHY_reg4 |= 0x0080; break;
1816 case 0x8: db->PHY_reg4 |= 0x0100; break;
1817 }
1818 }
1819
1820 /* Media Mode Force or not check */
1821 dmfe_mode = le32_to_cpup(srom + 34) & le32_to_cpup(srom + 36);
1822 switch(dmfe_mode) {
1823 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1824 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1825 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1826 case 0x100:
1827 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1828 }
1829
1830 /* Special Function setting */
1831 /* VLAN function */
1832 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1833 db->cr15_data |= 0x40;
1834
1835 /* Flow Control */
1836 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1837 db->cr15_data |= 0x400;
1838
1839 /* TX pause packet */
1840 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1841 db->cr15_data |= 0x9800;
1842 }
1843
1844 /* Parse HPNA parameter */
1845 db->HPNA_command = 1;
1846
1847 /* Accept remote command or not */
1848 if (HPNA_rx_cmd == 0)
1849 db->HPNA_command |= 0x8000;
1850
1851 /* Issue remote command & operation mode */
1852 if (HPNA_tx_cmd == 1)
1853 switch(HPNA_mode) { /* Issue Remote Command */
1854 case 0: db->HPNA_command |= 0x0904; break;
1855 case 1: db->HPNA_command |= 0x0a00; break;
1856 case 2: db->HPNA_command |= 0x0506; break;
1857 case 3: db->HPNA_command |= 0x0602; break;
1858 }
1859 else
1860 switch(HPNA_mode) { /* Don't Issue */
1861 case 0: db->HPNA_command |= 0x0004; break;
1862 case 1: db->HPNA_command |= 0x0000; break;
1863 case 2: db->HPNA_command |= 0x0006; break;
1864 case 3: db->HPNA_command |= 0x0002; break;
1865 }
1866
1867 /* Check DM9801 or DM9802 present or not */
1868 db->HPNA_present = 0;
1869 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1870 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1871 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1872 /* DM9801 or DM9802 present */
1873 db->HPNA_timer = 8;
1874 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1875 /* DM9801 HomeRun */
1876 db->HPNA_present = 1;
1877 dmfe_program_DM9801(db, tmp_reg);
1878 } else {
1879 /* DM9802 LongRun */
1880 db->HPNA_present = 2;
1881 dmfe_program_DM9802(db);
1882 }
1883 }
1884
1885}
1886
1887
1888/*
1889 * Init HomeRun DM9801
1890 */
1891
1892static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1893{
1894 uint reg17, reg25;
1895
1896 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1897 switch(HPNA_rev) {
1898 case 0xb900: /* DM9801 E3 */
1899 db->HPNA_command |= 0x1000;
1900 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1901 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1902 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1903 break;
1904 case 0xb901: /* DM9801 E4 */
1905 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1906 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1907 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1908 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1909 break;
1910 case 0xb902: /* DM9801 E5 */
1911 case 0xb903: /* DM9801 E6 */
1912 default:
1913 db->HPNA_command |= 0x1000;
1914 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1915 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1916 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1917 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1918 break;
1919 }
1920 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1921 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1922 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1923}
1924
1925
1926/*
1927 * Init HomeRun DM9802
1928 */
1929
1930static void dmfe_program_DM9802(struct dmfe_board_info * db)
1931{
1932 uint phy_reg;
1933
1934 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1935 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1936 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1937 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1938 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1939}
1940
1941
1942/*
1943 * Check remote HPNA power and speed status. If not correct,
1944 * issue command again.
1945*/
1946
1947static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1948{
1949 uint phy_reg;
1950
1951 /* Got remote device status */
1952 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1953 switch(phy_reg) {
1954 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1955 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1956 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1957 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1958 }
1959
1960 /* Check remote device status match our setting ot not */
1961 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1962 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1963 db->HPNA_timer=8;
1964 } else
1965 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1966}
1967
1968
1969
1970static struct pci_device_id dmfe_pci_tbl[] = {
1971 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1972 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1973 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1974 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1975 { 0, }
1976};
1977MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1978
1979
1980static struct pci_driver dmfe_driver = {
1981 .name = "dmfe",
1982 .id_table = dmfe_pci_tbl,
1983 .probe = dmfe_init_one,
1984 .remove = __devexit_p(dmfe_remove_one),
1985};
1986
1987MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1988MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1989MODULE_LICENSE("GPL");
1990MODULE_VERSION(DRV_VERSION);
1991
1992module_param(debug, int, 0);
1993module_param(mode, byte, 0);
1994module_param(cr6set, int, 0);
1995module_param(chkmode, byte, 0);
1996module_param(HPNA_mode, byte, 0);
1997module_param(HPNA_rx_cmd, byte, 0);
1998module_param(HPNA_tx_cmd, byte, 0);
1999module_param(HPNA_NoiseFloor, byte, 0);
2000module_param(SF_mode, byte, 0);
2001MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2002MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2003MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2004
2005/* Description:
2006 * when user used insmod to add module, system invoked init_module()
2007 * to initilize and register.
2008 */
2009
2010static int __init dmfe_init_module(void)
2011{
2012 int rc;
2013
2014 printk(version);
2015 printed_version = 1;
2016
2017 DMFE_DBUG(0, "init_module() ", debug);
2018
2019 if (debug)
2020 dmfe_debug = debug; /* set debug flag */
2021 if (cr6set)
2022 dmfe_cr6_user_set = cr6set;
2023
2024 switch(mode) {
2025 case DMFE_10MHF:
2026 case DMFE_100MHF:
2027 case DMFE_10MFD:
2028 case DMFE_100MFD:
2029 case DMFE_1M_HPNA:
2030 dmfe_media_mode = mode;
2031 break;
2032 default:dmfe_media_mode = DMFE_AUTO;
2033 break;
2034 }
2035
2036 if (HPNA_mode > 4)
2037 HPNA_mode = 0; /* Default: LP/HS */
2038 if (HPNA_rx_cmd > 1)
2039 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2040 if (HPNA_tx_cmd > 1)
2041 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2042 if (HPNA_NoiseFloor > 15)
2043 HPNA_NoiseFloor = 0;
2044
2045 rc = pci_module_init(&dmfe_driver);
2046 if (rc < 0)
2047 return rc;
2048
2049 return 0;
2050}
2051
2052
2053/*
2054 * Description:
2055 * when user used rmmod to delete module, system invoked clean_module()
2056 * to un-register all registered services.
2057 */
2058
2059static void __exit dmfe_cleanup_module(void)
2060{
2061 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2062 pci_unregister_driver(&dmfe_driver);
2063}
2064
2065module_init(dmfe_init_module);
2066module_exit(dmfe_cleanup_module);
diff --git a/drivers/net/tulip/eeprom.c b/drivers/net/tulip/eeprom.c
new file mode 100644
index 000000000000..ac5bf49ff60f
--- /dev/null
+++ b/drivers/net/tulip/eeprom.c
@@ -0,0 +1,357 @@
1/*
2 drivers/net/tulip/eeprom.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/pci.h>
18#include "tulip.h"
19#include <linux/init.h>
20#include <asm/unaligned.h>
21
22
23
24/* Serial EEPROM section. */
25/* The main routine to parse the very complicated SROM structure.
26 Search www.digital.com for "21X4 SROM" to get details.
27 This code is very complex, and will require changes to support
28 additional cards, so I'll be verbose about what is going on.
29 */
30
31/* Known cards that have old-style EEPROMs. */
32static struct eeprom_fixup eeprom_fixups[] __devinitdata = {
33 {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
34 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
35 {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
36 0x0000, 0x009E, /* 10baseT */
37 0x0004, 0x009E, /* 10baseT-FD */
38 0x0903, 0x006D, /* 100baseTx */
39 0x0905, 0x006D, /* 100baseTx-FD */ }},
40 {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
41 0x0107, 0x8021, /* 100baseFx */
42 0x0108, 0x8021, /* 100baseFx-FD */
43 0x0100, 0x009E, /* 10baseT */
44 0x0104, 0x009E, /* 10baseT-FD */
45 0x0103, 0x006D, /* 100baseTx */
46 0x0105, 0x006D, /* 100baseTx-FD */ }},
47 {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
48 0x1001, 0x009E, /* 10base2, CSR12 0x10*/
49 0x0000, 0x009E, /* 10baseT */
50 0x0004, 0x009E, /* 10baseT-FD */
51 0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */
52 0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}},
53 {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F,
54 0x1B01, 0x0000, /* 10base2, CSR12 0x1B */
55 0x0B00, 0x009E, /* 10baseT, CSR12 0x0B */
56 0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */
57 0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */
58 0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */
59 }},
60 {"NetWinder", 0x00, 0x10, 0x57,
61 /* Default media = MII
62 * MII block, reset sequence (3) = 0x0821 0x0000 0x0001, capabilities 0x01e1
63 */
64 { 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 }
65 },
66 {NULL}};
67
68
69static const char *block_name[] __devinitdata = {
70 "21140 non-MII",
71 "21140 MII PHY",
72 "21142 Serial PHY",
73 "21142 MII PHY",
74 "21143 SYM PHY",
75 "21143 reset method"
76};
77
78
79/**
80 * tulip_build_fake_mediatable - Build a fake mediatable entry.
81 * @tp: Ptr to the tulip private data.
82 *
83 * Some cards like the 3x5 HSC cards (J3514A) do not have a standard
84 * srom and can not be handled under the fixup routine. These cards
85 * still need a valid mediatable entry for correct csr12 setup and
86 * mii handling.
87 *
88 * Since this is currently a parisc-linux specific function, the
89 * #ifdef __hppa__ should completely optimize this function away for
90 * non-parisc hardware.
91 */
92static void __devinit tulip_build_fake_mediatable(struct tulip_private *tp)
93{
94#ifdef CONFIG_GSC
95 if (tp->flags & NEEDS_FAKE_MEDIA_TABLE) {
96 static unsigned char leafdata[] =
97 { 0x01, /* phy number */
98 0x02, /* gpr setup sequence length */
99 0x02, 0x00, /* gpr setup sequence */
100 0x02, /* phy reset sequence length */
101 0x01, 0x00, /* phy reset sequence */
102 0x00, 0x78, /* media capabilities */
103 0x00, 0xe0, /* nway advertisment */
104 0x00, 0x05, /* fdx bit map */
105 0x00, 0x06 /* ttm bit map */
106 };
107
108 tp->mtable = (struct mediatable *)
109 kmalloc(sizeof(struct mediatable) + sizeof(struct medialeaf), GFP_KERNEL);
110
111 if (tp->mtable == NULL)
112 return; /* Horrible, impossible failure. */
113
114 tp->mtable->defaultmedia = 0x800;
115 tp->mtable->leafcount = 1;
116 tp->mtable->csr12dir = 0x3f; /* inputs on bit7 for hsc-pci, bit6 for pci-fx */
117 tp->mtable->has_nonmii = 0;
118 tp->mtable->has_reset = 0;
119 tp->mtable->has_mii = 1;
120 tp->mtable->csr15dir = tp->mtable->csr15val = 0;
121 tp->mtable->mleaf[0].type = 1;
122 tp->mtable->mleaf[0].media = 11;
123 tp->mtable->mleaf[0].leafdata = &leafdata[0];
124 tp->flags |= HAS_PHY_IRQ;
125 tp->csr12_shadow = -1;
126 }
127#endif
128}
129
130void __devinit tulip_parse_eeprom(struct net_device *dev)
131{
132 /* The last media info list parsed, for multiport boards. */
133 static struct mediatable *last_mediatable;
134 static unsigned char *last_ee_data;
135 static int controller_index;
136 struct tulip_private *tp = netdev_priv(dev);
137 unsigned char *ee_data = tp->eeprom;
138 int i;
139
140 tp->mtable = NULL;
141 /* Detect an old-style (SA only) EEPROM layout:
142 memcmp(eedata, eedata+16, 8). */
143 for (i = 0; i < 8; i ++)
144 if (ee_data[i] != ee_data[16+i])
145 break;
146 if (i >= 8) {
147 if (ee_data[0] == 0xff) {
148 if (last_mediatable) {
149 controller_index++;
150 printk(KERN_INFO "%s: Controller %d of multiport board.\n",
151 dev->name, controller_index);
152 tp->mtable = last_mediatable;
153 ee_data = last_ee_data;
154 goto subsequent_board;
155 } else
156 printk(KERN_INFO "%s: Missing EEPROM, this interface may "
157 "not work correctly!\n",
158 dev->name);
159 return;
160 }
161 /* Do a fix-up based on the vendor half of the station address prefix. */
162 for (i = 0; eeprom_fixups[i].name; i++) {
163 if (dev->dev_addr[0] == eeprom_fixups[i].addr0
164 && dev->dev_addr[1] == eeprom_fixups[i].addr1
165 && dev->dev_addr[2] == eeprom_fixups[i].addr2) {
166 if (dev->dev_addr[2] == 0xE8 && ee_data[0x1a] == 0x55)
167 i++; /* An Accton EN1207, not an outlaw Maxtech. */
168 memcpy(ee_data + 26, eeprom_fixups[i].newtable,
169 sizeof(eeprom_fixups[i].newtable));
170 printk(KERN_INFO "%s: Old format EEPROM on '%s' board. Using"
171 " substitute media control info.\n",
172 dev->name, eeprom_fixups[i].name);
173 break;
174 }
175 }
176 if (eeprom_fixups[i].name == NULL) { /* No fixup found. */
177 printk(KERN_INFO "%s: Old style EEPROM with no media selection "
178 "information.\n",
179 dev->name);
180 return;
181 }
182 }
183
184 controller_index = 0;
185 if (ee_data[19] > 1) { /* Multiport board. */
186 last_ee_data = ee_data;
187 }
188subsequent_board:
189
190 if (ee_data[27] == 0) { /* No valid media table. */
191 tulip_build_fake_mediatable(tp);
192 } else {
193 unsigned char *p = (void *)ee_data + ee_data[27];
194 unsigned char csr12dir = 0;
195 int count, new_advertise = 0;
196 struct mediatable *mtable;
197 u16 media = get_u16(p);
198
199 p += 2;
200 if (tp->flags & CSR12_IN_SROM)
201 csr12dir = *p++;
202 count = *p++;
203
204 /* there is no phy information, don't even try to build mtable */
205 if (count == 0) {
206 if (tulip_debug > 0)
207 printk(KERN_WARNING "%s: no phy info, aborting mtable build\n", dev->name);
208 return;
209 }
210
211 mtable = (struct mediatable *)
212 kmalloc(sizeof(struct mediatable) + count*sizeof(struct medialeaf),
213 GFP_KERNEL);
214 if (mtable == NULL)
215 return; /* Horrible, impossible failure. */
216 last_mediatable = tp->mtable = mtable;
217 mtable->defaultmedia = media;
218 mtable->leafcount = count;
219 mtable->csr12dir = csr12dir;
220 mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0;
221 mtable->csr15dir = mtable->csr15val = 0;
222
223 printk(KERN_INFO "%s: EEPROM default media type %s.\n", dev->name,
224 media & 0x0800 ? "Autosense" : medianame[media & MEDIA_MASK]);
225 for (i = 0; i < count; i++) {
226 struct medialeaf *leaf = &mtable->mleaf[i];
227
228 if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */
229 leaf->type = 0;
230 leaf->media = p[0] & 0x3f;
231 leaf->leafdata = p;
232 if ((p[2] & 0x61) == 0x01) /* Bogus, but Znyx boards do it. */
233 mtable->has_mii = 1;
234 p += 4;
235 } else {
236 leaf->type = p[1];
237 if (p[1] == 0x05) {
238 mtable->has_reset = i;
239 leaf->media = p[2] & 0x0f;
240 } else if (tp->chip_id == DM910X && p[1] == 0x80) {
241 /* Hack to ignore Davicom delay period block */
242 mtable->leafcount--;
243 count--;
244 i--;
245 leaf->leafdata = p + 2;
246 p += (p[0] & 0x3f) + 1;
247 continue;
248 } else if (p[1] & 1) {
249 int gpr_len, reset_len;
250
251 mtable->has_mii = 1;
252 leaf->media = 11;
253 gpr_len=p[3]*2;
254 reset_len=p[4+gpr_len]*2;
255 new_advertise |= get_u16(&p[7+gpr_len+reset_len]);
256 } else {
257 mtable->has_nonmii = 1;
258 leaf->media = p[2] & MEDIA_MASK;
259 /* Davicom's media number for 100BaseTX is strange */
260 if (tp->chip_id == DM910X && leaf->media == 1)
261 leaf->media = 3;
262 switch (leaf->media) {
263 case 0: new_advertise |= 0x0020; break;
264 case 4: new_advertise |= 0x0040; break;
265 case 3: new_advertise |= 0x0080; break;
266 case 5: new_advertise |= 0x0100; break;
267 case 6: new_advertise |= 0x0200; break;
268 }
269 if (p[1] == 2 && leaf->media == 0) {
270 if (p[2] & 0x40) {
271 u32 base15 = get_unaligned((u16*)&p[7]);
272 mtable->csr15dir =
273 (get_unaligned((u16*)&p[9])<<16) + base15;
274 mtable->csr15val =
275 (get_unaligned((u16*)&p[11])<<16) + base15;
276 } else {
277 mtable->csr15dir = get_unaligned((u16*)&p[3])<<16;
278 mtable->csr15val = get_unaligned((u16*)&p[5])<<16;
279 }
280 }
281 }
282 leaf->leafdata = p + 2;
283 p += (p[0] & 0x3f) + 1;
284 }
285 if (tulip_debug > 1 && leaf->media == 11) {
286 unsigned char *bp = leaf->leafdata;
287 printk(KERN_INFO "%s: MII interface PHY %d, setup/reset "
288 "sequences %d/%d long, capabilities %2.2x %2.2x.\n",
289 dev->name, bp[0], bp[1], bp[2 + bp[1]*2],
290 bp[5 + bp[2 + bp[1]*2]*2], bp[4 + bp[2 + bp[1]*2]*2]);
291 }
292 printk(KERN_INFO "%s: Index #%d - Media %s (#%d) described "
293 "by a %s (%d) block.\n",
294 dev->name, i, medianame[leaf->media & 15], leaf->media,
295 leaf->type < ARRAY_SIZE(block_name) ? block_name[leaf->type] : "<unknown>",
296 leaf->type);
297 }
298 if (new_advertise)
299 tp->sym_advertise = new_advertise;
300 }
301}
302/* Reading a serial EEPROM is a "bit" grungy, but we work our way through:->.*/
303
304/* EEPROM_Ctrl bits. */
305#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
306#define EE_CS 0x01 /* EEPROM chip select. */
307#define EE_DATA_WRITE 0x04 /* Data from the Tulip to EEPROM. */
308#define EE_WRITE_0 0x01
309#define EE_WRITE_1 0x05
310#define EE_DATA_READ 0x08 /* Data from the EEPROM chip. */
311#define EE_ENB (0x4800 | EE_CS)
312
313/* Delay between EEPROM clock transitions.
314 Even at 33Mhz current PCI implementations don't overrun the EEPROM clock.
315 We add a bus turn-around to insure that this remains true. */
316#define eeprom_delay() ioread32(ee_addr)
317
318/* The EEPROM commands include the alway-set leading bit. */
319#define EE_READ_CMD (6)
320
321/* Note: this routine returns extra data bits for size detection. */
322int __devinit tulip_read_eeprom(struct net_device *dev, int location, int addr_len)
323{
324 int i;
325 unsigned retval = 0;
326 struct tulip_private *tp = dev->priv;
327 void __iomem *ee_addr = tp->base_addr + CSR9;
328 int read_cmd = location | (EE_READ_CMD << addr_len);
329
330 iowrite32(EE_ENB & ~EE_CS, ee_addr);
331 iowrite32(EE_ENB, ee_addr);
332
333 /* Shift the read command bits out. */
334 for (i = 4 + addr_len; i >= 0; i--) {
335 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
336 iowrite32(EE_ENB | dataval, ee_addr);
337 eeprom_delay();
338 iowrite32(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
339 eeprom_delay();
340 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
341 }
342 iowrite32(EE_ENB, ee_addr);
343 eeprom_delay();
344
345 for (i = 16; i > 0; i--) {
346 iowrite32(EE_ENB | EE_SHIFT_CLK, ee_addr);
347 eeprom_delay();
348 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
349 iowrite32(EE_ENB, ee_addr);
350 eeprom_delay();
351 }
352
353 /* Terminate the EEPROM access. */
354 iowrite32(EE_ENB & ~EE_CS, ee_addr);
355 return (tp->flags & HAS_SWAPPED_SEEPROM) ? swab16(retval) : retval;
356}
357
diff --git a/drivers/net/tulip/interrupt.c b/drivers/net/tulip/interrupt.c
new file mode 100644
index 000000000000..afb5cda9d8e1
--- /dev/null
+++ b/drivers/net/tulip/interrupt.c
@@ -0,0 +1,786 @@
1/*
2 drivers/net/tulip/interrupt.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/pci.h>
18#include "tulip.h"
19#include <linux/config.h>
20#include <linux/etherdevice.h>
21
22int tulip_rx_copybreak;
23unsigned int tulip_max_interrupt_work;
24
25#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
26#define MIT_SIZE 15
27#define MIT_TABLE 15 /* We use 0 or max */
28
29static unsigned int mit_table[MIT_SIZE+1] =
30{
31 /* CRS11 21143 hardware Mitigation Control Interrupt
32 We use only RX mitigation we other techniques for
33 TX intr. mitigation.
34
35 31 Cycle Size (timer control)
36 30:27 TX timer in 16 * Cycle size
37 26:24 TX No pkts before Int.
38 23:20 RX timer in Cycle size
39 19:17 RX No pkts before Int.
40 16 Continues Mode (CM)
41 */
42
43 0x0, /* IM disabled */
44 0x80150000, /* RX time = 1, RX pkts = 2, CM = 1 */
45 0x80150000,
46 0x80270000,
47 0x80370000,
48 0x80490000,
49 0x80590000,
50 0x80690000,
51 0x807B0000,
52 0x808B0000,
53 0x809D0000,
54 0x80AD0000,
55 0x80BD0000,
56 0x80CF0000,
57 0x80DF0000,
58// 0x80FF0000 /* RX time = 16, RX pkts = 7, CM = 1 */
59 0x80F10000 /* RX time = 16, RX pkts = 0, CM = 1 */
60};
61#endif
62
63
64int tulip_refill_rx(struct net_device *dev)
65{
66 struct tulip_private *tp = netdev_priv(dev);
67 int entry;
68 int refilled = 0;
69
70 /* Refill the Rx ring buffers. */
71 for (; tp->cur_rx - tp->dirty_rx > 0; tp->dirty_rx++) {
72 entry = tp->dirty_rx % RX_RING_SIZE;
73 if (tp->rx_buffers[entry].skb == NULL) {
74 struct sk_buff *skb;
75 dma_addr_t mapping;
76
77 skb = tp->rx_buffers[entry].skb = dev_alloc_skb(PKT_BUF_SZ);
78 if (skb == NULL)
79 break;
80
81 mapping = pci_map_single(tp->pdev, skb->tail, PKT_BUF_SZ,
82 PCI_DMA_FROMDEVICE);
83 tp->rx_buffers[entry].mapping = mapping;
84
85 skb->dev = dev; /* Mark as being used by this device. */
86 tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
87 refilled++;
88 }
89 tp->rx_ring[entry].status = cpu_to_le32(DescOwned);
90 }
91 if(tp->chip_id == LC82C168) {
92 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) {
93 /* Rx stopped due to out of buffers,
94 * restart it
95 */
96 iowrite32(0x01, tp->base_addr + CSR2);
97 }
98 }
99 return refilled;
100}
101
102#ifdef CONFIG_TULIP_NAPI
103
104void oom_timer(unsigned long data)
105{
106 struct net_device *dev = (struct net_device *)data;
107 netif_rx_schedule(dev);
108}
109
110int tulip_poll(struct net_device *dev, int *budget)
111{
112 struct tulip_private *tp = netdev_priv(dev);
113 int entry = tp->cur_rx % RX_RING_SIZE;
114 int rx_work_limit = *budget;
115 int received = 0;
116
117 if (!netif_running(dev))
118 goto done;
119
120 if (rx_work_limit > dev->quota)
121 rx_work_limit = dev->quota;
122
123#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
124
125/* that one buffer is needed for mit activation; or might be a
126 bug in the ring buffer code; check later -- JHS*/
127
128 if (rx_work_limit >=RX_RING_SIZE) rx_work_limit--;
129#endif
130
131 if (tulip_debug > 4)
132 printk(KERN_DEBUG " In tulip_rx(), entry %d %8.8x.\n", entry,
133 tp->rx_ring[entry].status);
134
135 do {
136 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) {
137 printk(KERN_DEBUG " In tulip_poll(), hardware disappeared.\n");
138 break;
139 }
140 /* Acknowledge current RX interrupt sources. */
141 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5);
142
143
144 /* If we own the next entry, it is a new packet. Send it up. */
145 while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) {
146 s32 status = le32_to_cpu(tp->rx_ring[entry].status);
147
148
149 if (tp->dirty_rx + RX_RING_SIZE == tp->cur_rx)
150 break;
151
152 if (tulip_debug > 5)
153 printk(KERN_DEBUG "%s: In tulip_rx(), entry %d %8.8x.\n",
154 dev->name, entry, status);
155 if (--rx_work_limit < 0)
156 goto not_done;
157
158 if ((status & 0x38008300) != 0x0300) {
159 if ((status & 0x38000300) != 0x0300) {
160 /* Ingore earlier buffers. */
161 if ((status & 0xffff) != 0x7fff) {
162 if (tulip_debug > 1)
163 printk(KERN_WARNING "%s: Oversized Ethernet frame "
164 "spanned multiple buffers, status %8.8x!\n",
165 dev->name, status);
166 tp->stats.rx_length_errors++;
167 }
168 } else if (status & RxDescFatalErr) {
169 /* There was a fatal error. */
170 if (tulip_debug > 2)
171 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
172 dev->name, status);
173 tp->stats.rx_errors++; /* end of a packet.*/
174 if (status & 0x0890) tp->stats.rx_length_errors++;
175 if (status & 0x0004) tp->stats.rx_frame_errors++;
176 if (status & 0x0002) tp->stats.rx_crc_errors++;
177 if (status & 0x0001) tp->stats.rx_fifo_errors++;
178 }
179 } else {
180 /* Omit the four octet CRC from the length. */
181 short pkt_len = ((status >> 16) & 0x7ff) - 4;
182 struct sk_buff *skb;
183
184#ifndef final_version
185 if (pkt_len > 1518) {
186 printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n",
187 dev->name, pkt_len, pkt_len);
188 pkt_len = 1518;
189 tp->stats.rx_length_errors++;
190 }
191#endif
192 /* Check if the packet is long enough to accept without copying
193 to a minimally-sized skbuff. */
194 if (pkt_len < tulip_rx_copybreak
195 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
196 skb->dev = dev;
197 skb_reserve(skb, 2); /* 16 byte align the IP header */
198 pci_dma_sync_single_for_cpu(tp->pdev,
199 tp->rx_buffers[entry].mapping,
200 pkt_len, PCI_DMA_FROMDEVICE);
201#if ! defined(__alpha__)
202 eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->tail,
203 pkt_len, 0);
204 skb_put(skb, pkt_len);
205#else
206 memcpy(skb_put(skb, pkt_len),
207 tp->rx_buffers[entry].skb->tail,
208 pkt_len);
209#endif
210 pci_dma_sync_single_for_device(tp->pdev,
211 tp->rx_buffers[entry].mapping,
212 pkt_len, PCI_DMA_FROMDEVICE);
213 } else { /* Pass up the skb already on the Rx ring. */
214 char *temp = skb_put(skb = tp->rx_buffers[entry].skb,
215 pkt_len);
216
217#ifndef final_version
218 if (tp->rx_buffers[entry].mapping !=
219 le32_to_cpu(tp->rx_ring[entry].buffer1)) {
220 printk(KERN_ERR "%s: Internal fault: The skbuff addresses "
221 "do not match in tulip_rx: %08x vs. %08llx %p / %p.\n",
222 dev->name,
223 le32_to_cpu(tp->rx_ring[entry].buffer1),
224 (unsigned long long)tp->rx_buffers[entry].mapping,
225 skb->head, temp);
226 }
227#endif
228
229 pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping,
230 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
231
232 tp->rx_buffers[entry].skb = NULL;
233 tp->rx_buffers[entry].mapping = 0;
234 }
235 skb->protocol = eth_type_trans(skb, dev);
236
237 netif_receive_skb(skb);
238
239 dev->last_rx = jiffies;
240 tp->stats.rx_packets++;
241 tp->stats.rx_bytes += pkt_len;
242 }
243 received++;
244
245 entry = (++tp->cur_rx) % RX_RING_SIZE;
246 if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/4)
247 tulip_refill_rx(dev);
248
249 }
250
251 /* New ack strategy... irq does not ack Rx any longer
252 hopefully this helps */
253
254 /* Really bad things can happen here... If new packet arrives
255 * and an irq arrives (tx or just due to occasionally unset
256 * mask), it will be acked by irq handler, but new thread
257 * is not scheduled. It is major hole in design.
258 * No idea how to fix this if "playing with fire" will fail
259 * tomorrow (night 011029). If it will not fail, we won
260 * finally: amount of IO did not increase at all. */
261 } while ((ioread32(tp->base_addr + CSR5) & RxIntr));
262
263done:
264
265 #ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
266
267 /* We use this simplistic scheme for IM. It's proven by
268 real life installations. We can have IM enabled
269 continuesly but this would cause unnecessary latency.
270 Unfortunely we can't use all the NET_RX_* feedback here.
271 This would turn on IM for devices that is not contributing
272 to backlog congestion with unnecessary latency.
273
274 We monitor the the device RX-ring and have:
275
276 HW Interrupt Mitigation either ON or OFF.
277
278 ON: More then 1 pkt received (per intr.) OR we are dropping
279 OFF: Only 1 pkt received
280
281 Note. We only use min and max (0, 15) settings from mit_table */
282
283
284 if( tp->flags & HAS_INTR_MITIGATION) {
285 if( received > 1 ) {
286 if( ! tp->mit_on ) {
287 tp->mit_on = 1;
288 iowrite32(mit_table[MIT_TABLE], tp->base_addr + CSR11);
289 }
290 }
291 else {
292 if( tp->mit_on ) {
293 tp->mit_on = 0;
294 iowrite32(0, tp->base_addr + CSR11);
295 }
296 }
297 }
298
299#endif /* CONFIG_TULIP_NAPI_HW_MITIGATION */
300
301 dev->quota -= received;
302 *budget -= received;
303
304 tulip_refill_rx(dev);
305
306 /* If RX ring is not full we are out of memory. */
307 if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL) goto oom;
308
309 /* Remove us from polling list and enable RX intr. */
310
311 netif_rx_complete(dev);
312 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7);
313
314 /* The last op happens after poll completion. Which means the following:
315 * 1. it can race with disabling irqs in irq handler
316 * 2. it can race with dise/enabling irqs in other poll threads
317 * 3. if an irq raised after beginning loop, it will be immediately
318 * triggered here.
319 *
320 * Summarizing: the logic results in some redundant irqs both
321 * due to races in masking and due to too late acking of already
322 * processed irqs. But it must not result in losing events.
323 */
324
325 return 0;
326
327 not_done:
328 if (!received) {
329
330 received = dev->quota; /* Not to happen */
331 }
332 dev->quota -= received;
333 *budget -= received;
334
335 if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/2 ||
336 tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
337 tulip_refill_rx(dev);
338
339 if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL) goto oom;
340
341 return 1;
342
343
344 oom: /* Executed with RX ints disabled */
345
346
347 /* Start timer, stop polling, but do not enable rx interrupts. */
348 mod_timer(&tp->oom_timer, jiffies+1);
349
350 /* Think: timer_pending() was an explicit signature of bug.
351 * Timer can be pending now but fired and completed
352 * before we did netif_rx_complete(). See? We would lose it. */
353
354 /* remove ourselves from the polling list */
355 netif_rx_complete(dev);
356
357 return 0;
358}
359
360#else /* CONFIG_TULIP_NAPI */
361
362static int tulip_rx(struct net_device *dev)
363{
364 struct tulip_private *tp = netdev_priv(dev);
365 int entry = tp->cur_rx % RX_RING_SIZE;
366 int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx;
367 int received = 0;
368
369 if (tulip_debug > 4)
370 printk(KERN_DEBUG " In tulip_rx(), entry %d %8.8x.\n", entry,
371 tp->rx_ring[entry].status);
372 /* If we own the next entry, it is a new packet. Send it up. */
373 while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) {
374 s32 status = le32_to_cpu(tp->rx_ring[entry].status);
375
376 if (tulip_debug > 5)
377 printk(KERN_DEBUG "%s: In tulip_rx(), entry %d %8.8x.\n",
378 dev->name, entry, status);
379 if (--rx_work_limit < 0)
380 break;
381 if ((status & 0x38008300) != 0x0300) {
382 if ((status & 0x38000300) != 0x0300) {
383 /* Ingore earlier buffers. */
384 if ((status & 0xffff) != 0x7fff) {
385 if (tulip_debug > 1)
386 printk(KERN_WARNING "%s: Oversized Ethernet frame "
387 "spanned multiple buffers, status %8.8x!\n",
388 dev->name, status);
389 tp->stats.rx_length_errors++;
390 }
391 } else if (status & RxDescFatalErr) {
392 /* There was a fatal error. */
393 if (tulip_debug > 2)
394 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
395 dev->name, status);
396 tp->stats.rx_errors++; /* end of a packet.*/
397 if (status & 0x0890) tp->stats.rx_length_errors++;
398 if (status & 0x0004) tp->stats.rx_frame_errors++;
399 if (status & 0x0002) tp->stats.rx_crc_errors++;
400 if (status & 0x0001) tp->stats.rx_fifo_errors++;
401 }
402 } else {
403 /* Omit the four octet CRC from the length. */
404 short pkt_len = ((status >> 16) & 0x7ff) - 4;
405 struct sk_buff *skb;
406
407#ifndef final_version
408 if (pkt_len > 1518) {
409 printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n",
410 dev->name, pkt_len, pkt_len);
411 pkt_len = 1518;
412 tp->stats.rx_length_errors++;
413 }
414#endif
415
416 /* Check if the packet is long enough to accept without copying
417 to a minimally-sized skbuff. */
418 if (pkt_len < tulip_rx_copybreak
419 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
420 skb->dev = dev;
421 skb_reserve(skb, 2); /* 16 byte align the IP header */
422 pci_dma_sync_single_for_cpu(tp->pdev,
423 tp->rx_buffers[entry].mapping,
424 pkt_len, PCI_DMA_FROMDEVICE);
425#if ! defined(__alpha__)
426 eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->tail,
427 pkt_len, 0);
428 skb_put(skb, pkt_len);
429#else
430 memcpy(skb_put(skb, pkt_len),
431 tp->rx_buffers[entry].skb->tail,
432 pkt_len);
433#endif
434 pci_dma_sync_single_for_device(tp->pdev,
435 tp->rx_buffers[entry].mapping,
436 pkt_len, PCI_DMA_FROMDEVICE);
437 } else { /* Pass up the skb already on the Rx ring. */
438 char *temp = skb_put(skb = tp->rx_buffers[entry].skb,
439 pkt_len);
440
441#ifndef final_version
442 if (tp->rx_buffers[entry].mapping !=
443 le32_to_cpu(tp->rx_ring[entry].buffer1)) {
444 printk(KERN_ERR "%s: Internal fault: The skbuff addresses "
445 "do not match in tulip_rx: %08x vs. %Lx %p / %p.\n",
446 dev->name,
447 le32_to_cpu(tp->rx_ring[entry].buffer1),
448 (long long)tp->rx_buffers[entry].mapping,
449 skb->head, temp);
450 }
451#endif
452
453 pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping,
454 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
455
456 tp->rx_buffers[entry].skb = NULL;
457 tp->rx_buffers[entry].mapping = 0;
458 }
459 skb->protocol = eth_type_trans(skb, dev);
460
461 netif_rx(skb);
462
463 dev->last_rx = jiffies;
464 tp->stats.rx_packets++;
465 tp->stats.rx_bytes += pkt_len;
466 }
467 received++;
468 entry = (++tp->cur_rx) % RX_RING_SIZE;
469 }
470 return received;
471}
472#endif /* CONFIG_TULIP_NAPI */
473
474static inline unsigned int phy_interrupt (struct net_device *dev)
475{
476#ifdef __hppa__
477 struct tulip_private *tp = netdev_priv(dev);
478 int csr12 = ioread32(tp->base_addr + CSR12) & 0xff;
479
480 if (csr12 != tp->csr12_shadow) {
481 /* ack interrupt */
482 iowrite32(csr12 | 0x02, tp->base_addr + CSR12);
483 tp->csr12_shadow = csr12;
484 /* do link change stuff */
485 spin_lock(&tp->lock);
486 tulip_check_duplex(dev);
487 spin_unlock(&tp->lock);
488 /* clear irq ack bit */
489 iowrite32(csr12 & ~0x02, tp->base_addr + CSR12);
490
491 return 1;
492 }
493#endif
494
495 return 0;
496}
497
498/* The interrupt handler does all of the Rx thread work and cleans up
499 after the Tx thread. */
500irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
501{
502 struct net_device *dev = (struct net_device *)dev_instance;
503 struct tulip_private *tp = netdev_priv(dev);
504 void __iomem *ioaddr = tp->base_addr;
505 int csr5;
506 int missed;
507 int rx = 0;
508 int tx = 0;
509 int oi = 0;
510 int maxrx = RX_RING_SIZE;
511 int maxtx = TX_RING_SIZE;
512 int maxoi = TX_RING_SIZE;
513#ifdef CONFIG_TULIP_NAPI
514 int rxd = 0;
515#else
516 int entry;
517#endif
518 unsigned int work_count = tulip_max_interrupt_work;
519 unsigned int handled = 0;
520
521 /* Let's see whether the interrupt really is for us */
522 csr5 = ioread32(ioaddr + CSR5);
523
524 if (tp->flags & HAS_PHY_IRQ)
525 handled = phy_interrupt (dev);
526
527 if ((csr5 & (NormalIntr|AbnormalIntr)) == 0)
528 return IRQ_RETVAL(handled);
529
530 tp->nir++;
531
532 do {
533
534#ifdef CONFIG_TULIP_NAPI
535
536 if (!rxd && (csr5 & (RxIntr | RxNoBuf))) {
537 rxd++;
538 /* Mask RX intrs and add the device to poll list. */
539 iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7);
540 netif_rx_schedule(dev);
541
542 if (!(csr5&~(AbnormalIntr|NormalIntr|RxPollInt|TPLnkPass)))
543 break;
544 }
545
546 /* Acknowledge the interrupt sources we handle here ASAP
547 the poll function does Rx and RxNoBuf acking */
548
549 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5);
550
551#else
552 /* Acknowledge all of the current interrupt sources ASAP. */
553 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5);
554
555
556 if (csr5 & (RxIntr | RxNoBuf)) {
557 rx += tulip_rx(dev);
558 tulip_refill_rx(dev);
559 }
560
561#endif /* CONFIG_TULIP_NAPI */
562
563 if (tulip_debug > 4)
564 printk(KERN_DEBUG "%s: interrupt csr5=%#8.8x new csr5=%#8.8x.\n",
565 dev->name, csr5, ioread32(ioaddr + CSR5));
566
567
568 if (csr5 & (TxNoBuf | TxDied | TxIntr | TimerInt)) {
569 unsigned int dirty_tx;
570
571 spin_lock(&tp->lock);
572
573 for (dirty_tx = tp->dirty_tx; tp->cur_tx - dirty_tx > 0;
574 dirty_tx++) {
575 int entry = dirty_tx % TX_RING_SIZE;
576 int status = le32_to_cpu(tp->tx_ring[entry].status);
577
578 if (status < 0)
579 break; /* It still has not been Txed */
580
581 /* Check for Rx filter setup frames. */
582 if (tp->tx_buffers[entry].skb == NULL) {
583 /* test because dummy frames not mapped */
584 if (tp->tx_buffers[entry].mapping)
585 pci_unmap_single(tp->pdev,
586 tp->tx_buffers[entry].mapping,
587 sizeof(tp->setup_frame),
588 PCI_DMA_TODEVICE);
589 continue;
590 }
591
592 if (status & 0x8000) {
593 /* There was an major error, log it. */
594#ifndef final_version
595 if (tulip_debug > 1)
596 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
597 dev->name, status);
598#endif
599 tp->stats.tx_errors++;
600 if (status & 0x4104) tp->stats.tx_aborted_errors++;
601 if (status & 0x0C00) tp->stats.tx_carrier_errors++;
602 if (status & 0x0200) tp->stats.tx_window_errors++;
603 if (status & 0x0002) tp->stats.tx_fifo_errors++;
604 if ((status & 0x0080) && tp->full_duplex == 0)
605 tp->stats.tx_heartbeat_errors++;
606 } else {
607 tp->stats.tx_bytes +=
608 tp->tx_buffers[entry].skb->len;
609 tp->stats.collisions += (status >> 3) & 15;
610 tp->stats.tx_packets++;
611 }
612
613 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
614 tp->tx_buffers[entry].skb->len,
615 PCI_DMA_TODEVICE);
616
617 /* Free the original skb. */
618 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
619 tp->tx_buffers[entry].skb = NULL;
620 tp->tx_buffers[entry].mapping = 0;
621 tx++;
622 }
623
624#ifndef final_version
625 if (tp->cur_tx - dirty_tx > TX_RING_SIZE) {
626 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
627 dev->name, dirty_tx, tp->cur_tx);
628 dirty_tx += TX_RING_SIZE;
629 }
630#endif
631
632 if (tp->cur_tx - dirty_tx < TX_RING_SIZE - 2)
633 netif_wake_queue(dev);
634
635 tp->dirty_tx = dirty_tx;
636 if (csr5 & TxDied) {
637 if (tulip_debug > 2)
638 printk(KERN_WARNING "%s: The transmitter stopped."
639 " CSR5 is %x, CSR6 %x, new CSR6 %x.\n",
640 dev->name, csr5, ioread32(ioaddr + CSR6), tp->csr6);
641 tulip_restart_rxtx(tp);
642 }
643 spin_unlock(&tp->lock);
644 }
645
646 /* Log errors. */
647 if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */
648 if (csr5 == 0xffffffff)
649 break;
650 if (csr5 & TxJabber) tp->stats.tx_errors++;
651 if (csr5 & TxFIFOUnderflow) {
652 if ((tp->csr6 & 0xC000) != 0xC000)
653 tp->csr6 += 0x4000; /* Bump up the Tx threshold */
654 else
655 tp->csr6 |= 0x00200000; /* Store-n-forward. */
656 /* Restart the transmit process. */
657 tulip_restart_rxtx(tp);
658 iowrite32(0, ioaddr + CSR1);
659 }
660 if (csr5 & (RxDied | RxNoBuf)) {
661 if (tp->flags & COMET_MAC_ADDR) {
662 iowrite32(tp->mc_filter[0], ioaddr + 0xAC);
663 iowrite32(tp->mc_filter[1], ioaddr + 0xB0);
664 }
665 }
666 if (csr5 & RxDied) { /* Missed a Rx frame. */
667 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
668 tp->stats.rx_errors++;
669 tulip_start_rxtx(tp);
670 }
671 /*
672 * NB: t21142_lnk_change() does a del_timer_sync(), so be careful if this
673 * call is ever done under the spinlock
674 */
675 if (csr5 & (TPLnkPass | TPLnkFail | 0x08000000)) {
676 if (tp->link_change)
677 (tp->link_change)(dev, csr5);
678 }
679 if (csr5 & SytemError) {
680 int error = (csr5 >> 23) & 7;
681 /* oops, we hit a PCI error. The code produced corresponds
682 * to the reason:
683 * 0 - parity error
684 * 1 - master abort
685 * 2 - target abort
686 * Note that on parity error, we should do a software reset
687 * of the chip to get it back into a sane state (according
688 * to the 21142/3 docs that is).
689 * -- rmk
690 */
691 printk(KERN_ERR "%s: (%lu) System Error occurred (%d)\n",
692 dev->name, tp->nir, error);
693 }
694 /* Clear all error sources, included undocumented ones! */
695 iowrite32(0x0800f7ba, ioaddr + CSR5);
696 oi++;
697 }
698 if (csr5 & TimerInt) {
699
700 if (tulip_debug > 2)
701 printk(KERN_ERR "%s: Re-enabling interrupts, %8.8x.\n",
702 dev->name, csr5);
703 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
704 tp->ttimer = 0;
705 oi++;
706 }
707 if (tx > maxtx || rx > maxrx || oi > maxoi) {
708 if (tulip_debug > 1)
709 printk(KERN_WARNING "%s: Too much work during an interrupt, "
710 "csr5=0x%8.8x. (%lu) (%d,%d,%d)\n", dev->name, csr5, tp->nir, tx, rx, oi);
711
712 /* Acknowledge all interrupt sources. */
713 iowrite32(0x8001ffff, ioaddr + CSR5);
714 if (tp->flags & HAS_INTR_MITIGATION) {
715 /* Josip Loncaric at ICASE did extensive experimentation
716 to develop a good interrupt mitigation setting.*/
717 iowrite32(0x8b240000, ioaddr + CSR11);
718 } else if (tp->chip_id == LC82C168) {
719 /* the LC82C168 doesn't have a hw timer.*/
720 iowrite32(0x00, ioaddr + CSR7);
721 mod_timer(&tp->timer, RUN_AT(HZ/50));
722 } else {
723 /* Mask all interrupting sources, set timer to
724 re-enable. */
725 iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);
726 iowrite32(0x0012, ioaddr + CSR11);
727 }
728 break;
729 }
730
731 work_count--;
732 if (work_count == 0)
733 break;
734
735 csr5 = ioread32(ioaddr + CSR5);
736
737#ifdef CONFIG_TULIP_NAPI
738 if (rxd)
739 csr5 &= ~RxPollInt;
740 } while ((csr5 & (TxNoBuf |
741 TxDied |
742 TxIntr |
743 TimerInt |
744 /* Abnormal intr. */
745 RxDied |
746 TxFIFOUnderflow |
747 TxJabber |
748 TPLnkFail |
749 SytemError )) != 0);
750#else
751 } while ((csr5 & (NormalIntr|AbnormalIntr)) != 0);
752
753 tulip_refill_rx(dev);
754
755 /* check if the card is in suspend mode */
756 entry = tp->dirty_rx % RX_RING_SIZE;
757 if (tp->rx_buffers[entry].skb == NULL) {
758 if (tulip_debug > 1)
759 printk(KERN_WARNING "%s: in rx suspend mode: (%lu) (tp->cur_rx = %u, ttimer = %d, rx = %d) go/stay in suspend mode\n", dev->name, tp->nir, tp->cur_rx, tp->ttimer, rx);
760 if (tp->chip_id == LC82C168) {
761 iowrite32(0x00, ioaddr + CSR7);
762 mod_timer(&tp->timer, RUN_AT(HZ/50));
763 } else {
764 if (tp->ttimer == 0 || (ioread32(ioaddr + CSR11) & 0xffff) == 0) {
765 if (tulip_debug > 1)
766 printk(KERN_WARNING "%s: in rx suspend mode: (%lu) set timer\n", dev->name, tp->nir);
767 iowrite32(tulip_tbl[tp->chip_id].valid_intrs | TimerInt,
768 ioaddr + CSR7);
769 iowrite32(TimerInt, ioaddr + CSR5);
770 iowrite32(12, ioaddr + CSR11);
771 tp->ttimer = 1;
772 }
773 }
774 }
775#endif /* CONFIG_TULIP_NAPI */
776
777 if ((missed = ioread32(ioaddr + CSR8) & 0x1ffff)) {
778 tp->stats.rx_dropped += missed & 0x10000 ? 0x10000 : missed;
779 }
780
781 if (tulip_debug > 4)
782 printk(KERN_DEBUG "%s: exiting interrupt, csr5=%#4.4x.\n",
783 dev->name, ioread32(ioaddr + CSR5));
784
785 return IRQ_HANDLED;
786}
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c
new file mode 100644
index 000000000000..edae09a4b021
--- /dev/null
+++ b/drivers/net/tulip/media.c
@@ -0,0 +1,562 @@
1/*
2 drivers/net/tulip/media.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/kernel.h>
18#include <linux/mii.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include "tulip.h"
23
24
25/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
26 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
27 "overclocking" issues or future 66Mhz PCI. */
28#define mdio_delay() ioread32(mdio_addr)
29
30/* Read and write the MII registers using software-generated serial
31 MDIO protocol. It is just different enough from the EEPROM protocol
32 to not share code. The maxium data clock rate is 2.5 Mhz. */
33#define MDIO_SHIFT_CLK 0x10000
34#define MDIO_DATA_WRITE0 0x00000
35#define MDIO_DATA_WRITE1 0x20000
36#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
37#define MDIO_ENB_IN 0x40000
38#define MDIO_DATA_READ 0x80000
39
40static const unsigned char comet_miireg2offset[32] = {
41 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
42 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
43
44
45/* MII transceiver control section.
46 Read and write the MII registers using software-generated serial
47 MDIO protocol. See the MII specifications or DP83840A data sheet
48 for details. */
49
50int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
51{
52 struct tulip_private *tp = netdev_priv(dev);
53 int i;
54 int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
55 int retval = 0;
56 void __iomem *ioaddr = tp->base_addr;
57 void __iomem *mdio_addr = ioaddr + CSR9;
58 unsigned long flags;
59
60 if (location & ~0x1f)
61 return 0xffff;
62
63 if (tp->chip_id == COMET && phy_id == 30) {
64 if (comet_miireg2offset[location])
65 return ioread32(ioaddr + comet_miireg2offset[location]);
66 return 0xffff;
67 }
68
69 spin_lock_irqsave(&tp->mii_lock, flags);
70 if (tp->chip_id == LC82C168) {
71 int i = 1000;
72 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
73 ioread32(ioaddr + 0xA0);
74 ioread32(ioaddr + 0xA0);
75 while (--i > 0) {
76 barrier();
77 if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
78 break;
79 }
80 spin_unlock_irqrestore(&tp->mii_lock, flags);
81 return retval & 0xffff;
82 }
83
84 if(tp->chip_id == ULI526X && tp->revision >= 0x40) {
85 int value;
86 int i = 1000;
87
88 value = ioread32(ioaddr + CSR9);
89 iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
90
91 value = (phy_id << 21) | (location << 16) | 0x08000000;
92 iowrite32(value, ioaddr + CSR10);
93
94 while(--i > 0) {
95 mdio_delay();
96 if(ioread32(ioaddr + CSR10) & 0x10000000)
97 break;
98 }
99 retval = ioread32(ioaddr + CSR10);
100 spin_unlock_irqrestore(&tp->mii_lock, flags);
101 return retval & 0xFFFF;
102 }
103 /* Establish sync by sending at least 32 logic ones. */
104 for (i = 32; i >= 0; i--) {
105 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
106 mdio_delay();
107 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
108 mdio_delay();
109 }
110 /* Shift the read command bits out. */
111 for (i = 15; i >= 0; i--) {
112 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
113
114 iowrite32(MDIO_ENB | dataval, mdio_addr);
115 mdio_delay();
116 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
117 mdio_delay();
118 }
119 /* Read the two transition, 16 data, and wire-idle bits. */
120 for (i = 19; i > 0; i--) {
121 iowrite32(MDIO_ENB_IN, mdio_addr);
122 mdio_delay();
123 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
124 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
125 mdio_delay();
126 }
127
128 spin_unlock_irqrestore(&tp->mii_lock, flags);
129 return (retval>>1) & 0xffff;
130}
131
132void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
133{
134 struct tulip_private *tp = netdev_priv(dev);
135 int i;
136 int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
137 void __iomem *ioaddr = tp->base_addr;
138 void __iomem *mdio_addr = ioaddr + CSR9;
139 unsigned long flags;
140
141 if (location & ~0x1f)
142 return;
143
144 if (tp->chip_id == COMET && phy_id == 30) {
145 if (comet_miireg2offset[location])
146 iowrite32(val, ioaddr + comet_miireg2offset[location]);
147 return;
148 }
149
150 spin_lock_irqsave(&tp->mii_lock, flags);
151 if (tp->chip_id == LC82C168) {
152 int i = 1000;
153 iowrite32(cmd, ioaddr + 0xA0);
154 do {
155 barrier();
156 if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
157 break;
158 } while (--i > 0);
159 spin_unlock_irqrestore(&tp->mii_lock, flags);
160 return;
161 }
162 if (tp->chip_id == ULI526X && tp->revision >= 0x40) {
163 int value;
164 int i = 1000;
165
166 value = ioread32(ioaddr + CSR9);
167 iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
168
169 value = (phy_id << 21) | (location << 16) | 0x04000000 | (val & 0xFFFF);
170 iowrite32(value, ioaddr + CSR10);
171
172 while(--i > 0) {
173 if (ioread32(ioaddr + CSR10) & 0x10000000)
174 break;
175 }
176 spin_unlock_irqrestore(&tp->mii_lock, flags);
177 }
178
179 /* Establish sync by sending 32 logic ones. */
180 for (i = 32; i >= 0; i--) {
181 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
182 mdio_delay();
183 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
184 mdio_delay();
185 }
186 /* Shift the command bits out. */
187 for (i = 31; i >= 0; i--) {
188 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
189 iowrite32(MDIO_ENB | dataval, mdio_addr);
190 mdio_delay();
191 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
192 mdio_delay();
193 }
194 /* Clear out extra bits. */
195 for (i = 2; i > 0; i--) {
196 iowrite32(MDIO_ENB_IN, mdio_addr);
197 mdio_delay();
198 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
199 mdio_delay();
200 }
201
202 spin_unlock_irqrestore(&tp->mii_lock, flags);
203}
204
205
206/* Set up the transceiver control registers for the selected media type. */
207void tulip_select_media(struct net_device *dev, int startup)
208{
209 struct tulip_private *tp = netdev_priv(dev);
210 void __iomem *ioaddr = tp->base_addr;
211 struct mediatable *mtable = tp->mtable;
212 u32 new_csr6;
213 int i;
214
215 if (mtable) {
216 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
217 unsigned char *p = mleaf->leafdata;
218 switch (mleaf->type) {
219 case 0: /* 21140 non-MII xcvr. */
220 if (tulip_debug > 1)
221 printk(KERN_DEBUG "%s: Using a 21140 non-MII transceiver"
222 " with control setting %2.2x.\n",
223 dev->name, p[1]);
224 dev->if_port = p[0];
225 if (startup)
226 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
227 iowrite32(p[1], ioaddr + CSR12);
228 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
229 break;
230 case 2: case 4: {
231 u16 setup[5];
232 u32 csr13val, csr14val, csr15dir, csr15val;
233 for (i = 0; i < 5; i++)
234 setup[i] = get_u16(&p[i*2 + 1]);
235
236 dev->if_port = p[0] & MEDIA_MASK;
237 if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
238 tp->full_duplex = 1;
239
240 if (startup && mtable->has_reset) {
241 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
242 unsigned char *rst = rleaf->leafdata;
243 if (tulip_debug > 1)
244 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
245 dev->name);
246 for (i = 0; i < rst[0]; i++)
247 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
248 }
249 if (tulip_debug > 1)
250 printk(KERN_DEBUG "%s: 21143 non-MII %s transceiver control "
251 "%4.4x/%4.4x.\n",
252 dev->name, medianame[dev->if_port], setup[0], setup[1]);
253 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
254 csr13val = setup[0];
255 csr14val = setup[1];
256 csr15dir = (setup[3]<<16) | setup[2];
257 csr15val = (setup[4]<<16) | setup[2];
258 iowrite32(0, ioaddr + CSR13);
259 iowrite32(csr14val, ioaddr + CSR14);
260 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
261 iowrite32(csr15val, ioaddr + CSR15); /* Data */
262 iowrite32(csr13val, ioaddr + CSR13);
263 } else {
264 csr13val = 1;
265 csr14val = 0;
266 csr15dir = (setup[0]<<16) | 0x0008;
267 csr15val = (setup[1]<<16) | 0x0008;
268 if (dev->if_port <= 4)
269 csr14val = t21142_csr14[dev->if_port];
270 if (startup) {
271 iowrite32(0, ioaddr + CSR13);
272 iowrite32(csr14val, ioaddr + CSR14);
273 }
274 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
275 iowrite32(csr15val, ioaddr + CSR15); /* Data */
276 if (startup) iowrite32(csr13val, ioaddr + CSR13);
277 }
278 if (tulip_debug > 1)
279 printk(KERN_DEBUG "%s: Setting CSR15 to %8.8x/%8.8x.\n",
280 dev->name, csr15dir, csr15val);
281 if (mleaf->type == 4)
282 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
283 else
284 new_csr6 = 0x82420000;
285 break;
286 }
287 case 1: case 3: {
288 int phy_num = p[0];
289 int init_length = p[1];
290 u16 *misc_info, tmp_info;
291
292 dev->if_port = 11;
293 new_csr6 = 0x020E0000;
294 if (mleaf->type == 3) { /* 21142 */
295 u16 *init_sequence = (u16*)(p+2);
296 u16 *reset_sequence = &((u16*)(p+3))[init_length];
297 int reset_length = p[2 + init_length*2];
298 misc_info = reset_sequence + reset_length;
299 if (startup)
300 for (i = 0; i < reset_length; i++)
301 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
302 for (i = 0; i < init_length; i++)
303 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
304 } else {
305 u8 *init_sequence = p + 2;
306 u8 *reset_sequence = p + 3 + init_length;
307 int reset_length = p[2 + init_length];
308 misc_info = (u16*)(reset_sequence + reset_length);
309 if (startup) {
310 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
311 for (i = 0; i < reset_length; i++)
312 iowrite32(reset_sequence[i], ioaddr + CSR12);
313 }
314 for (i = 0; i < init_length; i++)
315 iowrite32(init_sequence[i], ioaddr + CSR12);
316 }
317 tmp_info = get_u16(&misc_info[1]);
318 if (tmp_info)
319 tp->advertising[phy_num] = tmp_info | 1;
320 if (tmp_info && startup < 2) {
321 if (tp->mii_advertise == 0)
322 tp->mii_advertise = tp->advertising[phy_num];
323 if (tulip_debug > 1)
324 printk(KERN_DEBUG "%s: Advertising %4.4x on MII %d.\n",
325 dev->name, tp->mii_advertise, tp->phys[phy_num]);
326 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
327 }
328 break;
329 }
330 case 5: case 6: {
331 u16 setup[5];
332
333 new_csr6 = 0; /* FIXME */
334
335 for (i = 0; i < 5; i++)
336 setup[i] = get_u16(&p[i*2 + 1]);
337
338 if (startup && mtable->has_reset) {
339 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
340 unsigned char *rst = rleaf->leafdata;
341 if (tulip_debug > 1)
342 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
343 dev->name);
344 for (i = 0; i < rst[0]; i++)
345 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
346 }
347
348 break;
349 }
350 default:
351 printk(KERN_DEBUG "%s: Invalid media table selection %d.\n",
352 dev->name, mleaf->type);
353 new_csr6 = 0x020E0000;
354 }
355 if (tulip_debug > 1)
356 printk(KERN_DEBUG "%s: Using media type %s, CSR12 is %2.2x.\n",
357 dev->name, medianame[dev->if_port],
358 ioread32(ioaddr + CSR12) & 0xff);
359 } else if (tp->chip_id == LC82C168) {
360 if (startup && ! tp->medialock)
361 dev->if_port = tp->mii_cnt ? 11 : 0;
362 if (tulip_debug > 1)
363 printk(KERN_DEBUG "%s: PNIC PHY status is %3.3x, media %s.\n",
364 dev->name, ioread32(ioaddr + 0xB8), medianame[dev->if_port]);
365 if (tp->mii_cnt) {
366 new_csr6 = 0x810C0000;
367 iowrite32(0x0001, ioaddr + CSR15);
368 iowrite32(0x0201B07A, ioaddr + 0xB8);
369 } else if (startup) {
370 /* Start with 10mbps to do autonegotiation. */
371 iowrite32(0x32, ioaddr + CSR12);
372 new_csr6 = 0x00420000;
373 iowrite32(0x0001B078, ioaddr + 0xB8);
374 iowrite32(0x0201B078, ioaddr + 0xB8);
375 } else if (dev->if_port == 3 || dev->if_port == 5) {
376 iowrite32(0x33, ioaddr + CSR12);
377 new_csr6 = 0x01860000;
378 /* Trigger autonegotiation. */
379 iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
380 } else {
381 iowrite32(0x32, ioaddr + CSR12);
382 new_csr6 = 0x00420000;
383 iowrite32(0x1F078, ioaddr + 0xB8);
384 }
385 } else { /* Unknown chip type with no media table. */
386 if (tp->default_port == 0)
387 dev->if_port = tp->mii_cnt ? 11 : 3;
388 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
389 new_csr6 = 0x020E0000;
390 } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
391 new_csr6 = 0x02860000;
392 } else
393 new_csr6 = 0x03860000;
394 if (tulip_debug > 1)
395 printk(KERN_DEBUG "%s: No media description table, assuming "
396 "%s transceiver, CSR12 %2.2x.\n",
397 dev->name, medianame[dev->if_port],
398 ioread32(ioaddr + CSR12));
399 }
400
401 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
402 return;
403}
404
405/*
406 Check the MII negotiated duplex and change the CSR6 setting if
407 required.
408 Return 0 if everything is OK.
409 Return < 0 if the transceiver is missing or has no link beat.
410 */
411int tulip_check_duplex(struct net_device *dev)
412{
413 struct tulip_private *tp = netdev_priv(dev);
414 unsigned int bmsr, lpa, negotiated, new_csr6;
415
416 bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
417 lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
418 if (tulip_debug > 1)
419 printk(KERN_INFO "%s: MII status %4.4x, Link partner report "
420 "%4.4x.\n", dev->name, bmsr, lpa);
421 if (bmsr == 0xffff)
422 return -2;
423 if ((bmsr & BMSR_LSTATUS) == 0) {
424 int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
425 if ((new_bmsr & BMSR_LSTATUS) == 0) {
426 if (tulip_debug > 1)
427 printk(KERN_INFO "%s: No link beat on the MII interface,"
428 " status %4.4x.\n", dev->name, new_bmsr);
429 return -1;
430 }
431 }
432 negotiated = lpa & tp->advertising[0];
433 tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
434
435 new_csr6 = tp->csr6;
436
437 if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
438 else new_csr6 |= TxThreshold;
439 if (tp->full_duplex) new_csr6 |= FullDuplex;
440 else new_csr6 &= ~FullDuplex;
441
442 if (new_csr6 != tp->csr6) {
443 tp->csr6 = new_csr6;
444 tulip_restart_rxtx(tp);
445
446 if (tulip_debug > 0)
447 printk(KERN_INFO "%s: Setting %s-duplex based on MII"
448 "#%d link partner capability of %4.4x.\n",
449 dev->name, tp->full_duplex ? "full" : "half",
450 tp->phys[0], lpa);
451 return 1;
452 }
453
454 return 0;
455}
456
457void __devinit tulip_find_mii (struct net_device *dev, int board_idx)
458{
459 struct tulip_private *tp = netdev_priv(dev);
460 int phyn, phy_idx = 0;
461 int mii_reg0;
462 int mii_advert;
463 unsigned int to_advert, new_bmcr, ane_switch;
464
465 /* Find the connected MII xcvrs.
466 Doing this in open() would allow detecting external xcvrs later,
467 but takes much time. */
468 for (phyn = 1; phyn <= 32 && phy_idx < sizeof (tp->phys); phyn++) {
469 int phy = phyn & 0x1f;
470 int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
471 if ((mii_status & 0x8301) == 0x8001 ||
472 ((mii_status & BMSR_100BASE4) == 0
473 && (mii_status & 0x7800) != 0)) {
474 /* preserve Becker logic, gain indentation level */
475 } else {
476 continue;
477 }
478
479 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
480 mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
481 ane_switch = 0;
482
483 /* if not advertising at all, gen an
484 * advertising value from the capability
485 * bits in BMSR
486 */
487 if ((mii_advert & ADVERTISE_ALL) == 0) {
488 unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
489 mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
490 }
491
492 if (tp->mii_advertise) {
493 tp->advertising[phy_idx] =
494 to_advert = tp->mii_advertise;
495 } else if (tp->advertising[phy_idx]) {
496 to_advert = tp->advertising[phy_idx];
497 } else {
498 tp->advertising[phy_idx] =
499 tp->mii_advertise =
500 to_advert = mii_advert;
501 }
502
503 tp->phys[phy_idx++] = phy;
504
505 printk (KERN_INFO "tulip%d: MII transceiver #%d "
506 "config %4.4x status %4.4x advertising %4.4x.\n",
507 board_idx, phy, mii_reg0, mii_status, mii_advert);
508
509 /* Fixup for DLink with miswired PHY. */
510 if (mii_advert != to_advert) {
511 printk (KERN_DEBUG "tulip%d: Advertising %4.4x on PHY %d,"
512 " previously advertising %4.4x.\n",
513 board_idx, to_advert, phy, mii_advert);
514 tulip_mdio_write (dev, phy, 4, to_advert);
515 }
516
517 /* Enable autonegotiation: some boards default to off. */
518 if (tp->default_port == 0) {
519 new_bmcr = mii_reg0 | BMCR_ANENABLE;
520 if (new_bmcr != mii_reg0) {
521 new_bmcr |= BMCR_ANRESTART;
522 ane_switch = 1;
523 }
524 }
525 /* ...or disable nway, if forcing media */
526 else {
527 new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
528 if (new_bmcr != mii_reg0)
529 ane_switch = 1;
530 }
531
532 /* clear out bits we never want at this point */
533 new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
534 BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
535 BMCR_RESET);
536
537 if (tp->full_duplex)
538 new_bmcr |= BMCR_FULLDPLX;
539 if (tulip_media_cap[tp->default_port] & MediaIs100)
540 new_bmcr |= BMCR_SPEED100;
541
542 if (new_bmcr != mii_reg0) {
543 /* some phys need the ANE switch to
544 * happen before forced media settings
545 * will "take." However, we write the
546 * same value twice in order not to
547 * confuse the sane phys.
548 */
549 if (ane_switch) {
550 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
551 udelay (10);
552 }
553 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
554 }
555 }
556 tp->mii_cnt = phy_idx;
557 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
558 printk (KERN_INFO "tulip%d: ***WARNING***: No MII transceiver found!\n",
559 board_idx);
560 tp->phys[0] = 1;
561 }
562}
diff --git a/drivers/net/tulip/pnic.c b/drivers/net/tulip/pnic.c
new file mode 100644
index 000000000000..d9980bde7508
--- /dev/null
+++ b/drivers/net/tulip/pnic.c
@@ -0,0 +1,172 @@
1/*
2 drivers/net/tulip/pnic.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include "tulip.h"
20
21
22void pnic_do_nway(struct net_device *dev)
23{
24 struct tulip_private *tp = netdev_priv(dev);
25 void __iomem *ioaddr = tp->base_addr;
26 u32 phy_reg = ioread32(ioaddr + 0xB8);
27 u32 new_csr6 = tp->csr6 & ~0x40C40200;
28
29 if (phy_reg & 0x78000000) { /* Ignore baseT4 */
30 if (phy_reg & 0x20000000) dev->if_port = 5;
31 else if (phy_reg & 0x40000000) dev->if_port = 3;
32 else if (phy_reg & 0x10000000) dev->if_port = 4;
33 else if (phy_reg & 0x08000000) dev->if_port = 0;
34 tp->nwayset = 1;
35 new_csr6 = (dev->if_port & 1) ? 0x01860000 : 0x00420000;
36 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12);
37 if (dev->if_port & 1)
38 iowrite32(0x1F868, ioaddr + 0xB8);
39 if (phy_reg & 0x30000000) {
40 tp->full_duplex = 1;
41 new_csr6 |= 0x00000200;
42 }
43 if (tulip_debug > 1)
44 printk(KERN_DEBUG "%s: PNIC autonegotiated status %8.8x, %s.\n",
45 dev->name, phy_reg, medianame[dev->if_port]);
46 if (tp->csr6 != new_csr6) {
47 tp->csr6 = new_csr6;
48 /* Restart Tx */
49 tulip_restart_rxtx(tp);
50 dev->trans_start = jiffies;
51 }
52 }
53}
54
55void pnic_lnk_change(struct net_device *dev, int csr5)
56{
57 struct tulip_private *tp = netdev_priv(dev);
58 void __iomem *ioaddr = tp->base_addr;
59 int phy_reg = ioread32(ioaddr + 0xB8);
60
61 if (tulip_debug > 1)
62 printk(KERN_DEBUG "%s: PNIC link changed state %8.8x, CSR5 %8.8x.\n",
63 dev->name, phy_reg, csr5);
64 if (ioread32(ioaddr + CSR5) & TPLnkFail) {
65 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7);
66 /* If we use an external MII, then we mustn't use the
67 * internal negotiation.
68 */
69 if (tulip_media_cap[dev->if_port] & MediaIsMII)
70 return;
71 if (! tp->nwayset || jiffies - dev->trans_start > 1*HZ) {
72 tp->csr6 = 0x00420000 | (tp->csr6 & 0x0000fdff);
73 iowrite32(tp->csr6, ioaddr + CSR6);
74 iowrite32(0x30, ioaddr + CSR12);
75 iowrite32(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */
76 dev->trans_start = jiffies;
77 }
78 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) {
79 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
80 spin_lock(&tp->lock);
81 tulip_check_duplex(dev);
82 spin_unlock(&tp->lock);
83 } else {
84 pnic_do_nway(dev);
85 }
86 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7);
87 }
88}
89
90void pnic_timer(unsigned long data)
91{
92 struct net_device *dev = (struct net_device *)data;
93 struct tulip_private *tp = netdev_priv(dev);
94 void __iomem *ioaddr = tp->base_addr;
95 int next_tick = 60*HZ;
96
97 if(!ioread32(ioaddr + CSR7)) {
98 /* the timer was called due to a work overflow
99 * in the interrupt handler. Skip the connection
100 * checks, the nic is definitively speaking with
101 * his link partner.
102 */
103 goto too_good_connection;
104 }
105
106 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
107 spin_lock_irq(&tp->lock);
108 if (tulip_check_duplex(dev) > 0)
109 next_tick = 3*HZ;
110 spin_unlock_irq(&tp->lock);
111 } else {
112 int csr12 = ioread32(ioaddr + CSR12);
113 int new_csr6 = tp->csr6 & ~0x40C40200;
114 int phy_reg = ioread32(ioaddr + 0xB8);
115 int csr5 = ioread32(ioaddr + CSR5);
116
117 if (tulip_debug > 1)
118 printk(KERN_DEBUG "%s: PNIC timer PHY status %8.8x, %s "
119 "CSR5 %8.8x.\n",
120 dev->name, phy_reg, medianame[dev->if_port], csr5);
121 if (phy_reg & 0x04000000) { /* Remote link fault */
122 iowrite32(0x0201F078, ioaddr + 0xB8);
123 next_tick = 1*HZ;
124 tp->nwayset = 0;
125 } else if (phy_reg & 0x78000000) { /* Ignore baseT4 */
126 pnic_do_nway(dev);
127 next_tick = 60*HZ;
128 } else if (csr5 & TPLnkFail) { /* 100baseTx link beat */
129 if (tulip_debug > 1)
130 printk(KERN_DEBUG "%s: %s link beat failed, CSR12 %4.4x, "
131 "CSR5 %8.8x, PHY %3.3x.\n",
132 dev->name, medianame[dev->if_port], csr12,
133 ioread32(ioaddr + CSR5), ioread32(ioaddr + 0xB8));
134 next_tick = 3*HZ;
135 if (tp->medialock) {
136 } else if (tp->nwayset && (dev->if_port & 1)) {
137 next_tick = 1*HZ;
138 } else if (dev->if_port == 0) {
139 dev->if_port = 3;
140 iowrite32(0x33, ioaddr + CSR12);
141 new_csr6 = 0x01860000;
142 iowrite32(0x1F868, ioaddr + 0xB8);
143 } else {
144 dev->if_port = 0;
145 iowrite32(0x32, ioaddr + CSR12);
146 new_csr6 = 0x00420000;
147 iowrite32(0x1F078, ioaddr + 0xB8);
148 }
149 if (tp->csr6 != new_csr6) {
150 tp->csr6 = new_csr6;
151 /* Restart Tx */
152 tulip_restart_rxtx(tp);
153 dev->trans_start = jiffies;
154 if (tulip_debug > 1)
155 printk(KERN_INFO "%s: Changing PNIC configuration to %s "
156 "%s-duplex, CSR6 %8.8x.\n",
157 dev->name, medianame[dev->if_port],
158 tp->full_duplex ? "full" : "half", new_csr6);
159 }
160 }
161 }
162too_good_connection:
163 mod_timer(&tp->timer, RUN_AT(next_tick));
164 if(!ioread32(ioaddr + CSR7)) {
165 if (tulip_debug > 1)
166 printk(KERN_INFO "%s: sw timer wakeup.\n", dev->name);
167 disable_irq(dev->irq);
168 tulip_refill_rx(dev);
169 enable_irq(dev->irq);
170 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
171 }
172}
diff --git a/drivers/net/tulip/pnic2.c b/drivers/net/tulip/pnic2.c
new file mode 100644
index 000000000000..55f4a9a631bc
--- /dev/null
+++ b/drivers/net/tulip/pnic2.c
@@ -0,0 +1,407 @@
1/*
2 drivers/net/tulip/pnic2.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7 Modified to hep support PNIC_II by Kevin B. Hendricks
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License, incorporated herein by reference.
11
12 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
13 for more information on this driver, or visit the project
14 Web page at http://sourceforge.net/projects/tulip/
15
16*/
17
18
19/* Understanding the PNIC_II - everything is this file is based
20 * on the PNIC_II_PDF datasheet which is sorely lacking in detail
21 *
22 * As I understand things, here are the registers and bits that
23 * explain the masks and constants used in this file that are
24 * either different from the 21142/3 or important for basic operation.
25 *
26 *
27 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
28 * -----
29 * Bit 24 - SCR
30 * Bit 23 - PCS
31 * Bit 22 - TTM (Trasmit Threshold Mode)
32 * Bit 18 - Port Select
33 * Bit 13 - Start - 1, Stop - 0 Transmissions
34 * Bit 11:10 - Loop Back Operation Mode
35 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
36 * Bit 1 - Start - 1, Stop - 0 Receive
37 *
38 *
39 * CSR 14 (mask = 0xfff0ee39 of bits not to change)
40 * ------
41 * Bit 19 - PAUSE-Pause
42 * Bit 18 - Advertise T4
43 * Bit 17 - Advertise 100baseTx-FD
44 * Bit 16 - Advertise 100baseTx-HD
45 * Bit 12 - LTE - Link Test Enable
46 * Bit 7 - ANE - Auto Negotiate Enable
47 * Bit 6 - HDE - Advertise 10baseT-HD
48 * Bit 2 - Reset to Power down - kept as 1 for normal operation
49 * Bit 1 - Loop Back enable for 10baseT MCC
50 *
51 *
52 * CSR 12
53 * ------
54 * Bit 25 - Partner can do T4
55 * Bit 24 - Partner can do 100baseTx-FD
56 * Bit 23 - Partner can do 100baseTx-HD
57 * Bit 22 - Partner can do 10baseT-FD
58 * Bit 21 - Partner can do 10baseT-HD
59 * Bit 15 - LPN is 1 if all above bits are valid other wise 0
60 * Bit 14:12 - autonegotiation state (write 001 to start autonegotiate)
61 * Bit 3 - Autopolarity state
62 * Bit 2 - LS10B - link state of 10baseT 0 - good, 1 - failed
63 * Bit 1 - LS100B - link state of 100baseT 0 - good, 1- faild
64 *
65 *
66 * Data Port Selection Info
67 *-------------------------
68 *
69 * CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> MODE/PORT
70 * 1 0 0 (X) 0 (X) 1 NWAY
71 * 0 0 1 0 (X) 0 10baseT
72 * 0 1 0 1 1 (X) 100baseT
73 *
74 *
75 */
76
77
78
79#include <linux/pci.h>
80#include "tulip.h"
81#include <linux/delay.h>
82
83
84void pnic2_timer(unsigned long data)
85{
86 struct net_device *dev = (struct net_device *)data;
87 struct tulip_private *tp = netdev_priv(dev);
88 void __iomem *ioaddr = tp->base_addr;
89 int next_tick = 60*HZ;
90
91 if (tulip_debug > 3)
92 printk(KERN_INFO"%s: PNIC2 negotiation status %8.8x.\n",
93 dev->name,ioread32(ioaddr + CSR12));
94
95 if (next_tick) {
96 mod_timer(&tp->timer, RUN_AT(next_tick));
97 }
98}
99
100
101void pnic2_start_nway(struct net_device *dev)
102{
103 struct tulip_private *tp = netdev_priv(dev);
104 void __iomem *ioaddr = tp->base_addr;
105 int csr14;
106 int csr12;
107
108 /* set up what to advertise during the negotiation */
109
110 /* load in csr14 and mask off bits not to touch
111 * comment at top of file explains mask value
112 */
113 csr14 = (ioread32(ioaddr + CSR14) & 0xfff0ee39);
114
115 /* bit 17 - advetise 100baseTx-FD */
116 if (tp->sym_advertise & 0x0100) csr14 |= 0x00020000;
117
118 /* bit 16 - advertise 100baseTx-HD */
119 if (tp->sym_advertise & 0x0080) csr14 |= 0x00010000;
120
121 /* bit 6 - advertise 10baseT-HD */
122 if (tp->sym_advertise & 0x0020) csr14 |= 0x00000040;
123
124 /* Now set bit 12 Link Test Enable, Bit 7 Autonegotiation Enable
125 * and bit 0 Don't PowerDown 10baseT
126 */
127 csr14 |= 0x00001184;
128
129 if (tulip_debug > 1)
130 printk(KERN_DEBUG "%s: Restarting PNIC2 autonegotiation, "
131 "csr14=%8.8x.\n", dev->name, csr14);
132
133 /* tell pnic2_lnk_change we are doing an nway negotiation */
134 dev->if_port = 0;
135 tp->nway = tp->mediasense = 1;
136 tp->nwayset = tp->lpar = 0;
137
138 /* now we have to set up csr6 for NWAY state */
139
140 tp->csr6 = ioread32(ioaddr + CSR6);
141 if (tulip_debug > 1)
142 printk(KERN_DEBUG "%s: On Entry to Nway, "
143 "csr6=%8.8x.\n", dev->name, tp->csr6);
144
145 /* mask off any bits not to touch
146 * comment at top of file explains mask value
147 */
148 tp->csr6 = tp->csr6 & 0xfe3bd1fd;
149
150 /* don't forget that bit 9 is also used for advertising */
151 /* advertise 10baseT-FD for the negotiation (bit 9) */
152 if (tp->sym_advertise & 0x0040) tp->csr6 |= 0x00000200;
153
154 /* set bit 24 for nway negotiation mode ...
155 * see Data Port Selection comment at top of file
156 * and "Stop" - reset both Transmit (bit 13) and Receive (bit 1)
157 */
158 tp->csr6 |= 0x01000000;
159 iowrite32(csr14, ioaddr + CSR14);
160 iowrite32(tp->csr6, ioaddr + CSR6);
161 udelay(100);
162
163 /* all set up so now force the negotiation to begin */
164
165 /* read in current values and mask off all but the
166 * Autonegotiation bits 14:12. Writing a 001 to those bits
167 * should start the autonegotiation
168 */
169 csr12 = (ioread32(ioaddr + CSR12) & 0xffff8fff);
170 csr12 |= 0x1000;
171 iowrite32(csr12, ioaddr + CSR12);
172}
173
174
175
176void pnic2_lnk_change(struct net_device *dev, int csr5)
177{
178 struct tulip_private *tp = netdev_priv(dev);
179 void __iomem *ioaddr = tp->base_addr;
180 int csr14;
181
182 /* read the staus register to find out what is up */
183 int csr12 = ioread32(ioaddr + CSR12);
184
185 if (tulip_debug > 1)
186 printk(KERN_INFO"%s: PNIC2 link status interrupt %8.8x, "
187 " CSR5 %x, %8.8x.\n", dev->name, csr12,
188 csr5, ioread32(ioaddr + CSR14));
189
190 /* If NWay finished and we have a negotiated partner capability.
191 * check bits 14:12 for bit pattern 101 - all is good
192 */
193 if (tp->nway && !tp->nwayset) {
194
195 /* we did an auto negotiation */
196
197 if ((csr12 & 0x7000) == 0x5000) {
198
199 /* negotiation ended successfully */
200
201 /* get the link partners reply and mask out all but
202 * bits 24-21 which show the partners capabilites
203 * and match those to what we advertised
204 *
205 * then begin to interpret the results of the negotiation.
206 * Always go in this order : (we are ignoring T4 for now)
207 * 100baseTx-FD, 100baseTx-HD, 10baseT-FD, 10baseT-HD
208 */
209
210 int negotiated = ((csr12 >> 16) & 0x01E0) & tp->sym_advertise;
211 tp->lpar = (csr12 >> 16);
212 tp->nwayset = 1;
213
214 if (negotiated & 0x0100) dev->if_port = 5;
215 else if (negotiated & 0x0080) dev->if_port = 3;
216 else if (negotiated & 0x0040) dev->if_port = 4;
217 else if (negotiated & 0x0020) dev->if_port = 0;
218 else {
219 if (tulip_debug > 1)
220 printk(KERN_INFO "%s: funny autonegotiate result "
221 "csr12 %8.8x advertising %4.4x\n",
222 dev->name, csr12, tp->sym_advertise);
223 tp->nwayset = 0;
224 /* so check if 100baseTx link state is okay */
225 if ((csr12 & 2) == 0 && (tp->sym_advertise & 0x0180))
226 dev->if_port = 3;
227 }
228
229 /* now record the duplex that was negotiated */
230 tp->full_duplex = 0;
231 if ((dev->if_port == 4) || (dev->if_port == 5))
232 tp->full_duplex = 1;
233
234 if (tulip_debug > 1) {
235 if (tp->nwayset)
236 printk(KERN_INFO "%s: Switching to %s based on link "
237 "negotiation %4.4x & %4.4x = %4.4x.\n",
238 dev->name, medianame[dev->if_port],
239 tp->sym_advertise, tp->lpar, negotiated);
240 }
241
242 /* remember to turn off bit 7 - autonegotiate
243 * enable so we can properly end nway mode and
244 * set duplex (ie. use csr6<9> again)
245 */
246 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
247 iowrite32(csr14,ioaddr + CSR14);
248
249
250 /* now set the data port and operating mode
251 * (see the Data Port Selection comments at
252 * the top of the file
253 */
254
255 /* get current csr6 and mask off bits not to touch */
256 /* see comment at top of file */
257
258 tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
259
260 /* so if using if_port 3 or 5 then select the 100baseT
261 * port else select the 10baseT port.
262 * See the Data Port Selection table at the top
263 * of the file which was taken from the PNIC_II.PDF
264 * datasheet
265 */
266 if (dev->if_port & 1) tp->csr6 |= 0x01840000;
267 else tp->csr6 |= 0x00400000;
268
269 /* now set the full duplex bit appropriately */
270 if (tp->full_duplex) tp->csr6 |= 0x00000200;
271
272 iowrite32(1, ioaddr + CSR13);
273
274 if (tulip_debug > 2)
275 printk(KERN_DEBUG "%s: Setting CSR6 %8.8x/%x CSR12 "
276 "%8.8x.\n", dev->name, tp->csr6,
277 ioread32(ioaddr + CSR6), ioread32(ioaddr + CSR12));
278
279 /* now the following actually writes out the
280 * new csr6 values
281 */
282 tulip_start_rxtx(tp);
283
284 return;
285
286 } else {
287 printk(KERN_INFO "%s: Autonegotiation failed, "
288 "using %s, link beat status %4.4x.\n",
289 dev->name, medianame[dev->if_port], csr12);
290
291 /* remember to turn off bit 7 - autonegotiate
292 * enable so we don't forget
293 */
294 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
295 iowrite32(csr14,ioaddr + CSR14);
296
297 /* what should we do when autonegotiate fails?
298 * should we try again or default to baseline
299 * case. I just don't know.
300 *
301 * for now default to some baseline case
302 */
303
304 dev->if_port = 0;
305 tp->nway = 0;
306 tp->nwayset = 1;
307
308 /* set to 10baseTx-HD - see Data Port Selection
309 * comment given at the top of the file
310 */
311 tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
312 tp->csr6 |= 0x00400000;
313
314 tulip_restart_rxtx(tp);
315
316 return;
317
318 }
319 }
320
321 if ((tp->nwayset && (csr5 & 0x08000000)
322 && (dev->if_port == 3 || dev->if_port == 5)
323 && (csr12 & 2) == 2) || (tp->nway && (csr5 & (TPLnkFail)))) {
324
325 /* Link blew? Maybe restart NWay. */
326
327 if (tulip_debug > 2)
328 printk(KERN_DEBUG "%s: Ugh! Link blew?\n", dev->name);
329
330 del_timer_sync(&tp->timer);
331 pnic2_start_nway(dev);
332 tp->timer.expires = RUN_AT(3*HZ);
333 add_timer(&tp->timer);
334
335 return;
336 }
337
338
339 if (dev->if_port == 3 || dev->if_port == 5) {
340
341 /* we are at 100mb and a potential link change occurred */
342
343 if (tulip_debug > 1)
344 printk(KERN_INFO"%s: PNIC2 %s link beat %s.\n",
345 dev->name, medianame[dev->if_port],
346 (csr12 & 2) ? "failed" : "good");
347
348 /* check 100 link beat */
349
350 tp->nway = 0;
351 tp->nwayset = 1;
352
353 /* if failed then try doing an nway to get in sync */
354 if ((csr12 & 2) && ! tp->medialock) {
355 del_timer_sync(&tp->timer);
356 pnic2_start_nway(dev);
357 tp->timer.expires = RUN_AT(3*HZ);
358 add_timer(&tp->timer);
359 }
360
361 return;
362 }
363
364 if (dev->if_port == 0 || dev->if_port == 4) {
365
366 /* we are at 10mb and a potential link change occurred */
367
368 if (tulip_debug > 1)
369 printk(KERN_INFO"%s: PNIC2 %s link beat %s.\n",
370 dev->name, medianame[dev->if_port],
371 (csr12 & 4) ? "failed" : "good");
372
373
374 tp->nway = 0;
375 tp->nwayset = 1;
376
377 /* if failed, try doing an nway to get in sync */
378 if ((csr12 & 4) && ! tp->medialock) {
379 del_timer_sync(&tp->timer);
380 pnic2_start_nway(dev);
381 tp->timer.expires = RUN_AT(3*HZ);
382 add_timer(&tp->timer);
383 }
384
385 return;
386 }
387
388
389 if (tulip_debug > 1)
390 printk(KERN_INFO"%s: PNIC2 Link Change Default?\n",dev->name);
391
392 /* if all else fails default to trying 10baseT-HD */
393 dev->if_port = 0;
394
395 /* make sure autonegotiate enable is off */
396 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
397 iowrite32(csr14,ioaddr + CSR14);
398
399 /* set to 10baseTx-HD - see Data Port Selection
400 * comment given at the top of the file
401 */
402 tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
403 tp->csr6 |= 0x00400000;
404
405 tulip_restart_rxtx(tp);
406}
407
diff --git a/drivers/net/tulip/timer.c b/drivers/net/tulip/timer.c
new file mode 100644
index 000000000000..691568283553
--- /dev/null
+++ b/drivers/net/tulip/timer.c
@@ -0,0 +1,175 @@
1/*
2 drivers/net/tulip/timer.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/pci.h>
18#include "tulip.h"
19
20
21void tulip_timer(unsigned long data)
22{
23 struct net_device *dev = (struct net_device *)data;
24 struct tulip_private *tp = netdev_priv(dev);
25 void __iomem *ioaddr = tp->base_addr;
26 u32 csr12 = ioread32(ioaddr + CSR12);
27 int next_tick = 2*HZ;
28
29 if (tulip_debug > 2) {
30 printk(KERN_DEBUG "%s: Media selection tick, %s, status %8.8x mode"
31 " %8.8x SIA %8.8x %8.8x %8.8x %8.8x.\n",
32 dev->name, medianame[dev->if_port], ioread32(ioaddr + CSR5),
33 ioread32(ioaddr + CSR6), csr12, ioread32(ioaddr + CSR13),
34 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
35 }
36 switch (tp->chip_id) {
37 case DC21140:
38 case DC21142:
39 case MX98713:
40 case COMPEX9881:
41 case DM910X:
42 case ULI526X:
43 default: {
44 struct medialeaf *mleaf;
45 unsigned char *p;
46 if (tp->mtable == NULL) { /* No EEPROM info, use generic code. */
47 /* Not much that can be done.
48 Assume this a generic MII or SYM transceiver. */
49 next_tick = 60*HZ;
50 if (tulip_debug > 2)
51 printk(KERN_DEBUG "%s: network media monitor CSR6 %8.8x "
52 "CSR12 0x%2.2x.\n",
53 dev->name, ioread32(ioaddr + CSR6), csr12 & 0xff);
54 break;
55 }
56 mleaf = &tp->mtable->mleaf[tp->cur_index];
57 p = mleaf->leafdata;
58 switch (mleaf->type) {
59 case 0: case 4: {
60 /* Type 0 serial or 4 SYM transceiver. Check the link beat bit. */
61 int offset = mleaf->type == 4 ? 5 : 2;
62 s8 bitnum = p[offset];
63 if (p[offset+1] & 0x80) {
64 if (tulip_debug > 1)
65 printk(KERN_DEBUG"%s: Transceiver monitor tick "
66 "CSR12=%#2.2x, no media sense.\n",
67 dev->name, csr12);
68 if (mleaf->type == 4) {
69 if (mleaf->media == 3 && (csr12 & 0x02))
70 goto select_next_media;
71 }
72 break;
73 }
74 if (tulip_debug > 2)
75 printk(KERN_DEBUG "%s: Transceiver monitor tick: CSR12=%#2.2x"
76 " bit %d is %d, expecting %d.\n",
77 dev->name, csr12, (bitnum >> 1) & 7,
78 (csr12 & (1 << ((bitnum >> 1) & 7))) != 0,
79 (bitnum >= 0));
80 /* Check that the specified bit has the proper value. */
81 if ((bitnum < 0) !=
82 ((csr12 & (1 << ((bitnum >> 1) & 7))) != 0)) {
83 if (tulip_debug > 2)
84 printk(KERN_DEBUG "%s: Link beat detected for %s.\n", dev->name,
85 medianame[mleaf->media & MEDIA_MASK]);
86 if ((p[2] & 0x61) == 0x01) /* Bogus Znyx board. */
87 goto actually_mii;
88 netif_carrier_on(dev);
89 break;
90 }
91 netif_carrier_off(dev);
92 if (tp->medialock)
93 break;
94 select_next_media:
95 if (--tp->cur_index < 0) {
96 /* We start again, but should instead look for default. */
97 tp->cur_index = tp->mtable->leafcount - 1;
98 }
99 dev->if_port = tp->mtable->mleaf[tp->cur_index].media;
100 if (tulip_media_cap[dev->if_port] & MediaIsFD)
101 goto select_next_media; /* Skip FD entries. */
102 if (tulip_debug > 1)
103 printk(KERN_DEBUG "%s: No link beat on media %s,"
104 " trying transceiver type %s.\n",
105 dev->name, medianame[mleaf->media & MEDIA_MASK],
106 medianame[tp->mtable->mleaf[tp->cur_index].media]);
107 tulip_select_media(dev, 0);
108 /* Restart the transmit process. */
109 tulip_restart_rxtx(tp);
110 next_tick = (24*HZ)/10;
111 break;
112 }
113 case 1: case 3: /* 21140, 21142 MII */
114 actually_mii:
115 if (tulip_check_duplex(dev) < 0) {
116 netif_carrier_off(dev);
117 next_tick = 3*HZ;
118 } else {
119 netif_carrier_on(dev);
120 next_tick = 60*HZ;
121 }
122 break;
123 case 2: /* 21142 serial block has no link beat. */
124 default:
125 break;
126 }
127 }
128 break;
129 }
130 /* mod_timer synchronizes us with potential add_timer calls
131 * from interrupts.
132 */
133 mod_timer(&tp->timer, RUN_AT(next_tick));
134}
135
136
137void mxic_timer(unsigned long data)
138{
139 struct net_device *dev = (struct net_device *)data;
140 struct tulip_private *tp = netdev_priv(dev);
141 void __iomem *ioaddr = tp->base_addr;
142 int next_tick = 60*HZ;
143
144 if (tulip_debug > 3) {
145 printk(KERN_INFO"%s: MXIC negotiation status %8.8x.\n", dev->name,
146 ioread32(ioaddr + CSR12));
147 }
148 if (next_tick) {
149 mod_timer(&tp->timer, RUN_AT(next_tick));
150 }
151}
152
153
154void comet_timer(unsigned long data)
155{
156 struct net_device *dev = (struct net_device *)data;
157 struct tulip_private *tp = netdev_priv(dev);
158 int next_tick = 60*HZ;
159
160 if (tulip_debug > 1)
161 printk(KERN_DEBUG "%s: Comet link status %4.4x partner capability "
162 "%4.4x.\n",
163 dev->name,
164 tulip_mdio_read(dev, tp->phys[0], 1),
165 tulip_mdio_read(dev, tp->phys[0], 5));
166 /* mod_timer synchronizes us with potential add_timer calls
167 * from interrupts.
168 */
169 if (tulip_check_duplex(dev) < 0)
170 { netif_carrier_off(dev); }
171 else
172 { netif_carrier_on(dev); }
173 mod_timer(&tp->timer, RUN_AT(next_tick));
174}
175
diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h
new file mode 100644
index 000000000000..20346d847d9e
--- /dev/null
+++ b/drivers/net/tulip/tulip.h
@@ -0,0 +1,493 @@
1/*
2 drivers/net/tulip/tulip.h
3
4 Copyright 2000,2001 The Linux Kernel Team
5 Written/copyright 1994-2001 by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU General Public License, incorporated herein by reference.
9
10 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
11 for more information on this driver, or visit the project
12 Web page at http://sourceforge.net/projects/tulip/
13
14*/
15
16#ifndef __NET_TULIP_H__
17#define __NET_TULIP_H__
18
19#include <linux/config.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22#include <linux/spinlock.h>
23#include <linux/netdevice.h>
24#include <linux/timer.h>
25#include <linux/delay.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28
29
30
31/* undefine, or define to various debugging levels (>4 == obscene levels) */
32#define TULIP_DEBUG 1
33
34/* undefine USE_IO_OPS for MMIO, define for PIO */
35#ifdef CONFIG_TULIP_MMIO
36# undef USE_IO_OPS
37#else
38# define USE_IO_OPS 1
39#endif
40
41
42
43struct tulip_chip_table {
44 char *chip_name;
45 int io_size;
46 int valid_intrs; /* CSR7 interrupt enable settings */
47 int flags;
48 void (*media_timer) (unsigned long data);
49};
50
51
52enum tbl_flag {
53 HAS_MII = 0x0001,
54 HAS_MEDIA_TABLE = 0x0002,
55 CSR12_IN_SROM = 0x0004,
56 ALWAYS_CHECK_MII = 0x0008,
57 HAS_ACPI = 0x0010,
58 MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
59 HAS_PNICNWAY = 0x0080,
60 HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
61 HAS_INTR_MITIGATION = 0x0100,
62 IS_ASIX = 0x0200,
63 HAS_8023X = 0x0400,
64 COMET_MAC_ADDR = 0x0800,
65 HAS_PCI_MWI = 0x1000,
66 HAS_PHY_IRQ = 0x2000,
67 HAS_SWAPPED_SEEPROM = 0x4000,
68 NEEDS_FAKE_MEDIA_TABLE = 0x8000,
69};
70
71
72/* chip types. careful! order is VERY IMPORTANT here, as these
73 * are used throughout the driver as indices into arrays */
74/* Note 21142 == 21143. */
75enum chips {
76 DC21040 = 0,
77 DC21041 = 1,
78 DC21140 = 2,
79 DC21142 = 3, DC21143 = 3,
80 LC82C168,
81 MX98713,
82 MX98715,
83 MX98725,
84 AX88140,
85 PNIC2,
86 COMET,
87 COMPEX9881,
88 I21145,
89 DM910X,
90 CONEXANT,
91 ULI526X
92};
93
94
95enum MediaIs {
96 MediaIsFD = 1,
97 MediaAlwaysFD = 2,
98 MediaIsMII = 4,
99 MediaIsFx = 8,
100 MediaIs100 = 16
101};
102
103
104/* Offsets to the Command and Status Registers, "CSRs". All accesses
105 must be longword instructions and quadword aligned. */
106enum tulip_offsets {
107 CSR0 = 0,
108 CSR1 = 0x08,
109 CSR2 = 0x10,
110 CSR3 = 0x18,
111 CSR4 = 0x20,
112 CSR5 = 0x28,
113 CSR6 = 0x30,
114 CSR7 = 0x38,
115 CSR8 = 0x40,
116 CSR9 = 0x48,
117 CSR10 = 0x50,
118 CSR11 = 0x58,
119 CSR12 = 0x60,
120 CSR13 = 0x68,
121 CSR14 = 0x70,
122 CSR15 = 0x78,
123};
124
125/* register offset and bits for CFDD PCI config reg */
126enum pci_cfg_driver_reg {
127 CFDD = 0x40,
128 CFDD_Sleep = (1 << 31),
129 CFDD_Snooze = (1 << 30),
130};
131
132#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
133
134/* The bits in the CSR5 status registers, mostly interrupt sources. */
135enum status_bits {
136 TimerInt = 0x800,
137 SytemError = 0x2000,
138 TPLnkFail = 0x1000,
139 TPLnkPass = 0x10,
140 NormalIntr = 0x10000,
141 AbnormalIntr = 0x8000,
142 RxJabber = 0x200,
143 RxDied = 0x100,
144 RxNoBuf = 0x80,
145 RxIntr = 0x40,
146 TxFIFOUnderflow = 0x20,
147 TxJabber = 0x08,
148 TxNoBuf = 0x04,
149 TxDied = 0x02,
150 TxIntr = 0x01,
151};
152
153/* bit mask for CSR5 TX/RX process state */
154#define CSR5_TS 0x00700000
155#define CSR5_RS 0x000e0000
156
157enum tulip_mode_bits {
158 TxThreshold = (1 << 22),
159 FullDuplex = (1 << 9),
160 TxOn = 0x2000,
161 AcceptBroadcast = 0x0100,
162 AcceptAllMulticast = 0x0080,
163 AcceptAllPhys = 0x0040,
164 AcceptRunt = 0x0008,
165 RxOn = 0x0002,
166 RxTx = (TxOn | RxOn),
167};
168
169
170enum tulip_busconfig_bits {
171 MWI = (1 << 24),
172 MRL = (1 << 23),
173 MRM = (1 << 21),
174 CALShift = 14,
175 BurstLenShift = 8,
176};
177
178
179/* The Tulip Rx and Tx buffer descriptors. */
180struct tulip_rx_desc {
181 s32 status;
182 s32 length;
183 u32 buffer1;
184 u32 buffer2;
185};
186
187
188struct tulip_tx_desc {
189 s32 status;
190 s32 length;
191 u32 buffer1;
192 u32 buffer2; /* We use only buffer 1. */
193};
194
195
196enum desc_status_bits {
197 DescOwned = 0x80000000,
198 RxDescFatalErr = 0x8000,
199 RxWholePkt = 0x0300,
200};
201
202
203enum t21143_csr6_bits {
204 csr6_sc = (1<<31),
205 csr6_ra = (1<<30),
206 csr6_ign_dest_msb = (1<<26),
207 csr6_mbo = (1<<25),
208 csr6_scr = (1<<24), /* scramble mode flag: can't be set */
209 csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
210 csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
211 csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
212 csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
213 csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
214 csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
215 csr6_trh = (1<<15), /* Transmit Threshold high bit */
216 csr6_trl = (1<<14), /* Transmit Threshold low bit */
217
218 /***************************************************************
219 * This table shows transmit threshold values based on media *
220 * and these two registers (from PNIC1 & 2 docs) Note: this is *
221 * all meaningless if sf is set. *
222 ***************************************************************/
223
224 /***********************************
225 * (trh,trl) * 100BaseTX * 10BaseT *
226 ***********************************
227 * (0,0) * 128 * 72 *
228 * (0,1) * 256 * 96 *
229 * (1,0) * 512 * 128 *
230 * (1,1) * 1024 * 160 *
231 ***********************************/
232
233 csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
234 csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
235 csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
236 /* set both and you get (PHY) loopback */
237 csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
238 csr6_pm = (1<<7), /* Pass All Multicast */
239 csr6_pr = (1<<6), /* Promiscuous mode */
240 csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
241 csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
242 csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
243 csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
244 csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
245
246 csr6_mask_capture = (csr6_sc | csr6_ca),
247 csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
248 csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
249 csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
250 csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
251 csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
252 csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
253 csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
254};
255
256
257/* Keep the ring sizes a power of two for efficiency.
258 Making the Tx ring too large decreases the effectiveness of channel
259 bonding and packet priority.
260 There are no ill effects from too-large receive rings. */
261
262#define TX_RING_SIZE 32
263#define RX_RING_SIZE 128
264#define MEDIA_MASK 31
265
266#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
267
268#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
269
270#if defined(__sparc__) || defined(__hppa__)
271/* The UltraSparc PCI controllers will disconnect at every 64-byte
272 * crossing anyways so it makes no sense to tell Tulip to burst
273 * any more than that.
274 */
275#define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
276#else
277#define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
278#endif
279
280
281/* Ring-wrap flag in length field, use for last ring entry.
282 0x01000000 means chain on buffer2 address,
283 0x02000000 means use the ring start address in CSR2/3.
284 Note: Some work-alike chips do not function correctly in chained mode.
285 The ASIX chip works only in chained mode.
286 Thus we indicates ring mode, but always write the 'next' field for
287 chained mode as well.
288*/
289#define DESC_RING_WRAP 0x02000000
290
291
292#define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */
293
294
295#define RUN_AT(x) (jiffies + (x))
296
297#if defined(__i386__) /* AKA get_unaligned() */
298#define get_u16(ptr) (*(u16 *)(ptr))
299#else
300#define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
301#endif
302
303struct medialeaf {
304 u8 type;
305 u8 media;
306 unsigned char *leafdata;
307};
308
309
310struct mediatable {
311 u16 defaultmedia;
312 u8 leafcount;
313 u8 csr12dir; /* General purpose pin directions. */
314 unsigned has_mii:1;
315 unsigned has_nonmii:1;
316 unsigned has_reset:6;
317 u32 csr15dir;
318 u32 csr15val; /* 21143 NWay setting. */
319 struct medialeaf mleaf[0];
320};
321
322
323struct mediainfo {
324 struct mediainfo *next;
325 int info_type;
326 int index;
327 unsigned char *info;
328};
329
330struct ring_info {
331 struct sk_buff *skb;
332 dma_addr_t mapping;
333};
334
335
336struct tulip_private {
337 const char *product_name;
338 struct net_device *next_module;
339 struct tulip_rx_desc *rx_ring;
340 struct tulip_tx_desc *tx_ring;
341 dma_addr_t rx_ring_dma;
342 dma_addr_t tx_ring_dma;
343 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
344 struct ring_info tx_buffers[TX_RING_SIZE];
345 /* The addresses of receive-in-place skbuffs. */
346 struct ring_info rx_buffers[RX_RING_SIZE];
347 u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
348 int chip_id;
349 int revision;
350 int flags;
351 struct net_device_stats stats;
352 struct timer_list timer; /* Media selection timer. */
353 struct timer_list oom_timer; /* Out of memory timer. */
354 u32 mc_filter[2];
355 spinlock_t lock;
356 spinlock_t mii_lock;
357 unsigned int cur_rx, cur_tx; /* The next free ring entry */
358 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
359
360#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
361 int mit_on;
362#endif
363 unsigned int full_duplex:1; /* Full-duplex operation requested. */
364 unsigned int full_duplex_lock:1;
365 unsigned int fake_addr:1; /* Multiport board faked address. */
366 unsigned int default_port:4; /* Last dev->if_port value. */
367 unsigned int media2:4; /* Secondary monitored media port. */
368 unsigned int medialock:1; /* Don't sense media type. */
369 unsigned int mediasense:1; /* Media sensing in progress. */
370 unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
371 unsigned int csr0; /* CSR0 setting. */
372 unsigned int csr6; /* Current CSR6 control settings. */
373 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
374 void (*link_change) (struct net_device * dev, int csr5);
375 u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
376 u16 lpar; /* 21143 Link partner ability. */
377 u16 advertising[4];
378 signed char phys[4], mii_cnt; /* MII device addresses. */
379 struct mediatable *mtable;
380 int cur_index; /* Current media index. */
381 int saved_if_port;
382 struct pci_dev *pdev;
383 int ttimer;
384 int susp_rx;
385 unsigned long nir;
386 void __iomem *base_addr;
387 int csr12_shadow;
388 int pad0; /* Used for 8-byte alignment */
389};
390
391
392struct eeprom_fixup {
393 char *name;
394 unsigned char addr0;
395 unsigned char addr1;
396 unsigned char addr2;
397 u16 newtable[32]; /* Max length below. */
398};
399
400
401/* 21142.c */
402extern u16 t21142_csr14[];
403void t21142_timer(unsigned long data);
404void t21142_start_nway(struct net_device *dev);
405void t21142_lnk_change(struct net_device *dev, int csr5);
406
407
408/* PNIC2.c */
409void pnic2_lnk_change(struct net_device *dev, int csr5);
410void pnic2_timer(unsigned long data);
411void pnic2_start_nway(struct net_device *dev);
412void pnic2_lnk_change(struct net_device *dev, int csr5);
413
414/* eeprom.c */
415void tulip_parse_eeprom(struct net_device *dev);
416int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
417
418/* interrupt.c */
419extern unsigned int tulip_max_interrupt_work;
420extern int tulip_rx_copybreak;
421irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
422int tulip_refill_rx(struct net_device *dev);
423#ifdef CONFIG_TULIP_NAPI
424int tulip_poll(struct net_device *dev, int *budget);
425#endif
426
427
428/* media.c */
429int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
430void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
431void tulip_select_media(struct net_device *dev, int startup);
432int tulip_check_duplex(struct net_device *dev);
433void tulip_find_mii (struct net_device *dev, int board_idx);
434
435/* pnic.c */
436void pnic_do_nway(struct net_device *dev);
437void pnic_lnk_change(struct net_device *dev, int csr5);
438void pnic_timer(unsigned long data);
439
440/* timer.c */
441void tulip_timer(unsigned long data);
442void mxic_timer(unsigned long data);
443void comet_timer(unsigned long data);
444
445/* tulip_core.c */
446extern int tulip_debug;
447extern const char * const medianame[];
448extern const char tulip_media_cap[];
449extern struct tulip_chip_table tulip_tbl[];
450void oom_timer(unsigned long data);
451extern u8 t21040_csr13[];
452
453static inline void tulip_start_rxtx(struct tulip_private *tp)
454{
455 void __iomem *ioaddr = tp->base_addr;
456 iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
457 barrier();
458 (void) ioread32(ioaddr + CSR6); /* mmio sync */
459}
460
461static inline void tulip_stop_rxtx(struct tulip_private *tp)
462{
463 void __iomem *ioaddr = tp->base_addr;
464 u32 csr6 = ioread32(ioaddr + CSR6);
465
466 if (csr6 & RxTx) {
467 unsigned i=1300/10;
468 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
469 barrier();
470 /* wait until in-flight frame completes.
471 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
472 * Typically expect this loop to end in < 50 us on 100BT.
473 */
474 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
475 udelay(10);
476
477 if (!i)
478 printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
479 pci_name(tp->pdev));
480 }
481}
482
483static inline void tulip_restart_rxtx(struct tulip_private *tp)
484{
485 if(!(tp->chip_id == ULI526X &&
486 (tp->revision == 0x40 || tp->revision == 0x50))) {
487 tulip_stop_rxtx(tp);
488 udelay(5);
489 }
490 tulip_start_rxtx(tp);
491}
492
493#endif /* __NET_TULIP_H__ */
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
new file mode 100644
index 000000000000..d098b3ba3538
--- /dev/null
+++ b/drivers/net/tulip/tulip_core.c
@@ -0,0 +1,1861 @@
1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3/*
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
17#include <linux/config.h>
18
19#define DRV_NAME "tulip"
20#ifdef CONFIG_TULIP_NAPI
21#define DRV_VERSION "1.1.13-NAPI" /* Keep at least for test */
22#else
23#define DRV_VERSION "1.1.13"
24#endif
25#define DRV_RELDATE "May 11, 2002"
26
27
28#include <linux/module.h>
29#include <linux/pci.h>
30#include "tulip.h"
31#include <linux/init.h>
32#include <linux/etherdevice.h>
33#include <linux/delay.h>
34#include <linux/mii.h>
35#include <linux/ethtool.h>
36#include <linux/crc32.h>
37#include <asm/unaligned.h>
38#include <asm/uaccess.h>
39
40#ifdef __sparc__
41#include <asm/pbm.h>
42#endif
43
44static char version[] __devinitdata =
45 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
46
47
48/* A few user-configurable values. */
49
50/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
51static unsigned int max_interrupt_work = 25;
52
53#define MAX_UNITS 8
54/* Used to pass the full-duplex flag, etc. */
55static int full_duplex[MAX_UNITS];
56static int options[MAX_UNITS];
57static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
58
59/* The possible media types that can be set in options[] are: */
60const char * const medianame[32] = {
61 "10baseT", "10base2", "AUI", "100baseTx",
62 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
63 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
64 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
65 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
66 "","","","", "","","","", "","","","Transceiver reset",
67};
68
69/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
70#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
71 || defined(__sparc_) || defined(__ia64__) \
72 || defined(__sh__) || defined(__mips__)
73static int rx_copybreak = 1518;
74#else
75static int rx_copybreak = 100;
76#endif
77
78/*
79 Set the bus performance register.
80 Typical: Set 16 longword cache alignment, no burst limit.
81 Cache alignment bits 15:14 Burst length 13:8
82 0000 No alignment 0x00000000 unlimited 0800 8 longwords
83 4000 8 longwords 0100 1 longword 1000 16 longwords
84 8000 16 longwords 0200 2 longwords 2000 32 longwords
85 C000 32 longwords 0400 4 longwords
86 Warning: many older 486 systems are broken and require setting 0x00A04800
87 8 longword cache alignment, 8 longword burst.
88 ToDo: Non-Intel setting could be better.
89*/
90
91#if defined(__alpha__) || defined(__ia64__)
92static int csr0 = 0x01A00000 | 0xE000;
93#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
94static int csr0 = 0x01A00000 | 0x8000;
95#elif defined(__sparc__) || defined(__hppa__)
96/* The UltraSparc PCI controllers will disconnect at every 64-byte
97 * crossing anyways so it makes no sense to tell Tulip to burst
98 * any more than that.
99 */
100static int csr0 = 0x01A00000 | 0x9000;
101#elif defined(__arm__) || defined(__sh__)
102static int csr0 = 0x01A00000 | 0x4800;
103#elif defined(__mips__)
104static int csr0 = 0x00200000 | 0x4000;
105#else
106#warning Processor architecture undefined!
107static int csr0 = 0x00A00000 | 0x4800;
108#endif
109
110/* Operational parameters that usually are not changed. */
111/* Time in jiffies before concluding the transmitter is hung. */
112#define TX_TIMEOUT (4*HZ)
113
114
115MODULE_AUTHOR("The Linux Kernel Team");
116MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
117MODULE_LICENSE("GPL");
118MODULE_VERSION(DRV_VERSION);
119module_param(tulip_debug, int, 0);
120module_param(max_interrupt_work, int, 0);
121module_param(rx_copybreak, int, 0);
122module_param(csr0, int, 0);
123module_param_array(options, int, NULL, 0);
124module_param_array(full_duplex, int, NULL, 0);
125
126#define PFX DRV_NAME ": "
127
128#ifdef TULIP_DEBUG
129int tulip_debug = TULIP_DEBUG;
130#else
131int tulip_debug = 1;
132#endif
133
134
135
136/*
137 * This table use during operation for capabilities and media timer.
138 *
139 * It is indexed via the values in 'enum chips'
140 */
141
142struct tulip_chip_table tulip_tbl[] = {
143 { }, /* placeholder for array, slot unused currently */
144 { }, /* placeholder for array, slot unused currently */
145
146 /* DC21140 */
147 { "Digital DS21140 Tulip", 128, 0x0001ebef,
148 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer },
149
150 /* DC21142, DC21143 */
151 { "Digital DS21143 Tulip", 128, 0x0801fbff,
152 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
153 | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer },
154
155 /* LC82C168 */
156 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
157 HAS_MII | HAS_PNICNWAY, pnic_timer },
158
159 /* MX98713 */
160 { "Macronix 98713 PMAC", 128, 0x0001ebef,
161 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
162
163 /* MX98715 */
164 { "Macronix 98715 PMAC", 256, 0x0001ebef,
165 HAS_MEDIA_TABLE, mxic_timer },
166
167 /* MX98725 */
168 { "Macronix 98725 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer },
170
171 /* AX88140 */
172 { "ASIX AX88140", 128, 0x0001fbff,
173 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
174 | IS_ASIX, tulip_timer },
175
176 /* PNIC2 */
177 { "Lite-On PNIC-II", 256, 0x0801fbff,
178 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer },
179
180 /* COMET */
181 { "ADMtek Comet", 256, 0x0001abef,
182 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer },
183
184 /* COMPEX9881 */
185 { "Compex 9881 PMAC", 128, 0x0001ebef,
186 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
187
188 /* I21145 */
189 { "Intel DS21145 Tulip", 128, 0x0801fbff,
190 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
191 | HAS_NWAY | HAS_PCI_MWI, t21142_timer },
192
193 /* DM910X */
194 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
195 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
196 tulip_timer },
197
198 /* RS7112 */
199 { "Conexant LANfinity", 256, 0x0001ebef,
200 HAS_MII | HAS_ACPI, tulip_timer },
201
202 /* ULi526X */
203 { "ULi M5261/M5263", 128, 0x0001ebef,
204 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, tulip_timer },
205};
206
207
208static struct pci_device_id tulip_pci_tbl[] = {
209 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
210 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
211 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
212 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
213 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
214/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
215 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
216 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
217 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
218 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
228 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
229 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
230 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
231 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
233 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
234 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
235 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
238 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
243 { 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
245 { } /* terminate list */
246};
247MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
248
249
250/* A full-duplex map for media types. */
251const char tulip_media_cap[32] =
252{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
253
254static void tulip_tx_timeout(struct net_device *dev);
255static void tulip_init_ring(struct net_device *dev);
256static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
257static int tulip_open(struct net_device *dev);
258static int tulip_close(struct net_device *dev);
259static void tulip_up(struct net_device *dev);
260static void tulip_down(struct net_device *dev);
261static struct net_device_stats *tulip_get_stats(struct net_device *dev);
262static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
263static void set_rx_mode(struct net_device *dev);
264#ifdef CONFIG_NET_POLL_CONTROLLER
265static void poll_tulip(struct net_device *dev);
266#endif
267
268static void tulip_set_power_state (struct tulip_private *tp,
269 int sleep, int snooze)
270{
271 if (tp->flags & HAS_ACPI) {
272 u32 tmp, newtmp;
273 pci_read_config_dword (tp->pdev, CFDD, &tmp);
274 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
275 if (sleep)
276 newtmp |= CFDD_Sleep;
277 else if (snooze)
278 newtmp |= CFDD_Snooze;
279 if (tmp != newtmp)
280 pci_write_config_dword (tp->pdev, CFDD, newtmp);
281 }
282
283}
284
285
286static void tulip_up(struct net_device *dev)
287{
288 struct tulip_private *tp = netdev_priv(dev);
289 void __iomem *ioaddr = tp->base_addr;
290 int next_tick = 3*HZ;
291 int i;
292
293 /* Wake the chip from sleep/snooze mode. */
294 tulip_set_power_state (tp, 0, 0);
295
296 /* On some chip revs we must set the MII/SYM port before the reset!? */
297 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
298 iowrite32(0x00040000, ioaddr + CSR6);
299
300 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
301 iowrite32(0x00000001, ioaddr + CSR0);
302 udelay(100);
303
304 /* Deassert reset.
305 Wait the specified 50 PCI cycles after a reset by initializing
306 Tx and Rx queues and the address filter list. */
307 iowrite32(tp->csr0, ioaddr + CSR0);
308 udelay(100);
309
310 if (tulip_debug > 1)
311 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
312
313 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
314 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
315 tp->cur_rx = tp->cur_tx = 0;
316 tp->dirty_rx = tp->dirty_tx = 0;
317
318 if (tp->flags & MC_HASH_ONLY) {
319 u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr));
320 u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4)));
321 if (tp->chip_id == AX88140) {
322 iowrite32(0, ioaddr + CSR13);
323 iowrite32(addr_low, ioaddr + CSR14);
324 iowrite32(1, ioaddr + CSR13);
325 iowrite32(addr_high, ioaddr + CSR14);
326 } else if (tp->flags & COMET_MAC_ADDR) {
327 iowrite32(addr_low, ioaddr + 0xA4);
328 iowrite32(addr_high, ioaddr + 0xA8);
329 iowrite32(0, ioaddr + 0xAC);
330 iowrite32(0, ioaddr + 0xB0);
331 }
332 } else {
333 /* This is set_rx_mode(), but without starting the transmitter. */
334 u16 *eaddrs = (u16 *)dev->dev_addr;
335 u16 *setup_frm = &tp->setup_frame[15*6];
336 dma_addr_t mapping;
337
338 /* 21140 bug: you must add the broadcast address. */
339 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
340 /* Fill the final entry of the table with our physical address. */
341 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
342 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
343 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
344
345 mapping = pci_map_single(tp->pdev, tp->setup_frame,
346 sizeof(tp->setup_frame),
347 PCI_DMA_TODEVICE);
348 tp->tx_buffers[tp->cur_tx].skb = NULL;
349 tp->tx_buffers[tp->cur_tx].mapping = mapping;
350
351 /* Put the setup frame on the Tx list. */
352 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
353 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
354 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
355
356 tp->cur_tx++;
357 }
358
359 tp->saved_if_port = dev->if_port;
360 if (dev->if_port == 0)
361 dev->if_port = tp->default_port;
362
363 /* Allow selecting a default media. */
364 i = 0;
365 if (tp->mtable == NULL)
366 goto media_picked;
367 if (dev->if_port) {
368 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
369 (dev->if_port == 12 ? 0 : dev->if_port);
370 for (i = 0; i < tp->mtable->leafcount; i++)
371 if (tp->mtable->mleaf[i].media == looking_for) {
372 printk(KERN_INFO "%s: Using user-specified media %s.\n",
373 dev->name, medianame[dev->if_port]);
374 goto media_picked;
375 }
376 }
377 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
378 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
379 for (i = 0; i < tp->mtable->leafcount; i++)
380 if (tp->mtable->mleaf[i].media == looking_for) {
381 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
382 dev->name, medianame[looking_for]);
383 goto media_picked;
384 }
385 }
386 /* Start sensing first non-full-duplex media. */
387 for (i = tp->mtable->leafcount - 1;
388 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
389 ;
390media_picked:
391
392 tp->csr6 = 0;
393 tp->cur_index = i;
394 tp->nwayset = 0;
395
396 if (dev->if_port) {
397 if (tp->chip_id == DC21143 &&
398 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
399 /* We must reset the media CSRs when we force-select MII mode. */
400 iowrite32(0x0000, ioaddr + CSR13);
401 iowrite32(0x0000, ioaddr + CSR14);
402 iowrite32(0x0008, ioaddr + CSR15);
403 }
404 tulip_select_media(dev, 1);
405 } else if (tp->chip_id == DC21142) {
406 if (tp->mii_cnt) {
407 tulip_select_media(dev, 1);
408 if (tulip_debug > 1)
409 printk(KERN_INFO "%s: Using MII transceiver %d, status "
410 "%4.4x.\n",
411 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
412 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
413 tp->csr6 = csr6_mask_hdcap;
414 dev->if_port = 11;
415 iowrite32(0x0000, ioaddr + CSR13);
416 iowrite32(0x0000, ioaddr + CSR14);
417 } else
418 t21142_start_nway(dev);
419 } else if (tp->chip_id == PNIC2) {
420 /* for initial startup advertise 10/100 Full and Half */
421 tp->sym_advertise = 0x01E0;
422 /* enable autonegotiate end interrupt */
423 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
424 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
425 pnic2_start_nway(dev);
426 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
427 if (tp->mii_cnt) {
428 dev->if_port = 11;
429 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
430 iowrite32(0x0001, ioaddr + CSR15);
431 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
432 pnic_do_nway(dev);
433 else {
434 /* Start with 10mbps to do autonegotiation. */
435 iowrite32(0x32, ioaddr + CSR12);
436 tp->csr6 = 0x00420000;
437 iowrite32(0x0001B078, ioaddr + 0xB8);
438 iowrite32(0x0201B078, ioaddr + 0xB8);
439 next_tick = 1*HZ;
440 }
441 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
442 && ! tp->medialock) {
443 dev->if_port = 0;
444 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
445 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
446 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
447 /* Provided by BOLO, Macronix - 12/10/1998. */
448 dev->if_port = 0;
449 tp->csr6 = 0x01a80200;
450 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
451 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
452 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
453 /* Enable automatic Tx underrun recovery. */
454 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
455 dev->if_port = tp->mii_cnt ? 11 : 0;
456 tp->csr6 = 0x00040000;
457 } else if (tp->chip_id == AX88140) {
458 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
459 } else
460 tulip_select_media(dev, 1);
461
462 /* Start the chip's Tx to process setup frame. */
463 tulip_stop_rxtx(tp);
464 barrier();
465 udelay(5);
466 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
467
468 /* Enable interrupts by setting the interrupt mask. */
469 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
470 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
471 tulip_start_rxtx(tp);
472 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
473
474 if (tulip_debug > 2) {
475 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
476 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
477 ioread32(ioaddr + CSR6));
478 }
479
480 /* Set the timer to switch to check for link beat and perhaps switch
481 to an alternate media type. */
482 tp->timer.expires = RUN_AT(next_tick);
483 add_timer(&tp->timer);
484#ifdef CONFIG_TULIP_NAPI
485 init_timer(&tp->oom_timer);
486 tp->oom_timer.data = (unsigned long)dev;
487 tp->oom_timer.function = oom_timer;
488#endif
489}
490
491static int
492tulip_open(struct net_device *dev)
493{
494 int retval;
495
496 if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev)))
497 return retval;
498
499 tulip_init_ring (dev);
500
501 tulip_up (dev);
502
503 netif_start_queue (dev);
504
505 return 0;
506}
507
508
509static void tulip_tx_timeout(struct net_device *dev)
510{
511 struct tulip_private *tp = netdev_priv(dev);
512 void __iomem *ioaddr = tp->base_addr;
513 unsigned long flags;
514
515 spin_lock_irqsave (&tp->lock, flags);
516
517 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
518 /* Do nothing -- the media monitor should handle this. */
519 if (tulip_debug > 1)
520 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
521 dev->name);
522 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
523 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
524 || tp->chip_id == DM910X || tp->chip_id == ULI526X) {
525 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
526 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
527 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
528 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
529 if ( ! tp->medialock && tp->mtable) {
530 do
531 --tp->cur_index;
532 while (tp->cur_index >= 0
533 && (tulip_media_cap[tp->mtable->mleaf[tp->cur_index].media]
534 & MediaIsFD));
535 if (--tp->cur_index < 0) {
536 /* We start again, but should instead look for default. */
537 tp->cur_index = tp->mtable->leafcount - 1;
538 }
539 tulip_select_media(dev, 0);
540 printk(KERN_WARNING "%s: transmit timed out, switching to %s "
541 "media.\n", dev->name, medianame[dev->if_port]);
542 }
543 } else if (tp->chip_id == PNIC2) {
544 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
545 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
546 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
547 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
548 } else {
549 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
550 "%8.8x, resetting...\n",
551 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
552 dev->if_port = 0;
553 }
554
555#if defined(way_too_many_messages)
556 if (tulip_debug > 3) {
557 int i;
558 for (i = 0; i < RX_RING_SIZE; i++) {
559 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
560 int j;
561 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
562 "%2.2x %2.2x %2.2x.\n",
563 i, (unsigned int)tp->rx_ring[i].status,
564 (unsigned int)tp->rx_ring[i].length,
565 (unsigned int)tp->rx_ring[i].buffer1,
566 (unsigned int)tp->rx_ring[i].buffer2,
567 buf[0], buf[1], buf[2]);
568 for (j = 0; buf[j] != 0xee && j < 1600; j++)
569 if (j < 100) printk(" %2.2x", buf[j]);
570 printk(" j=%d.\n", j);
571 }
572 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
573 for (i = 0; i < RX_RING_SIZE; i++)
574 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
575 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
576 for (i = 0; i < TX_RING_SIZE; i++)
577 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
578 printk("\n");
579 }
580#endif
581
582 /* Stop and restart the chip's Tx processes . */
583
584 tulip_restart_rxtx(tp);
585 /* Trigger an immediate transmit demand. */
586 iowrite32(0, ioaddr + CSR1);
587
588 tp->stats.tx_errors++;
589
590 spin_unlock_irqrestore (&tp->lock, flags);
591 dev->trans_start = jiffies;
592 netif_wake_queue (dev);
593}
594
595
596/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
597static void tulip_init_ring(struct net_device *dev)
598{
599 struct tulip_private *tp = netdev_priv(dev);
600 int i;
601
602 tp->susp_rx = 0;
603 tp->ttimer = 0;
604 tp->nir = 0;
605
606 for (i = 0; i < RX_RING_SIZE; i++) {
607 tp->rx_ring[i].status = 0x00000000;
608 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
609 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
610 tp->rx_buffers[i].skb = NULL;
611 tp->rx_buffers[i].mapping = 0;
612 }
613 /* Mark the last entry as wrapping the ring. */
614 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
615 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
616
617 for (i = 0; i < RX_RING_SIZE; i++) {
618 dma_addr_t mapping;
619
620 /* Note the receive buffer must be longword aligned.
621 dev_alloc_skb() provides 16 byte alignment. But do *not*
622 use skb_reserve() to align the IP header! */
623 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
624 tp->rx_buffers[i].skb = skb;
625 if (skb == NULL)
626 break;
627 mapping = pci_map_single(tp->pdev, skb->tail,
628 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
629 tp->rx_buffers[i].mapping = mapping;
630 skb->dev = dev; /* Mark as being used by this device. */
631 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
632 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
633 }
634 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
635
636 /* The Tx buffer descriptor is filled in as needed, but we
637 do need to clear the ownership bit. */
638 for (i = 0; i < TX_RING_SIZE; i++) {
639 tp->tx_buffers[i].skb = NULL;
640 tp->tx_buffers[i].mapping = 0;
641 tp->tx_ring[i].status = 0x00000000;
642 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
643 }
644 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
645}
646
647static int
648tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
649{
650 struct tulip_private *tp = netdev_priv(dev);
651 int entry;
652 u32 flag;
653 dma_addr_t mapping;
654
655 spin_lock_irq(&tp->lock);
656
657 /* Calculate the next Tx descriptor entry. */
658 entry = tp->cur_tx % TX_RING_SIZE;
659
660 tp->tx_buffers[entry].skb = skb;
661 mapping = pci_map_single(tp->pdev, skb->data,
662 skb->len, PCI_DMA_TODEVICE);
663 tp->tx_buffers[entry].mapping = mapping;
664 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
665
666 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
667 flag = 0x60000000; /* No interrupt */
668 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
669 flag = 0xe0000000; /* Tx-done intr. */
670 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
671 flag = 0x60000000; /* No Tx-done intr. */
672 } else { /* Leave room for set_rx_mode() to fill entries. */
673 flag = 0xe0000000; /* Tx-done intr. */
674 netif_stop_queue(dev);
675 }
676 if (entry == TX_RING_SIZE-1)
677 flag = 0xe0000000 | DESC_RING_WRAP;
678
679 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
680 /* if we were using Transmit Automatic Polling, we would need a
681 * wmb() here. */
682 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
683 wmb();
684
685 tp->cur_tx++;
686
687 /* Trigger an immediate transmit demand. */
688 iowrite32(0, tp->base_addr + CSR1);
689
690 spin_unlock_irq(&tp->lock);
691
692 dev->trans_start = jiffies;
693
694 return 0;
695}
696
697static void tulip_clean_tx_ring(struct tulip_private *tp)
698{
699 unsigned int dirty_tx;
700
701 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
702 dirty_tx++) {
703 int entry = dirty_tx % TX_RING_SIZE;
704 int status = le32_to_cpu(tp->tx_ring[entry].status);
705
706 if (status < 0) {
707 tp->stats.tx_errors++; /* It wasn't Txed */
708 tp->tx_ring[entry].status = 0;
709 }
710
711 /* Check for Tx filter setup frames. */
712 if (tp->tx_buffers[entry].skb == NULL) {
713 /* test because dummy frames not mapped */
714 if (tp->tx_buffers[entry].mapping)
715 pci_unmap_single(tp->pdev,
716 tp->tx_buffers[entry].mapping,
717 sizeof(tp->setup_frame),
718 PCI_DMA_TODEVICE);
719 continue;
720 }
721
722 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
723 tp->tx_buffers[entry].skb->len,
724 PCI_DMA_TODEVICE);
725
726 /* Free the original skb. */
727 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
728 tp->tx_buffers[entry].skb = NULL;
729 tp->tx_buffers[entry].mapping = 0;
730 }
731}
732
733static void tulip_down (struct net_device *dev)
734{
735 struct tulip_private *tp = netdev_priv(dev);
736 void __iomem *ioaddr = tp->base_addr;
737 unsigned long flags;
738
739 del_timer_sync (&tp->timer);
740#ifdef CONFIG_TULIP_NAPI
741 del_timer_sync (&tp->oom_timer);
742#endif
743 spin_lock_irqsave (&tp->lock, flags);
744
745 /* Disable interrupts by clearing the interrupt mask. */
746 iowrite32 (0x00000000, ioaddr + CSR7);
747
748 /* Stop the Tx and Rx processes. */
749 tulip_stop_rxtx(tp);
750
751 /* prepare receive buffers */
752 tulip_refill_rx(dev);
753
754 /* release any unconsumed transmit buffers */
755 tulip_clean_tx_ring(tp);
756
757 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
758 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
759
760 spin_unlock_irqrestore (&tp->lock, flags);
761
762 init_timer(&tp->timer);
763 tp->timer.data = (unsigned long)dev;
764 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
765
766 dev->if_port = tp->saved_if_port;
767
768 /* Leave the driver in snooze, not sleep, mode. */
769 tulip_set_power_state (tp, 0, 1);
770}
771
772
773static int tulip_close (struct net_device *dev)
774{
775 struct tulip_private *tp = netdev_priv(dev);
776 void __iomem *ioaddr = tp->base_addr;
777 int i;
778
779 netif_stop_queue (dev);
780
781 tulip_down (dev);
782
783 if (tulip_debug > 1)
784 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
785 dev->name, ioread32 (ioaddr + CSR5));
786
787 free_irq (dev->irq, dev);
788
789 /* Free all the skbuffs in the Rx queue. */
790 for (i = 0; i < RX_RING_SIZE; i++) {
791 struct sk_buff *skb = tp->rx_buffers[i].skb;
792 dma_addr_t mapping = tp->rx_buffers[i].mapping;
793
794 tp->rx_buffers[i].skb = NULL;
795 tp->rx_buffers[i].mapping = 0;
796
797 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
798 tp->rx_ring[i].length = 0;
799 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
800 if (skb) {
801 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
802 PCI_DMA_FROMDEVICE);
803 dev_kfree_skb (skb);
804 }
805 }
806 for (i = 0; i < TX_RING_SIZE; i++) {
807 struct sk_buff *skb = tp->tx_buffers[i].skb;
808
809 if (skb != NULL) {
810 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
811 skb->len, PCI_DMA_TODEVICE);
812 dev_kfree_skb (skb);
813 }
814 tp->tx_buffers[i].skb = NULL;
815 tp->tx_buffers[i].mapping = 0;
816 }
817
818 return 0;
819}
820
821static struct net_device_stats *tulip_get_stats(struct net_device *dev)
822{
823 struct tulip_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->base_addr;
825
826 if (netif_running(dev)) {
827 unsigned long flags;
828
829 spin_lock_irqsave (&tp->lock, flags);
830
831 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
832
833 spin_unlock_irqrestore(&tp->lock, flags);
834 }
835
836 return &tp->stats;
837}
838
839
840static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
841{
842 struct tulip_private *np = netdev_priv(dev);
843 strcpy(info->driver, DRV_NAME);
844 strcpy(info->version, DRV_VERSION);
845 strcpy(info->bus_info, pci_name(np->pdev));
846}
847
848static struct ethtool_ops ops = {
849 .get_drvinfo = tulip_get_drvinfo
850};
851
852/* Provide ioctl() calls to examine the MII xcvr state. */
853static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
854{
855 struct tulip_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->base_addr;
857 struct mii_ioctl_data *data = if_mii(rq);
858 const unsigned int phy_idx = 0;
859 int phy = tp->phys[phy_idx] & 0x1f;
860 unsigned int regnum = data->reg_num;
861
862 switch (cmd) {
863 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
864 if (tp->mii_cnt)
865 data->phy_id = phy;
866 else if (tp->flags & HAS_NWAY)
867 data->phy_id = 32;
868 else if (tp->chip_id == COMET)
869 data->phy_id = 1;
870 else
871 return -ENODEV;
872
873 case SIOCGMIIREG: /* Read MII PHY register. */
874 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
875 int csr12 = ioread32 (ioaddr + CSR12);
876 int csr14 = ioread32 (ioaddr + CSR14);
877 switch (regnum) {
878 case 0:
879 if (((csr14<<5) & 0x1000) ||
880 (dev->if_port == 5 && tp->nwayset))
881 data->val_out = 0x1000;
882 else
883 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
884 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
885 break;
886 case 1:
887 data->val_out =
888 0x1848 +
889 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
890 ((csr12&0x06) == 6 ? 0 : 4);
891 data->val_out |= 0x6048;
892 break;
893 case 4:
894 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
895 data->val_out =
896 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
897 ((csr14 >> 1) & 0x20) + 1;
898 data->val_out |= ((csr14 >> 9) & 0x03C0);
899 break;
900 case 5: data->val_out = tp->lpar; break;
901 default: data->val_out = 0; break;
902 }
903 } else {
904 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
905 }
906 return 0;
907
908 case SIOCSMIIREG: /* Write MII PHY register. */
909 if (!capable (CAP_NET_ADMIN))
910 return -EPERM;
911 if (regnum & ~0x1f)
912 return -EINVAL;
913 if (data->phy_id == phy) {
914 u16 value = data->val_in;
915 switch (regnum) {
916 case 0: /* Check for autonegotiation on or reset. */
917 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
918 if (tp->full_duplex_lock)
919 tp->full_duplex = (value & 0x0100) ? 1 : 0;
920 break;
921 case 4:
922 tp->advertising[phy_idx] =
923 tp->mii_advertise = data->val_in;
924 break;
925 }
926 }
927 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
928 u16 value = data->val_in;
929 if (regnum == 0) {
930 if ((value & 0x1200) == 0x1200) {
931 if (tp->chip_id == PNIC2) {
932 pnic2_start_nway (dev);
933 } else {
934 t21142_start_nway (dev);
935 }
936 }
937 } else if (regnum == 4)
938 tp->sym_advertise = value;
939 } else {
940 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
941 }
942 return 0;
943 default:
944 return -EOPNOTSUPP;
945 }
946
947 return -EOPNOTSUPP;
948}
949
950
951/* Set or clear the multicast filter for this adaptor.
952 Note that we only use exclusion around actually queueing the
953 new frame, not around filling tp->setup_frame. This is non-deterministic
954 when re-entered but still correct. */
955
956#undef set_bit_le
957#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
958
959static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
960{
961 struct tulip_private *tp = netdev_priv(dev);
962 u16 hash_table[32];
963 struct dev_mc_list *mclist;
964 int i;
965 u16 *eaddrs;
966
967 memset(hash_table, 0, sizeof(hash_table));
968 set_bit_le(255, hash_table); /* Broadcast entry */
969 /* This should work on big-endian machines as well. */
970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
971 i++, mclist = mclist->next) {
972 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
973
974 set_bit_le(index, hash_table);
975
976 }
977 for (i = 0; i < 32; i++) {
978 *setup_frm++ = hash_table[i];
979 *setup_frm++ = hash_table[i];
980 }
981 setup_frm = &tp->setup_frame[13*6];
982
983 /* Fill the final entry with our physical address. */
984 eaddrs = (u16 *)dev->dev_addr;
985 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
986 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
987 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
988}
989
990static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
991{
992 struct tulip_private *tp = netdev_priv(dev);
993 struct dev_mc_list *mclist;
994 int i;
995 u16 *eaddrs;
996
997 /* We have <= 14 addresses so we can use the wonderful
998 16 address perfect filtering of the Tulip. */
999 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1000 i++, mclist = mclist->next) {
1001 eaddrs = (u16 *)mclist->dmi_addr;
1002 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1003 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 }
1006 /* Fill the unused entries with the broadcast address. */
1007 memset(setup_frm, 0xff, (15-i)*12);
1008 setup_frm = &tp->setup_frame[15*6];
1009
1010 /* Fill the final entry with our physical address. */
1011 eaddrs = (u16 *)dev->dev_addr;
1012 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1013 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1014 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1015}
1016
1017
1018static void set_rx_mode(struct net_device *dev)
1019{
1020 struct tulip_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->base_addr;
1022 int csr6;
1023
1024 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1025
1026 tp->csr6 &= ~0x00D5;
1027 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1028 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1029 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1030 /* Unconditionally log net taps. */
1031 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1032 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1033 /* Too many to filter well -- accept all multicasts. */
1034 tp->csr6 |= AcceptAllMulticast;
1035 csr6 |= AcceptAllMulticast;
1036 } else if (tp->flags & MC_HASH_ONLY) {
1037 /* Some work-alikes have only a 64-entry hash filter table. */
1038 /* Should verify correctness on big-endian/__powerpc__ */
1039 struct dev_mc_list *mclist;
1040 int i;
1041 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1042 tp->csr6 |= AcceptAllMulticast;
1043 csr6 |= AcceptAllMulticast;
1044 } else {
1045 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1046 int filterbit;
1047 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1048 i++, mclist = mclist->next) {
1049 if (tp->flags & COMET_MAC_ADDR)
1050 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1051 else
1052 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1053 filterbit &= 0x3f;
1054 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1055 if (tulip_debug > 2) {
1056 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1057 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1058 mclist->dmi_addr[0], mclist->dmi_addr[1],
1059 mclist->dmi_addr[2], mclist->dmi_addr[3],
1060 mclist->dmi_addr[4], mclist->dmi_addr[5],
1061 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1062 }
1063 }
1064 if (mc_filter[0] == tp->mc_filter[0] &&
1065 mc_filter[1] == tp->mc_filter[1])
1066 ; /* No change. */
1067 else if (tp->flags & IS_ASIX) {
1068 iowrite32(2, ioaddr + CSR13);
1069 iowrite32(mc_filter[0], ioaddr + CSR14);
1070 iowrite32(3, ioaddr + CSR13);
1071 iowrite32(mc_filter[1], ioaddr + CSR14);
1072 } else if (tp->flags & COMET_MAC_ADDR) {
1073 iowrite32(mc_filter[0], ioaddr + 0xAC);
1074 iowrite32(mc_filter[1], ioaddr + 0xB0);
1075 }
1076 tp->mc_filter[0] = mc_filter[0];
1077 tp->mc_filter[1] = mc_filter[1];
1078 }
1079 } else {
1080 unsigned long flags;
1081 u32 tx_flags = 0x08000000 | 192;
1082
1083 /* Note that only the low-address shortword of setup_frame is valid!
1084 The values are doubled for big-endian architectures. */
1085 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1086 build_setup_frame_hash(tp->setup_frame, dev);
1087 tx_flags = 0x08400000 | 192;
1088 } else {
1089 build_setup_frame_perfect(tp->setup_frame, dev);
1090 }
1091
1092 spin_lock_irqsave(&tp->lock, flags);
1093
1094 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1095 /* Same setup recently queued, we need not add it. */
1096 } else {
1097 unsigned int entry;
1098 int dummy = -1;
1099
1100 /* Now add this frame to the Tx list. */
1101
1102 entry = tp->cur_tx++ % TX_RING_SIZE;
1103
1104 if (entry != 0) {
1105 /* Avoid a chip errata by prefixing a dummy entry. Don't do
1106 this on the ULI526X as it triggers a different problem */
1107 if (!(tp->chip_id == ULI526X && (tp->revision = 0x40 || tp->revision == 0x50))) {
1108 tp->tx_buffers[entry].skb = NULL;
1109 tp->tx_buffers[entry].mapping = 0;
1110 tp->tx_ring[entry].length =
1111 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1112 tp->tx_ring[entry].buffer1 = 0;
1113 /* Must set DescOwned later to avoid race with chip */
1114 dummy = entry;
1115 entry = tp->cur_tx++ % TX_RING_SIZE;
1116 }
1117 }
1118
1119 tp->tx_buffers[entry].skb = NULL;
1120 tp->tx_buffers[entry].mapping =
1121 pci_map_single(tp->pdev, tp->setup_frame,
1122 sizeof(tp->setup_frame),
1123 PCI_DMA_TODEVICE);
1124 /* Put the setup frame on the Tx list. */
1125 if (entry == TX_RING_SIZE-1)
1126 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1127 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1128 tp->tx_ring[entry].buffer1 =
1129 cpu_to_le32(tp->tx_buffers[entry].mapping);
1130 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1131 if (dummy >= 0)
1132 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1133 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1134 netif_stop_queue(dev);
1135
1136 /* Trigger an immediate transmit demand. */
1137 iowrite32(0, ioaddr + CSR1);
1138 }
1139
1140 spin_unlock_irqrestore(&tp->lock, flags);
1141 }
1142
1143 iowrite32(csr6, ioaddr + CSR6);
1144}
1145
1146#ifdef CONFIG_TULIP_MWI
1147static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1148 struct net_device *dev)
1149{
1150 struct tulip_private *tp = netdev_priv(dev);
1151 u8 cache;
1152 u16 pci_command;
1153 u32 csr0;
1154
1155 if (tulip_debug > 3)
1156 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1157
1158 tp->csr0 = csr0 = 0;
1159
1160 /* if we have any cache line size at all, we can do MRM */
1161 csr0 |= MRM;
1162
1163 /* ...and barring hardware bugs, MWI */
1164 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1165 csr0 |= MWI;
1166
1167 /* set or disable MWI in the standard PCI command bit.
1168 * Check for the case where mwi is desired but not available
1169 */
1170 if (csr0 & MWI) pci_set_mwi(pdev);
1171 else pci_clear_mwi(pdev);
1172
1173 /* read result from hardware (in case bit refused to enable) */
1174 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1175 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1176 csr0 &= ~MWI;
1177
1178 /* if cache line size hardwired to zero, no MWI */
1179 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1180 if ((csr0 & MWI) && (cache == 0)) {
1181 csr0 &= ~MWI;
1182 pci_clear_mwi(pdev);
1183 }
1184
1185 /* assign per-cacheline-size cache alignment and
1186 * burst length values
1187 */
1188 switch (cache) {
1189 case 8:
1190 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1191 break;
1192 case 16:
1193 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1194 break;
1195 case 32:
1196 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1197 break;
1198 default:
1199 cache = 0;
1200 break;
1201 }
1202
1203 /* if we have a good cache line size, we by now have a good
1204 * csr0, so save it and exit
1205 */
1206 if (cache)
1207 goto out;
1208
1209 /* we don't have a good csr0 or cache line size, disable MWI */
1210 if (csr0 & MWI) {
1211 pci_clear_mwi(pdev);
1212 csr0 &= ~MWI;
1213 }
1214
1215 /* sane defaults for burst length and cache alignment
1216 * originally from de4x5 driver
1217 */
1218 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1219
1220out:
1221 tp->csr0 = csr0;
1222 if (tulip_debug > 2)
1223 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1224 pci_name(pdev), cache, csr0);
1225}
1226#endif
1227
1228/*
1229 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1230 * is the DM910X and the on chip ULi devices
1231 */
1232
1233static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1234{
1235 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1236 return 1;
1237 if (pdev->vendor == 0x10b9 && pdev->device == 0x5261)
1238 return 1;
1239 if (pdev->vendor == 0x10b9 && pdev->device == 0x5263)
1240 return 1;
1241 return 0;
1242}
1243
1244static int __devinit tulip_init_one (struct pci_dev *pdev,
1245 const struct pci_device_id *ent)
1246{
1247 struct tulip_private *tp;
1248 /* See note below on the multiport cards. */
1249 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1250 static struct pci_device_id early_486_chipsets[] = {
1251 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1252 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1253 { },
1254 };
1255 static int last_irq;
1256 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1257 u8 chip_rev;
1258 int i, irq;
1259 unsigned short sum;
1260 unsigned char *ee_data;
1261 struct net_device *dev;
1262 void __iomem *ioaddr;
1263 static int board_idx = -1;
1264 int chip_idx = ent->driver_data;
1265 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1266 unsigned int eeprom_missing = 0;
1267 unsigned int force_csr0 = 0;
1268
1269#ifndef MODULE
1270 static int did_version; /* Already printed version info. */
1271 if (tulip_debug > 0 && did_version++ == 0)
1272 printk (KERN_INFO "%s", version);
1273#endif
1274
1275 board_idx++;
1276
1277 /*
1278 * Lan media wire a tulip chip to a wan interface. Needs a very
1279 * different driver (lmc driver)
1280 */
1281
1282 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1283 printk (KERN_ERR PFX "skipping LMC card.\n");
1284 return -ENODEV;
1285 }
1286
1287 /*
1288 * Early DM9100's need software CRC and the DMFE driver
1289 */
1290
1291 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1292 {
1293 u32 dev_rev;
1294 /* Read Chip revision */
1295 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
1296 if(dev_rev < 0x02000030)
1297 {
1298 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1299 return -ENODEV;
1300 }
1301 }
1302
1303 /*
1304 * Looks for early PCI chipsets where people report hangs
1305 * without the workarounds being on.
1306 */
1307
1308 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1309 aligned. Aries might need this too. The Saturn errata are not
1310 pretty reading but thankfully it's an old 486 chipset.
1311
1312 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1313 Saturn.
1314 */
1315
1316 if (pci_dev_present(early_486_chipsets)) {
1317 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1318 force_csr0 = 1;
1319 }
1320
1321 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1322 if (chip_idx == AX88140) {
1323 if ((csr0 & 0x3f00) == 0)
1324 csr0 |= 0x2000;
1325 }
1326
1327 /* PNIC doesn't have MWI/MRL/MRM... */
1328 if (chip_idx == LC82C168)
1329 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1330
1331 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1332 if (tulip_uli_dm_quirk(pdev)) {
1333 csr0 &= ~0x01f100ff;
1334#if defined(__sparc__)
1335 csr0 = (csr0 & ~0xff00) | 0xe000;
1336#endif
1337 }
1338 /*
1339 * And back to business
1340 */
1341
1342 i = pci_enable_device(pdev);
1343 if (i) {
1344 printk (KERN_ERR PFX
1345 "Cannot enable tulip board #%d, aborting\n",
1346 board_idx);
1347 return i;
1348 }
1349
1350 irq = pdev->irq;
1351
1352 /* alloc_etherdev ensures aligned and zeroed private structures */
1353 dev = alloc_etherdev (sizeof (*tp));
1354 if (!dev) {
1355 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1356 return -ENOMEM;
1357 }
1358
1359 SET_MODULE_OWNER(dev);
1360 SET_NETDEV_DEV(dev, &pdev->dev);
1361 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1362 printk (KERN_ERR PFX "%s: I/O region (0x%lx@0x%lx) too small, "
1363 "aborting\n", pci_name(pdev),
1364 pci_resource_len (pdev, 0),
1365 pci_resource_start (pdev, 0));
1366 goto err_out_free_netdev;
1367 }
1368
1369 /* grab all resources from both PIO and MMIO regions, as we
1370 * don't want anyone else messing around with our hardware */
1371 if (pci_request_regions (pdev, "tulip"))
1372 goto err_out_free_netdev;
1373
1374#ifndef USE_IO_OPS
1375 ioaddr = pci_iomap(pdev, 1, tulip_tbl[chip_idx].io_size);
1376#else
1377 ioaddr = pci_iomap(pdev, 0, tulip_tbl[chip_idx].io_size);
1378#endif
1379 if (!ioaddr)
1380 goto err_out_free_res;
1381
1382 pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
1383
1384 /*
1385 * initialize private data structure 'tp'
1386 * it is zeroed and aligned in alloc_etherdev
1387 */
1388 tp = netdev_priv(dev);
1389
1390 tp->rx_ring = pci_alloc_consistent(pdev,
1391 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1392 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1393 &tp->rx_ring_dma);
1394 if (!tp->rx_ring)
1395 goto err_out_mtable;
1396 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1397 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1398
1399 tp->chip_id = chip_idx;
1400 tp->flags = tulip_tbl[chip_idx].flags;
1401 tp->pdev = pdev;
1402 tp->base_addr = ioaddr;
1403 tp->revision = chip_rev;
1404 tp->csr0 = csr0;
1405 spin_lock_init(&tp->lock);
1406 spin_lock_init(&tp->mii_lock);
1407 init_timer(&tp->timer);
1408 tp->timer.data = (unsigned long)dev;
1409 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1410
1411 dev->base_addr = (unsigned long)ioaddr;
1412
1413#ifdef CONFIG_TULIP_MWI
1414 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1415 tulip_mwi_config (pdev, dev);
1416#else
1417 /* MWI is broken for DC21143 rev 65... */
1418 if (chip_idx == DC21143 && chip_rev == 65)
1419 tp->csr0 &= ~MWI;
1420#endif
1421
1422 /* Stop the chip's Tx and Rx processes. */
1423 tulip_stop_rxtx(tp);
1424
1425 pci_set_master(pdev);
1426
1427#ifdef CONFIG_GSC
1428 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1429 switch (pdev->subsystem_device) {
1430 default:
1431 break;
1432 case 0x1061:
1433 case 0x1062:
1434 case 0x1063:
1435 case 0x1098:
1436 case 0x1099:
1437 case 0x10EE:
1438 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1439 chip_name = "GSC DS21140 Tulip";
1440 }
1441 }
1442#endif
1443
1444 /* Clear the missed-packet counter. */
1445 ioread32(ioaddr + CSR8);
1446
1447 /* The station address ROM is read byte serially. The register must
1448 be polled, waiting for the value to be read bit serially from the
1449 EEPROM.
1450 */
1451 ee_data = tp->eeprom;
1452 sum = 0;
1453 if (chip_idx == LC82C168) {
1454 for (i = 0; i < 3; i++) {
1455 int value, boguscnt = 100000;
1456 iowrite32(0x600 | i, ioaddr + 0x98);
1457 do
1458 value = ioread32(ioaddr + CSR9);
1459 while (value < 0 && --boguscnt > 0);
1460 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1461 sum += value & 0xffff;
1462 }
1463 } else if (chip_idx == COMET) {
1464 /* No need to read the EEPROM. */
1465 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1466 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4));
1467 for (i = 0; i < 6; i ++)
1468 sum += dev->dev_addr[i];
1469 } else {
1470 /* A serial EEPROM interface, we read now and sort it out later. */
1471 int sa_offset = 0;
1472 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1473
1474 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1475 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1476 ee_data[i] = data & 0xff;
1477 ee_data[i + 1] = data >> 8;
1478 }
1479
1480 /* DEC now has a specification (see Notes) but early board makers
1481 just put the address in the first EEPROM locations. */
1482 /* This does memcmp(ee_data, ee_data+16, 8) */
1483 for (i = 0; i < 8; i ++)
1484 if (ee_data[i] != ee_data[16+i])
1485 sa_offset = 20;
1486 if (chip_idx == CONEXANT) {
1487 /* Check that the tuple type and length is correct. */
1488 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1489 sa_offset = 0x19A;
1490 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1491 ee_data[2] == 0) {
1492 sa_offset = 2; /* Grrr, damn Matrox boards. */
1493 multiport_cnt = 4;
1494 }
1495#ifdef CONFIG_DDB5476
1496 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
1497 /* DDB5476 MAC address in first EEPROM locations. */
1498 sa_offset = 0;
1499 /* No media table either */
1500 tp->flags &= ~HAS_MEDIA_TABLE;
1501 }
1502#endif
1503#ifdef CONFIG_DDB5477
1504 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1505 /* DDB5477 MAC address in first EEPROM locations. */
1506 sa_offset = 0;
1507 /* No media table either */
1508 tp->flags &= ~HAS_MEDIA_TABLE;
1509 }
1510#endif
1511#ifdef CONFIG_MIPS_COBALT
1512 if ((pdev->bus->number == 0) &&
1513 ((PCI_SLOT(pdev->devfn) == 7) ||
1514 (PCI_SLOT(pdev->devfn) == 12))) {
1515 /* Cobalt MAC address in first EEPROM locations. */
1516 sa_offset = 0;
1517 /* No media table either */
1518 tp->flags &= ~HAS_MEDIA_TABLE;
1519 }
1520#endif
1521#ifdef CONFIG_GSC
1522 /* Check to see if we have a broken srom */
1523 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1524 /* pci_vendor_id and subsystem_id are swapped */
1525 ee_data[0] = ee_data[2];
1526 ee_data[1] = ee_data[3];
1527 ee_data[2] = 0x61;
1528 ee_data[3] = 0x10;
1529
1530 /* HSC-PCI boards need to be byte-swaped and shifted
1531 * up 1 word. This shift needs to happen at the end
1532 * of the MAC first because of the 2 byte overlap.
1533 */
1534 for (i = 4; i >= 0; i -= 2) {
1535 ee_data[17 + i + 3] = ee_data[17 + i];
1536 ee_data[16 + i + 5] = ee_data[16 + i];
1537 }
1538 }
1539#endif
1540
1541 for (i = 0; i < 6; i ++) {
1542 dev->dev_addr[i] = ee_data[i + sa_offset];
1543 sum += ee_data[i + sa_offset];
1544 }
1545 }
1546 /* Lite-On boards have the address byte-swapped. */
1547 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1548 && dev->dev_addr[1] == 0x00)
1549 for (i = 0; i < 6; i+=2) {
1550 char tmp = dev->dev_addr[i];
1551 dev->dev_addr[i] = dev->dev_addr[i+1];
1552 dev->dev_addr[i+1] = tmp;
1553 }
1554 /* On the Zynx 315 Etherarray and other multiport boards only the
1555 first Tulip has an EEPROM.
1556 On Sparc systems the mac address is held in the OBP property
1557 "local-mac-address".
1558 The addresses of the subsequent ports are derived from the first.
1559 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1560 that here as well. */
1561 if (sum == 0 || sum == 6*0xff) {
1562#if defined(__sparc__)
1563 struct pcidev_cookie *pcp = pdev->sysdata;
1564#endif
1565 eeprom_missing = 1;
1566 for (i = 0; i < 5; i++)
1567 dev->dev_addr[i] = last_phys_addr[i];
1568 dev->dev_addr[i] = last_phys_addr[i] + 1;
1569#if defined(__sparc__)
1570 if ((pcp != NULL) && prom_getproplen(pcp->prom_node,
1571 "local-mac-address") == 6) {
1572 prom_getproperty(pcp->prom_node, "local-mac-address",
1573 dev->dev_addr, 6);
1574 }
1575#endif
1576#if defined(__i386__) /* Patch up x86 BIOS bug. */
1577 if (last_irq)
1578 irq = last_irq;
1579#endif
1580 }
1581
1582 for (i = 0; i < 6; i++)
1583 last_phys_addr[i] = dev->dev_addr[i];
1584 last_irq = irq;
1585 dev->irq = irq;
1586
1587 /* The lower four bits are the media type. */
1588 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1589 if (options[board_idx] & MEDIA_MASK)
1590 tp->default_port = options[board_idx] & MEDIA_MASK;
1591 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1592 tp->full_duplex = 1;
1593 if (mtu[board_idx] > 0)
1594 dev->mtu = mtu[board_idx];
1595 }
1596 if (dev->mem_start & MEDIA_MASK)
1597 tp->default_port = dev->mem_start & MEDIA_MASK;
1598 if (tp->default_port) {
1599 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1600 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1601 tp->medialock = 1;
1602 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1603 tp->full_duplex = 1;
1604 }
1605 if (tp->full_duplex)
1606 tp->full_duplex_lock = 1;
1607
1608 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1609 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1610 tp->mii_advertise = media2advert[tp->default_port - 9];
1611 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1612 }
1613
1614 if (tp->flags & HAS_MEDIA_TABLE) {
1615 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1616 tulip_parse_eeprom(dev);
1617 strcpy(dev->name, "eth%d"); /* un-hack */
1618 }
1619
1620 if ((tp->flags & ALWAYS_CHECK_MII) ||
1621 (tp->mtable && tp->mtable->has_mii) ||
1622 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1623 if (tp->mtable && tp->mtable->has_mii) {
1624 for (i = 0; i < tp->mtable->leafcount; i++)
1625 if (tp->mtable->mleaf[i].media == 11) {
1626 tp->cur_index = i;
1627 tp->saved_if_port = dev->if_port;
1628 tulip_select_media(dev, 2);
1629 dev->if_port = tp->saved_if_port;
1630 break;
1631 }
1632 }
1633
1634 /* Find the connected MII xcvrs.
1635 Doing this in open() would allow detecting external xcvrs
1636 later, but takes much time. */
1637 tulip_find_mii (dev, board_idx);
1638 }
1639
1640 /* The Tulip-specific entries in the device structure. */
1641 dev->open = tulip_open;
1642 dev->hard_start_xmit = tulip_start_xmit;
1643 dev->tx_timeout = tulip_tx_timeout;
1644 dev->watchdog_timeo = TX_TIMEOUT;
1645#ifdef CONFIG_TULIP_NAPI
1646 dev->poll = tulip_poll;
1647 dev->weight = 16;
1648#endif
1649 dev->stop = tulip_close;
1650 dev->get_stats = tulip_get_stats;
1651 dev->do_ioctl = private_ioctl;
1652 dev->set_multicast_list = set_rx_mode;
1653#ifdef CONFIG_NET_POLL_CONTROLLER
1654 dev->poll_controller = &poll_tulip;
1655#endif
1656 SET_ETHTOOL_OPS(dev, &ops);
1657
1658 if (register_netdev(dev))
1659 goto err_out_free_ring;
1660
1661 printk(KERN_INFO "%s: %s rev %d at %p,",
1662 dev->name, chip_name, chip_rev, ioaddr);
1663 pci_set_drvdata(pdev, dev);
1664
1665 if (eeprom_missing)
1666 printk(" EEPROM not present,");
1667 for (i = 0; i < 6; i++)
1668 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1669 printk(", IRQ %d.\n", irq);
1670
1671 if (tp->chip_id == PNIC2)
1672 tp->link_change = pnic2_lnk_change;
1673 else if (tp->flags & HAS_NWAY)
1674 tp->link_change = t21142_lnk_change;
1675 else if (tp->flags & HAS_PNICNWAY)
1676 tp->link_change = pnic_lnk_change;
1677
1678 /* Reset the xcvr interface and turn on heartbeat. */
1679 switch (chip_idx) {
1680 case DC21140:
1681 case DM910X:
1682 case ULI526X:
1683 default:
1684 if (tp->mtable)
1685 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1686 break;
1687 case DC21142:
1688 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1689 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1690 iowrite32(0x0000, ioaddr + CSR13);
1691 iowrite32(0x0000, ioaddr + CSR14);
1692 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1693 } else
1694 t21142_start_nway(dev);
1695 break;
1696 case PNIC2:
1697 /* just do a reset for sanity sake */
1698 iowrite32(0x0000, ioaddr + CSR13);
1699 iowrite32(0x0000, ioaddr + CSR14);
1700 break;
1701 case LC82C168:
1702 if ( ! tp->mii_cnt) {
1703 tp->nway = 1;
1704 tp->nwayset = 0;
1705 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1706 iowrite32(0x30, ioaddr + CSR12);
1707 iowrite32(0x0001F078, ioaddr + CSR6);
1708 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1709 }
1710 break;
1711 case MX98713:
1712 case COMPEX9881:
1713 iowrite32(0x00000000, ioaddr + CSR6);
1714 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1715 iowrite32(0x00000001, ioaddr + CSR13);
1716 break;
1717 case MX98715:
1718 case MX98725:
1719 iowrite32(0x01a80000, ioaddr + CSR6);
1720 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1721 iowrite32(0x00001000, ioaddr + CSR12);
1722 break;
1723 case COMET:
1724 /* No initialization necessary. */
1725 break;
1726 }
1727
1728 /* put the chip in snooze mode until opened */
1729 tulip_set_power_state (tp, 0, 1);
1730
1731 return 0;
1732
1733err_out_free_ring:
1734 pci_free_consistent (pdev,
1735 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1736 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1737 tp->rx_ring, tp->rx_ring_dma);
1738
1739err_out_mtable:
1740 if (tp->mtable)
1741 kfree (tp->mtable);
1742 pci_iounmap(pdev, ioaddr);
1743
1744err_out_free_res:
1745 pci_release_regions (pdev);
1746
1747err_out_free_netdev:
1748 free_netdev (dev);
1749 return -ENODEV;
1750}
1751
1752
1753#ifdef CONFIG_PM
1754
1755static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1756{
1757 struct net_device *dev = pci_get_drvdata(pdev);
1758
1759 if (dev && netif_running (dev) && netif_device_present (dev)) {
1760 netif_device_detach (dev);
1761 tulip_down (dev);
1762 /* pci_power_off(pdev, -1); */
1763 }
1764 return 0;
1765}
1766
1767
1768static int tulip_resume(struct pci_dev *pdev)
1769{
1770 struct net_device *dev = pci_get_drvdata(pdev);
1771
1772 if (dev && netif_running (dev) && !netif_device_present (dev)) {
1773#if 1
1774 pci_enable_device (pdev);
1775#endif
1776 /* pci_power_on(pdev); */
1777 tulip_up (dev);
1778 netif_device_attach (dev);
1779 }
1780 return 0;
1781}
1782
1783#endif /* CONFIG_PM */
1784
1785
1786static void __devexit tulip_remove_one (struct pci_dev *pdev)
1787{
1788 struct net_device *dev = pci_get_drvdata (pdev);
1789 struct tulip_private *tp;
1790
1791 if (!dev)
1792 return;
1793
1794 tp = netdev_priv(dev);
1795 unregister_netdev(dev);
1796 pci_free_consistent (pdev,
1797 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1798 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1799 tp->rx_ring, tp->rx_ring_dma);
1800 if (tp->mtable)
1801 kfree (tp->mtable);
1802 pci_iounmap(pdev, tp->base_addr);
1803 free_netdev (dev);
1804 pci_release_regions (pdev);
1805 pci_set_drvdata (pdev, NULL);
1806
1807 /* pci_power_off (pdev, -1); */
1808}
1809
1810#ifdef CONFIG_NET_POLL_CONTROLLER
1811/*
1812 * Polling 'interrupt' - used by things like netconsole to send skbs
1813 * without having to re-enable interrupts. It's not called while
1814 * the interrupt routine is executing.
1815 */
1816
1817static void poll_tulip (struct net_device *dev)
1818{
1819 /* disable_irq here is not very nice, but with the lockless
1820 interrupt handler we have no other choice. */
1821 disable_irq(dev->irq);
1822 tulip_interrupt (dev->irq, dev, NULL);
1823 enable_irq(dev->irq);
1824}
1825#endif
1826
1827static struct pci_driver tulip_driver = {
1828 .name = DRV_NAME,
1829 .id_table = tulip_pci_tbl,
1830 .probe = tulip_init_one,
1831 .remove = __devexit_p(tulip_remove_one),
1832#ifdef CONFIG_PM
1833 .suspend = tulip_suspend,
1834 .resume = tulip_resume,
1835#endif /* CONFIG_PM */
1836};
1837
1838
1839static int __init tulip_init (void)
1840{
1841#ifdef MODULE
1842 printk (KERN_INFO "%s", version);
1843#endif
1844
1845 /* copy module parms into globals */
1846 tulip_rx_copybreak = rx_copybreak;
1847 tulip_max_interrupt_work = max_interrupt_work;
1848
1849 /* probe for and init boards */
1850 return pci_module_init (&tulip_driver);
1851}
1852
1853
1854static void __exit tulip_cleanup (void)
1855{
1856 pci_unregister_driver (&tulip_driver);
1857}
1858
1859
1860module_init(tulip_init);
1861module_exit(tulip_cleanup);
diff --git a/drivers/net/tulip/winbond-840.c b/drivers/net/tulip/winbond-840.c
new file mode 100644
index 000000000000..f7e64ee11b1d
--- /dev/null
+++ b/drivers/net/tulip/winbond-840.c
@@ -0,0 +1,1716 @@
1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
41
42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
46
47#define DRV_NAME "winbond-840"
48#define DRV_VERSION "1.01-d"
49#define DRV_RELDATE "Nov-17-2001"
50
51
52/* Automatically extracted configuration info:
53probe-func: winbond840_probe
54config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
55
56c-help-name: Winbond W89c840 PCI Ethernet support
57c-help-symbol: CONFIG_WINBOND_840
58c-help: This driver is for the Winbond W89c840 chip. It also works with
59c-help: the TX9882 chip on the Compex RL100-ATX board.
60c-help: More specific information and updates are available from
61c-help: http://www.scyld.com/network/drivers.html
62*/
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
68static int max_interrupt_work = 20;
69/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The '840 uses a 64 element hash table based on the Ethernet CRC. */
71static int multicast_filter_limit = 32;
72
73/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
74 Setting to > 1518 effectively disables this feature. */
75static int rx_copybreak;
76
77/* Used to pass the media type, etc.
78 Both 'options[]' and 'full_duplex[]' should exist for driver
79 interoperability.
80 The media type is usually passed in 'options[]'.
81*/
82#define MAX_UNITS 8 /* More are supported, limit only on options */
83static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
85
86/* Operational parameters that are set at compile time. */
87
88/* Keep the ring sizes a power of two for compile efficiency.
89 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */
93#define TX_RING_SIZE 16
94#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
95#define TX_QUEUE_LEN_RESTART 5
96#define RX_RING_SIZE 32
97
98#define TX_BUFLIMIT (1024-128)
99
100/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
101 To avoid overflowing we don't queue again until we have room for a
102 full-size packet.
103 */
104#define TX_FIFO_SIZE (2048)
105#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
106
107
108/* Operational parameters that usually are not changed. */
109/* Time in jiffies before concluding the transmitter is hung. */
110#define TX_TIMEOUT (2*HZ)
111
112#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
113
114/* Include files, designed to support most kernel versions 2.0.0 and later. */
115#include <linux/module.h>
116#include <linux/kernel.h>
117#include <linux/string.h>
118#include <linux/timer.h>
119#include <linux/errno.h>
120#include <linux/ioport.h>
121#include <linux/slab.h>
122#include <linux/interrupt.h>
123#include <linux/pci.h>
124#include <linux/netdevice.h>
125#include <linux/etherdevice.h>
126#include <linux/skbuff.h>
127#include <linux/init.h>
128#include <linux/delay.h>
129#include <linux/ethtool.h>
130#include <linux/mii.h>
131#include <linux/rtnetlink.h>
132#include <linux/crc32.h>
133#include <linux/bitops.h>
134#include <asm/uaccess.h>
135#include <asm/processor.h> /* Processor type for cache alignment. */
136#include <asm/io.h>
137#include <asm/irq.h>
138
139/* These identify the driver base version and may not be removed. */
140static char version[] __devinitdata =
141KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
142KERN_INFO " http://www.scyld.com/network/drivers.html\n";
143
144MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
145MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
146MODULE_LICENSE("GPL");
147MODULE_VERSION(DRV_VERSION);
148
149module_param(max_interrupt_work, int, 0);
150module_param(debug, int, 0);
151module_param(rx_copybreak, int, 0);
152module_param(multicast_filter_limit, int, 0);
153module_param_array(options, int, NULL, 0);
154module_param_array(full_duplex, int, NULL, 0);
155MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
156MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
157MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
158MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
159MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
160MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
161
162/*
163 Theory of Operation
164
165I. Board Compatibility
166
167This driver is for the Winbond w89c840 chip.
168
169II. Board-specific settings
170
171None.
172
173III. Driver operation
174
175This chip is very similar to the Digital 21*4* "Tulip" family. The first
176twelve registers and the descriptor format are nearly identical. Read a
177Tulip manual for operational details.
178
179A significant difference is that the multicast filter and station address are
180stored in registers rather than loaded through a pseudo-transmit packet.
181
182Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
183full-sized packet we must use both data buffers in a descriptor. Thus the
184driver uses ring mode where descriptors are implicitly sequential in memory,
185rather than using the second descriptor address as a chain pointer to
186subsequent descriptors.
187
188IV. Notes
189
190If you are going to almost clone a Tulip, why not go all the way and avoid
191the need for a new driver?
192
193IVb. References
194
195http://www.scyld.com/expert/100mbps.html
196http://www.scyld.com/expert/NWay.html
197http://www.winbond.com.tw/
198
199IVc. Errata
200
201A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
202correctly detect a full FIFO, and queuing more than 2048 bytes may result in
203silent data corruption.
204
205Test with 'ping -s 10000' on a fast computer.
206
207*/
208
209
210
211/*
212 PCI probe table.
213*/
214enum pci_id_flags_bits {
215 /* Set PCI command register bits before calling probe1(). */
216 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
217 /* Read and map the single following PCI BAR. */
218 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
219 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
220};
221enum chip_capability_flags {
222 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,};
223#ifdef USE_IO_OPS
224#define W840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER)
225#else
226#define W840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER)
227#endif
228
229static struct pci_device_id w840_pci_tbl[] = {
230 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
231 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
232 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
233 { 0, }
234};
235MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
236
237struct pci_id_info {
238 const char *name;
239 struct match_info {
240 int pci, pci_mask, subsystem, subsystem_mask;
241 int revision, revision_mask; /* Only 8 bits. */
242 } id;
243 enum pci_id_flags_bits pci_flags;
244 int io_size; /* Needed for I/O region check or ioremap(). */
245 int drv_flags; /* Driver use, intended as capability flags. */
246};
247static struct pci_id_info pci_id_tbl[] = {
248 {"Winbond W89c840", /* Sometime a Level-One switch card. */
249 { 0x08401050, 0xffffffff, 0x81530000, 0xffff0000 },
250 W840_FLAGS, 128, CanHaveMII | HasBrokenTx | FDXOnNoMII},
251 {"Winbond W89c840", { 0x08401050, 0xffffffff, },
252 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
253 {"Compex RL100-ATX", { 0x201111F6, 0xffffffff,},
254 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
255 {NULL,}, /* 0 terminated list. */
256};
257
258/* This driver was written to use PCI memory space, however some x86 systems
259 work only with I/O space accesses. Pass -DUSE_IO_OPS to use PCI I/O space
260 accesses instead of memory space. */
261
262/* Offsets to the Command and Status Registers, "CSRs".
263 While similar to the Tulip, these registers are longword aligned.
264 Note: It's not useful to define symbolic names for every register bit in
265 the device. The name can only partially document the semantics and make
266 the driver longer and more difficult to read.
267*/
268enum w840_offsets {
269 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
270 RxRingPtr=0x0C, TxRingPtr=0x10,
271 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
272 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
273 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
274 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
275 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
276};
277
278/* Bits in the interrupt status/enable registers. */
279/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
280enum intr_status_bits {
281 NormalIntr=0x10000, AbnormalIntr=0x8000,
282 IntrPCIErr=0x2000, TimerInt=0x800,
283 IntrRxDied=0x100, RxNoBuf=0x80, IntrRxDone=0x40,
284 TxFIFOUnderflow=0x20, RxErrIntr=0x10,
285 TxIdle=0x04, IntrTxStopped=0x02, IntrTxDone=0x01,
286};
287
288/* Bits in the NetworkConfig register. */
289enum rx_mode_bits {
290 AcceptErr=0x80, AcceptRunt=0x40,
291 AcceptBroadcast=0x20, AcceptMulticast=0x10,
292 AcceptAllPhys=0x08, AcceptMyPhys=0x02,
293};
294
295enum mii_reg_bits {
296 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
297 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
298};
299
300/* The Tulip Rx and Tx buffer descriptors. */
301struct w840_rx_desc {
302 s32 status;
303 s32 length;
304 u32 buffer1;
305 u32 buffer2;
306};
307
308struct w840_tx_desc {
309 s32 status;
310 s32 length;
311 u32 buffer1, buffer2;
312};
313
314/* Bits in network_desc.status */
315enum desc_status_bits {
316 DescOwn=0x80000000, DescEndRing=0x02000000, DescUseLink=0x01000000,
317 DescWholePkt=0x60000000, DescStartPkt=0x20000000, DescEndPkt=0x40000000,
318 DescIntr=0x80000000,
319};
320
321#define MII_CNT 1 /* winbond only supports one MII */
322struct netdev_private {
323 struct w840_rx_desc *rx_ring;
324 dma_addr_t rx_addr[RX_RING_SIZE];
325 struct w840_tx_desc *tx_ring;
326 dma_addr_t tx_addr[TX_RING_SIZE];
327 dma_addr_t ring_dma_addr;
328 /* The addresses of receive-in-place skbuffs. */
329 struct sk_buff* rx_skbuff[RX_RING_SIZE];
330 /* The saved address of a sent-in-place packet/buffer, for later free(). */
331 struct sk_buff* tx_skbuff[TX_RING_SIZE];
332 struct net_device_stats stats;
333 struct timer_list timer; /* Media monitoring timer. */
334 /* Frequently used values: keep some adjacent for cache effect. */
335 spinlock_t lock;
336 int chip_id, drv_flags;
337 struct pci_dev *pci_dev;
338 int csr6;
339 struct w840_rx_desc *rx_head_desc;
340 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
341 unsigned int rx_buf_sz; /* Based on MTU+slack. */
342 unsigned int cur_tx, dirty_tx;
343 unsigned int tx_q_bytes;
344 unsigned int tx_full; /* The Tx queue is full. */
345 /* MII transceiver section. */
346 int mii_cnt; /* MII device addresses. */
347 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
348 u32 mii;
349 struct mii_if_info mii_if;
350 void __iomem *base_addr;
351};
352
353static int eeprom_read(void __iomem *ioaddr, int location);
354static int mdio_read(struct net_device *dev, int phy_id, int location);
355static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
356static int netdev_open(struct net_device *dev);
357static int update_link(struct net_device *dev);
358static void netdev_timer(unsigned long data);
359static void init_rxtx_rings(struct net_device *dev);
360static void free_rxtx_rings(struct netdev_private *np);
361static void init_registers(struct net_device *dev);
362static void tx_timeout(struct net_device *dev);
363static int alloc_ringdesc(struct net_device *dev);
364static void free_ringdesc(struct netdev_private *np);
365static int start_tx(struct sk_buff *skb, struct net_device *dev);
366static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
367static void netdev_error(struct net_device *dev, int intr_status);
368static int netdev_rx(struct net_device *dev);
369static u32 __set_rx_mode(struct net_device *dev);
370static void set_rx_mode(struct net_device *dev);
371static struct net_device_stats *get_stats(struct net_device *dev);
372static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
373static struct ethtool_ops netdev_ethtool_ops;
374static int netdev_close(struct net_device *dev);
375
376
377
378static int __devinit w840_probe1 (struct pci_dev *pdev,
379 const struct pci_device_id *ent)
380{
381 struct net_device *dev;
382 struct netdev_private *np;
383 static int find_cnt;
384 int chip_idx = ent->driver_data;
385 int irq;
386 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
387 void __iomem *ioaddr;
388 int bar = 1;
389
390 i = pci_enable_device(pdev);
391 if (i) return i;
392
393 pci_set_master(pdev);
394
395 irq = pdev->irq;
396
397 if (pci_set_dma_mask(pdev,0xFFFFffff)) {
398 printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n",
399 pci_name(pdev));
400 return -EIO;
401 }
402 dev = alloc_etherdev(sizeof(*np));
403 if (!dev)
404 return -ENOMEM;
405 SET_MODULE_OWNER(dev);
406 SET_NETDEV_DEV(dev, &pdev->dev);
407
408 if (pci_request_regions(pdev, DRV_NAME))
409 goto err_out_netdev;
410#ifdef USE_IO_OPS
411 bar = 0;
412#endif
413 ioaddr = pci_iomap(pdev, bar, pci_id_tbl[chip_idx].io_size);
414 if (!ioaddr)
415 goto err_out_free_res;
416
417 for (i = 0; i < 3; i++)
418 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(eeprom_read(ioaddr, i));
419
420 /* Reset the chip to erase previous misconfiguration.
421 No hold time required! */
422 iowrite32(0x00000001, ioaddr + PCIBusCfg);
423
424 dev->base_addr = (unsigned long)ioaddr;
425 dev->irq = irq;
426
427 np = netdev_priv(dev);
428 np->pci_dev = pdev;
429 np->chip_id = chip_idx;
430 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
431 spin_lock_init(&np->lock);
432 np->mii_if.dev = dev;
433 np->mii_if.mdio_read = mdio_read;
434 np->mii_if.mdio_write = mdio_write;
435 np->base_addr = ioaddr;
436
437 pci_set_drvdata(pdev, dev);
438
439 if (dev->mem_start)
440 option = dev->mem_start;
441
442 /* The lower four bits are the media type. */
443 if (option > 0) {
444 if (option & 0x200)
445 np->mii_if.full_duplex = 1;
446 if (option & 15)
447 printk(KERN_INFO "%s: ignoring user supplied media type %d",
448 dev->name, option & 15);
449 }
450 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
451 np->mii_if.full_duplex = 1;
452
453 if (np->mii_if.full_duplex)
454 np->mii_if.force_media = 1;
455
456 /* The chip-specific entries in the device structure. */
457 dev->open = &netdev_open;
458 dev->hard_start_xmit = &start_tx;
459 dev->stop = &netdev_close;
460 dev->get_stats = &get_stats;
461 dev->set_multicast_list = &set_rx_mode;
462 dev->do_ioctl = &netdev_ioctl;
463 dev->ethtool_ops = &netdev_ethtool_ops;
464 dev->tx_timeout = &tx_timeout;
465 dev->watchdog_timeo = TX_TIMEOUT;
466
467 i = register_netdev(dev);
468 if (i)
469 goto err_out_cleardev;
470
471 printk(KERN_INFO "%s: %s at %p, ",
472 dev->name, pci_id_tbl[chip_idx].name, ioaddr);
473 for (i = 0; i < 5; i++)
474 printk("%2.2x:", dev->dev_addr[i]);
475 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
476
477 if (np->drv_flags & CanHaveMII) {
478 int phy, phy_idx = 0;
479 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
480 int mii_status = mdio_read(dev, phy, MII_BMSR);
481 if (mii_status != 0xffff && mii_status != 0x0000) {
482 np->phys[phy_idx++] = phy;
483 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
484 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
485 mdio_read(dev, phy, MII_PHYSID2);
486 printk(KERN_INFO "%s: MII PHY %8.8xh found at address %d, status "
487 "0x%4.4x advertising %4.4x.\n",
488 dev->name, np->mii, phy, mii_status, np->mii_if.advertising);
489 }
490 }
491 np->mii_cnt = phy_idx;
492 np->mii_if.phy_id = np->phys[0];
493 if (phy_idx == 0) {
494 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
495 "not operate correctly.\n", dev->name);
496 }
497 }
498
499 find_cnt++;
500 return 0;
501
502err_out_cleardev:
503 pci_set_drvdata(pdev, NULL);
504 pci_iounmap(pdev, ioaddr);
505err_out_free_res:
506 pci_release_regions(pdev);
507err_out_netdev:
508 free_netdev (dev);
509 return -ENODEV;
510}
511
512
513/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
514 often serial bit streams generated by the host processor.
515 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
516
517/* Delay between EEPROM clock transitions.
518 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
519 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
520 made udelay() unreliable.
521 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
522 depricated.
523*/
524#define eeprom_delay(ee_addr) ioread32(ee_addr)
525
526enum EEPROM_Ctrl_Bits {
527 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
528 EE_ChipSelect=0x801, EE_DataIn=0x08,
529};
530
531/* The EEPROM commands include the alway-set leading bit. */
532enum EEPROM_Cmds {
533 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
534};
535
536static int eeprom_read(void __iomem *addr, int location)
537{
538 int i;
539 int retval = 0;
540 void __iomem *ee_addr = addr + EECtrl;
541 int read_cmd = location | EE_ReadCmd;
542 iowrite32(EE_ChipSelect, ee_addr);
543
544 /* Shift the read command bits out. */
545 for (i = 10; i >= 0; i--) {
546 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
547 iowrite32(dataval, ee_addr);
548 eeprom_delay(ee_addr);
549 iowrite32(dataval | EE_ShiftClk, ee_addr);
550 eeprom_delay(ee_addr);
551 }
552 iowrite32(EE_ChipSelect, ee_addr);
553 eeprom_delay(ee_addr);
554
555 for (i = 16; i > 0; i--) {
556 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
557 eeprom_delay(ee_addr);
558 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
559 iowrite32(EE_ChipSelect, ee_addr);
560 eeprom_delay(ee_addr);
561 }
562
563 /* Terminate the EEPROM access. */
564 iowrite32(0, ee_addr);
565 return retval;
566}
567
568/* MII transceiver control section.
569 Read and write the MII registers using software-generated serial
570 MDIO protocol. See the MII specifications or DP83840A data sheet
571 for details.
572
573 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
574 met by back-to-back 33Mhz PCI cycles. */
575#define mdio_delay(mdio_addr) ioread32(mdio_addr)
576
577/* Set iff a MII transceiver on any interface requires mdio preamble.
578 This only set with older transceivers, so the extra
579 code size of a per-interface flag is not worthwhile. */
580static char mii_preamble_required = 1;
581
582#define MDIO_WRITE0 (MDIO_EnbOutput)
583#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
584
585/* Generate the preamble required for initial synchronization and
586 a few older transceivers. */
587static void mdio_sync(void __iomem *mdio_addr)
588{
589 int bits = 32;
590
591 /* Establish sync by sending at least 32 logic ones. */
592 while (--bits >= 0) {
593 iowrite32(MDIO_WRITE1, mdio_addr);
594 mdio_delay(mdio_addr);
595 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
596 mdio_delay(mdio_addr);
597 }
598}
599
600static int mdio_read(struct net_device *dev, int phy_id, int location)
601{
602 struct netdev_private *np = netdev_priv(dev);
603 void __iomem *mdio_addr = np->base_addr + MIICtrl;
604 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
605 int i, retval = 0;
606
607 if (mii_preamble_required)
608 mdio_sync(mdio_addr);
609
610 /* Shift the read command bits out. */
611 for (i = 15; i >= 0; i--) {
612 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
613
614 iowrite32(dataval, mdio_addr);
615 mdio_delay(mdio_addr);
616 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
617 mdio_delay(mdio_addr);
618 }
619 /* Read the two transition, 16 data, and wire-idle bits. */
620 for (i = 20; i > 0; i--) {
621 iowrite32(MDIO_EnbIn, mdio_addr);
622 mdio_delay(mdio_addr);
623 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
624 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
625 mdio_delay(mdio_addr);
626 }
627 return (retval>>1) & 0xffff;
628}
629
630static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
631{
632 struct netdev_private *np = netdev_priv(dev);
633 void __iomem *mdio_addr = np->base_addr + MIICtrl;
634 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
635 int i;
636
637 if (location == 4 && phy_id == np->phys[0])
638 np->mii_if.advertising = value;
639
640 if (mii_preamble_required)
641 mdio_sync(mdio_addr);
642
643 /* Shift the command bits out. */
644 for (i = 31; i >= 0; i--) {
645 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
646
647 iowrite32(dataval, mdio_addr);
648 mdio_delay(mdio_addr);
649 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
650 mdio_delay(mdio_addr);
651 }
652 /* Clear out extra bits. */
653 for (i = 2; i > 0; i--) {
654 iowrite32(MDIO_EnbIn, mdio_addr);
655 mdio_delay(mdio_addr);
656 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
657 mdio_delay(mdio_addr);
658 }
659 return;
660}
661
662
663static int netdev_open(struct net_device *dev)
664{
665 struct netdev_private *np = netdev_priv(dev);
666 void __iomem *ioaddr = np->base_addr;
667 int i;
668
669 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
670
671 netif_device_detach(dev);
672 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
673 if (i)
674 goto out_err;
675
676 if (debug > 1)
677 printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n",
678 dev->name, dev->irq);
679
680 if((i=alloc_ringdesc(dev)))
681 goto out_err;
682
683 spin_lock_irq(&np->lock);
684 netif_device_attach(dev);
685 init_registers(dev);
686 spin_unlock_irq(&np->lock);
687
688 netif_start_queue(dev);
689 if (debug > 2)
690 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
691
692 /* Set the timer to check for link beat. */
693 init_timer(&np->timer);
694 np->timer.expires = jiffies + 1*HZ;
695 np->timer.data = (unsigned long)dev;
696 np->timer.function = &netdev_timer; /* timer handler */
697 add_timer(&np->timer);
698 return 0;
699out_err:
700 netif_device_attach(dev);
701 return i;
702}
703
704#define MII_DAVICOM_DM9101 0x0181b800
705
706static int update_link(struct net_device *dev)
707{
708 struct netdev_private *np = netdev_priv(dev);
709 int duplex, fasteth, result, mii_reg;
710
711 /* BSMR */
712 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
713
714 if (mii_reg == 0xffff)
715 return np->csr6;
716 /* reread: the link status bit is sticky */
717 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
718 if (!(mii_reg & 0x4)) {
719 if (netif_carrier_ok(dev)) {
720 if (debug)
721 printk(KERN_INFO "%s: MII #%d reports no link. Disabling watchdog.\n",
722 dev->name, np->phys[0]);
723 netif_carrier_off(dev);
724 }
725 return np->csr6;
726 }
727 if (!netif_carrier_ok(dev)) {
728 if (debug)
729 printk(KERN_INFO "%s: MII #%d link is back. Enabling watchdog.\n",
730 dev->name, np->phys[0]);
731 netif_carrier_on(dev);
732 }
733
734 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
735 /* If the link partner doesn't support autonegotiation
736 * the MII detects it's abilities with the "parallel detection".
737 * Some MIIs update the LPA register to the result of the parallel
738 * detection, some don't.
739 * The Davicom PHY [at least 0181b800] doesn't.
740 * Instead bit 9 and 13 of the BMCR are updated to the result
741 * of the negotiation..
742 */
743 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
744 duplex = mii_reg & BMCR_FULLDPLX;
745 fasteth = mii_reg & BMCR_SPEED100;
746 } else {
747 int negotiated;
748 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
749 negotiated = mii_reg & np->mii_if.advertising;
750
751 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
752 fasteth = negotiated & 0x380;
753 }
754 duplex |= np->mii_if.force_media;
755 /* remove fastether and fullduplex */
756 result = np->csr6 & ~0x20000200;
757 if (duplex)
758 result |= 0x200;
759 if (fasteth)
760 result |= 0x20000000;
761 if (result != np->csr6 && debug)
762 printk(KERN_INFO "%s: Setting %dMBit-%s-duplex based on MII#%d\n",
763 dev->name, fasteth ? 100 : 10,
764 duplex ? "full" : "half", np->phys[0]);
765 return result;
766}
767
768#define RXTX_TIMEOUT 2000
769static inline void update_csr6(struct net_device *dev, int new)
770{
771 struct netdev_private *np = netdev_priv(dev);
772 void __iomem *ioaddr = np->base_addr;
773 int limit = RXTX_TIMEOUT;
774
775 if (!netif_device_present(dev))
776 new = 0;
777 if (new==np->csr6)
778 return;
779 /* stop both Tx and Rx processes */
780 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
781 /* wait until they have really stopped */
782 for (;;) {
783 int csr5 = ioread32(ioaddr + IntrStatus);
784 int t;
785
786 t = (csr5 >> 17) & 0x07;
787 if (t==0||t==1) {
788 /* rx stopped */
789 t = (csr5 >> 20) & 0x07;
790 if (t==0||t==1)
791 break;
792 }
793
794 limit--;
795 if(!limit) {
796 printk(KERN_INFO "%s: couldn't stop rxtx, IntrStatus %xh.\n",
797 dev->name, csr5);
798 break;
799 }
800 udelay(1);
801 }
802 np->csr6 = new;
803 /* and restart them with the new configuration */
804 iowrite32(np->csr6, ioaddr + NetworkConfig);
805 if (new & 0x200)
806 np->mii_if.full_duplex = 1;
807}
808
809static void netdev_timer(unsigned long data)
810{
811 struct net_device *dev = (struct net_device *)data;
812 struct netdev_private *np = netdev_priv(dev);
813 void __iomem *ioaddr = np->base_addr;
814
815 if (debug > 2)
816 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
817 "config %8.8x.\n",
818 dev->name, ioread32(ioaddr + IntrStatus),
819 ioread32(ioaddr + NetworkConfig));
820 spin_lock_irq(&np->lock);
821 update_csr6(dev, update_link(dev));
822 spin_unlock_irq(&np->lock);
823 np->timer.expires = jiffies + 10*HZ;
824 add_timer(&np->timer);
825}
826
827static void init_rxtx_rings(struct net_device *dev)
828{
829 struct netdev_private *np = netdev_priv(dev);
830 int i;
831
832 np->rx_head_desc = &np->rx_ring[0];
833 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
834
835 /* Initial all Rx descriptors. */
836 for (i = 0; i < RX_RING_SIZE; i++) {
837 np->rx_ring[i].length = np->rx_buf_sz;
838 np->rx_ring[i].status = 0;
839 np->rx_skbuff[i] = NULL;
840 }
841 /* Mark the last entry as wrapping the ring. */
842 np->rx_ring[i-1].length |= DescEndRing;
843
844 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
845 for (i = 0; i < RX_RING_SIZE; i++) {
846 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
847 np->rx_skbuff[i] = skb;
848 if (skb == NULL)
849 break;
850 skb->dev = dev; /* Mark as being used by this device. */
851 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->tail,
852 skb->len,PCI_DMA_FROMDEVICE);
853
854 np->rx_ring[i].buffer1 = np->rx_addr[i];
855 np->rx_ring[i].status = DescOwn;
856 }
857
858 np->cur_rx = 0;
859 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
860
861 /* Initialize the Tx descriptors */
862 for (i = 0; i < TX_RING_SIZE; i++) {
863 np->tx_skbuff[i] = NULL;
864 np->tx_ring[i].status = 0;
865 }
866 np->tx_full = 0;
867 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
868
869 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
870 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
871 np->base_addr + TxRingPtr);
872
873}
874
875static void free_rxtx_rings(struct netdev_private* np)
876{
877 int i;
878 /* Free all the skbuffs in the Rx queue. */
879 for (i = 0; i < RX_RING_SIZE; i++) {
880 np->rx_ring[i].status = 0;
881 if (np->rx_skbuff[i]) {
882 pci_unmap_single(np->pci_dev,
883 np->rx_addr[i],
884 np->rx_skbuff[i]->len,
885 PCI_DMA_FROMDEVICE);
886 dev_kfree_skb(np->rx_skbuff[i]);
887 }
888 np->rx_skbuff[i] = NULL;
889 }
890 for (i = 0; i < TX_RING_SIZE; i++) {
891 if (np->tx_skbuff[i]) {
892 pci_unmap_single(np->pci_dev,
893 np->tx_addr[i],
894 np->tx_skbuff[i]->len,
895 PCI_DMA_TODEVICE);
896 dev_kfree_skb(np->tx_skbuff[i]);
897 }
898 np->tx_skbuff[i] = NULL;
899 }
900}
901
902static void init_registers(struct net_device *dev)
903{
904 struct netdev_private *np = netdev_priv(dev);
905 void __iomem *ioaddr = np->base_addr;
906 int i;
907
908 for (i = 0; i < 6; i++)
909 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
910
911 /* Initialize other registers. */
912#ifdef __BIG_ENDIAN
913 i = (1<<20); /* Big-endian descriptors */
914#else
915 i = 0;
916#endif
917 i |= (0x04<<2); /* skip length 4 u32 */
918 i |= 0x02; /* give Rx priority */
919
920 /* Configure the PCI bus bursts and FIFO thresholds.
921 486: Set 8 longword cache alignment, 8 longword burst.
922 586: Set 16 longword cache alignment, no burst limit.
923 Cache alignment bits 15:14 Burst length 13:8
924 0000 <not allowed> 0000 align to cache 0800 8 longwords
925 4000 8 longwords 0100 1 longword 1000 16 longwords
926 8000 16 longwords 0200 2 longwords 2000 32 longwords
927 C000 32 longwords 0400 4 longwords */
928
929#if defined (__i386__) && !defined(MODULE)
930 /* When not a module we can work around broken '486 PCI boards. */
931 if (boot_cpu_data.x86 <= 4) {
932 i |= 0x4800;
933 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
934 "alignment to 8 longwords.\n", dev->name);
935 } else {
936 i |= 0xE000;
937 }
938#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
939 i |= 0xE000;
940#elif defined(__sparc__)
941 i |= 0x4800;
942#else
943#warning Processor architecture undefined
944 i |= 0x4800;
945#endif
946 iowrite32(i, ioaddr + PCIBusCfg);
947
948 np->csr6 = 0;
949 /* 128 byte Tx threshold;
950 Transmit on; Receive on; */
951 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
952
953 /* Clear and Enable interrupts by setting the interrupt mask. */
954 iowrite32(0x1A0F5, ioaddr + IntrStatus);
955 iowrite32(0x1A0F5, ioaddr + IntrEnable);
956
957 iowrite32(0, ioaddr + RxStartDemand);
958}
959
960static void tx_timeout(struct net_device *dev)
961{
962 struct netdev_private *np = netdev_priv(dev);
963 void __iomem *ioaddr = np->base_addr;
964
965 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
966 " resetting...\n", dev->name, ioread32(ioaddr + IntrStatus));
967
968 {
969 int i;
970 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
971 for (i = 0; i < RX_RING_SIZE; i++)
972 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
973 printk("\n"KERN_DEBUG" Tx ring %p: ", np->tx_ring);
974 for (i = 0; i < TX_RING_SIZE; i++)
975 printk(" %8.8x", np->tx_ring[i].status);
976 printk("\n");
977 }
978 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n",
979 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
980 printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",ioread32(ioaddr+0x4C));
981
982 disable_irq(dev->irq);
983 spin_lock_irq(&np->lock);
984 /*
985 * Under high load dirty_tx and the internal tx descriptor pointer
986 * come out of sync, thus perform a software reset and reinitialize
987 * everything.
988 */
989
990 iowrite32(1, np->base_addr+PCIBusCfg);
991 udelay(1);
992
993 free_rxtx_rings(np);
994 init_rxtx_rings(dev);
995 init_registers(dev);
996 spin_unlock_irq(&np->lock);
997 enable_irq(dev->irq);
998
999 netif_wake_queue(dev);
1000 dev->trans_start = jiffies;
1001 np->stats.tx_errors++;
1002 return;
1003}
1004
1005/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1006static int alloc_ringdesc(struct net_device *dev)
1007{
1008 struct netdev_private *np = netdev_priv(dev);
1009
1010 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1011
1012 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1013 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
1014 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
1015 &np->ring_dma_addr);
1016 if(!np->rx_ring)
1017 return -ENOMEM;
1018 init_rxtx_rings(dev);
1019 return 0;
1020}
1021
1022static void free_ringdesc(struct netdev_private *np)
1023{
1024 pci_free_consistent(np->pci_dev,
1025 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
1026 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
1027 np->rx_ring, np->ring_dma_addr);
1028
1029}
1030
1031static int start_tx(struct sk_buff *skb, struct net_device *dev)
1032{
1033 struct netdev_private *np = netdev_priv(dev);
1034 unsigned entry;
1035
1036 /* Caution: the write order is important here, set the field
1037 with the "ownership" bits last. */
1038
1039 /* Calculate the next Tx descriptor entry. */
1040 entry = np->cur_tx % TX_RING_SIZE;
1041
1042 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1043 skb->data,skb->len, PCI_DMA_TODEVICE);
1044 np->tx_skbuff[entry] = skb;
1045
1046 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1047 if (skb->len < TX_BUFLIMIT) {
1048 np->tx_ring[entry].length = DescWholePkt | skb->len;
1049 } else {
1050 int len = skb->len - TX_BUFLIMIT;
1051
1052 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1053 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1054 }
1055 if(entry == TX_RING_SIZE-1)
1056 np->tx_ring[entry].length |= DescEndRing;
1057
1058 /* Now acquire the irq spinlock.
1059 * The difficult race is the the ordering between
1060 * increasing np->cur_tx and setting DescOwn:
1061 * - if np->cur_tx is increased first the interrupt
1062 * handler could consider the packet as transmitted
1063 * since DescOwn is cleared.
1064 * - If DescOwn is set first the NIC could report the
1065 * packet as sent, but the interrupt handler would ignore it
1066 * since the np->cur_tx was not yet increased.
1067 */
1068 spin_lock_irq(&np->lock);
1069 np->cur_tx++;
1070
1071 wmb(); /* flush length, buffer1, buffer2 */
1072 np->tx_ring[entry].status = DescOwn;
1073 wmb(); /* flush status and kick the hardware */
1074 iowrite32(0, np->base_addr + TxStartDemand);
1075 np->tx_q_bytes += skb->len;
1076 /* Work around horrible bug in the chip by marking the queue as full
1077 when we do not have FIFO room for a maximum sized packet. */
1078 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1079 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1080 netif_stop_queue(dev);
1081 wmb();
1082 np->tx_full = 1;
1083 }
1084 spin_unlock_irq(&np->lock);
1085
1086 dev->trans_start = jiffies;
1087
1088 if (debug > 4) {
1089 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1090 dev->name, np->cur_tx, entry);
1091 }
1092 return 0;
1093}
1094
1095static void netdev_tx_done(struct net_device *dev)
1096{
1097 struct netdev_private *np = netdev_priv(dev);
1098 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1099 int entry = np->dirty_tx % TX_RING_SIZE;
1100 int tx_status = np->tx_ring[entry].status;
1101
1102 if (tx_status < 0)
1103 break;
1104 if (tx_status & 0x8000) { /* There was an error, log it. */
1105#ifndef final_version
1106 if (debug > 1)
1107 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1108 dev->name, tx_status);
1109#endif
1110 np->stats.tx_errors++;
1111 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1112 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1113 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1114 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1115 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1116 np->stats.tx_heartbeat_errors++;
1117 } else {
1118#ifndef final_version
1119 if (debug > 3)
1120 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %8.8x.\n",
1121 dev->name, entry, tx_status);
1122#endif
1123 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1124 np->stats.collisions += (tx_status >> 3) & 15;
1125 np->stats.tx_packets++;
1126 }
1127 /* Free the original skb. */
1128 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1129 np->tx_skbuff[entry]->len,
1130 PCI_DMA_TODEVICE);
1131 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1132 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1133 np->tx_skbuff[entry] = NULL;
1134 }
1135 if (np->tx_full &&
1136 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1137 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1138 /* The ring is no longer full, clear tbusy. */
1139 np->tx_full = 0;
1140 wmb();
1141 netif_wake_queue(dev);
1142 }
1143}
1144
1145/* The interrupt handler does all of the Rx thread work and cleans up
1146 after the Tx thread. */
1147static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1148{
1149 struct net_device *dev = (struct net_device *)dev_instance;
1150 struct netdev_private *np = netdev_priv(dev);
1151 void __iomem *ioaddr = np->base_addr;
1152 int work_limit = max_interrupt_work;
1153 int handled = 0;
1154
1155 if (!netif_device_present(dev))
1156 return IRQ_NONE;
1157 do {
1158 u32 intr_status = ioread32(ioaddr + IntrStatus);
1159
1160 /* Acknowledge all of the current interrupt sources ASAP. */
1161 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1162
1163 if (debug > 4)
1164 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1165 dev->name, intr_status);
1166
1167 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1168 break;
1169
1170 handled = 1;
1171
1172 if (intr_status & (IntrRxDone | RxNoBuf))
1173 netdev_rx(dev);
1174 if (intr_status & RxNoBuf)
1175 iowrite32(0, ioaddr + RxStartDemand);
1176
1177 if (intr_status & (TxIdle | IntrTxDone) &&
1178 np->cur_tx != np->dirty_tx) {
1179 spin_lock(&np->lock);
1180 netdev_tx_done(dev);
1181 spin_unlock(&np->lock);
1182 }
1183
1184 /* Abnormal error summary/uncommon events handlers. */
1185 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | IntrPCIErr |
1186 TimerInt | IntrTxStopped))
1187 netdev_error(dev, intr_status);
1188
1189 if (--work_limit < 0) {
1190 printk(KERN_WARNING "%s: Too much work at interrupt, "
1191 "status=0x%4.4x.\n", dev->name, intr_status);
1192 /* Set the timer to re-enable the other interrupts after
1193 10*82usec ticks. */
1194 spin_lock(&np->lock);
1195 if (netif_device_present(dev)) {
1196 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1197 iowrite32(10, ioaddr + GPTimer);
1198 }
1199 spin_unlock(&np->lock);
1200 break;
1201 }
1202 } while (1);
1203
1204 if (debug > 3)
1205 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1206 dev->name, ioread32(ioaddr + IntrStatus));
1207 return IRQ_RETVAL(handled);
1208}
1209
1210/* This routine is logically part of the interrupt handler, but separated
1211 for clarity and better register allocation. */
1212static int netdev_rx(struct net_device *dev)
1213{
1214 struct netdev_private *np = netdev_priv(dev);
1215 int entry = np->cur_rx % RX_RING_SIZE;
1216 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1217
1218 if (debug > 4) {
1219 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
1220 entry, np->rx_ring[entry].status);
1221 }
1222
1223 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1224 while (--work_limit >= 0) {
1225 struct w840_rx_desc *desc = np->rx_head_desc;
1226 s32 status = desc->status;
1227
1228 if (debug > 4)
1229 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1230 status);
1231 if (status < 0)
1232 break;
1233 if ((status & 0x38008300) != 0x0300) {
1234 if ((status & 0x38000300) != 0x0300) {
1235 /* Ingore earlier buffers. */
1236 if ((status & 0xffff) != 0x7fff) {
1237 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1238 "multiple buffers, entry %#x status %4.4x!\n",
1239 dev->name, np->cur_rx, status);
1240 np->stats.rx_length_errors++;
1241 }
1242 } else if (status & 0x8000) {
1243 /* There was a fatal error. */
1244 if (debug > 2)
1245 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1246 dev->name, status);
1247 np->stats.rx_errors++; /* end of a packet.*/
1248 if (status & 0x0890) np->stats.rx_length_errors++;
1249 if (status & 0x004C) np->stats.rx_frame_errors++;
1250 if (status & 0x0002) np->stats.rx_crc_errors++;
1251 }
1252 } else {
1253 struct sk_buff *skb;
1254 /* Omit the four octet CRC from the length. */
1255 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1256
1257#ifndef final_version
1258 if (debug > 4)
1259 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1260 " status %x.\n", pkt_len, status);
1261#endif
1262 /* Check if the packet is long enough to accept without copying
1263 to a minimally-sized skbuff. */
1264 if (pkt_len < rx_copybreak
1265 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1266 skb->dev = dev;
1267 skb_reserve(skb, 2); /* 16 byte align the IP header */
1268 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1269 np->rx_skbuff[entry]->len,
1270 PCI_DMA_FROMDEVICE);
1271 eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0);
1272 skb_put(skb, pkt_len);
1273 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1274 np->rx_skbuff[entry]->len,
1275 PCI_DMA_FROMDEVICE);
1276 } else {
1277 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1278 np->rx_skbuff[entry]->len,
1279 PCI_DMA_FROMDEVICE);
1280 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1281 np->rx_skbuff[entry] = NULL;
1282 }
1283#ifndef final_version /* Remove after testing. */
1284 /* You will want this info for the initial debug. */
1285 if (debug > 5)
1286 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
1287 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x "
1288 "%d.%d.%d.%d.\n",
1289 skb->data[0], skb->data[1], skb->data[2], skb->data[3],
1290 skb->data[4], skb->data[5], skb->data[6], skb->data[7],
1291 skb->data[8], skb->data[9], skb->data[10],
1292 skb->data[11], skb->data[12], skb->data[13],
1293 skb->data[14], skb->data[15], skb->data[16],
1294 skb->data[17]);
1295#endif
1296 skb->protocol = eth_type_trans(skb, dev);
1297 netif_rx(skb);
1298 dev->last_rx = jiffies;
1299 np->stats.rx_packets++;
1300 np->stats.rx_bytes += pkt_len;
1301 }
1302 entry = (++np->cur_rx) % RX_RING_SIZE;
1303 np->rx_head_desc = &np->rx_ring[entry];
1304 }
1305
1306 /* Refill the Rx ring buffers. */
1307 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1308 struct sk_buff *skb;
1309 entry = np->dirty_rx % RX_RING_SIZE;
1310 if (np->rx_skbuff[entry] == NULL) {
1311 skb = dev_alloc_skb(np->rx_buf_sz);
1312 np->rx_skbuff[entry] = skb;
1313 if (skb == NULL)
1314 break; /* Better luck next round. */
1315 skb->dev = dev; /* Mark as being used by this device. */
1316 np->rx_addr[entry] = pci_map_single(np->pci_dev,
1317 skb->tail,
1318 skb->len, PCI_DMA_FROMDEVICE);
1319 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1320 }
1321 wmb();
1322 np->rx_ring[entry].status = DescOwn;
1323 }
1324
1325 return 0;
1326}
1327
1328static void netdev_error(struct net_device *dev, int intr_status)
1329{
1330 struct netdev_private *np = netdev_priv(dev);
1331 void __iomem *ioaddr = np->base_addr;
1332
1333 if (debug > 2)
1334 printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n",
1335 dev->name, intr_status);
1336 if (intr_status == 0xffffffff)
1337 return;
1338 spin_lock(&np->lock);
1339 if (intr_status & TxFIFOUnderflow) {
1340 int new;
1341 /* Bump up the Tx threshold */
1342#if 0
1343 /* This causes lots of dropped packets,
1344 * and under high load even tx_timeouts
1345 */
1346 new = np->csr6 + 0x4000;
1347#else
1348 new = (np->csr6 >> 14)&0x7f;
1349 if (new < 64)
1350 new *= 2;
1351 else
1352 new = 127; /* load full packet before starting */
1353 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1354#endif
1355 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %8.8x.\n",
1356 dev->name, new);
1357 update_csr6(dev, new);
1358 }
1359 if (intr_status & IntrRxDied) { /* Missed a Rx frame. */
1360 np->stats.rx_errors++;
1361 }
1362 if (intr_status & TimerInt) {
1363 /* Re-enable other interrupts. */
1364 if (netif_device_present(dev))
1365 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1366 }
1367 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1368 iowrite32(0, ioaddr + RxStartDemand);
1369 spin_unlock(&np->lock);
1370}
1371
1372static struct net_device_stats *get_stats(struct net_device *dev)
1373{
1374 struct netdev_private *np = netdev_priv(dev);
1375 void __iomem *ioaddr = np->base_addr;
1376
1377 /* The chip only need report frame silently dropped. */
1378 spin_lock_irq(&np->lock);
1379 if (netif_running(dev) && netif_device_present(dev))
1380 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1381 spin_unlock_irq(&np->lock);
1382
1383 return &np->stats;
1384}
1385
1386
1387static u32 __set_rx_mode(struct net_device *dev)
1388{
1389 struct netdev_private *np = netdev_priv(dev);
1390 void __iomem *ioaddr = np->base_addr;
1391 u32 mc_filter[2]; /* Multicast hash filter */
1392 u32 rx_mode;
1393
1394 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1395 /* Unconditionally log net taps. */
1396 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1397 memset(mc_filter, 0xff, sizeof(mc_filter));
1398 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAllPhys
1399 | AcceptMyPhys;
1400 } else if ((dev->mc_count > multicast_filter_limit)
1401 || (dev->flags & IFF_ALLMULTI)) {
1402 /* Too many to match, or accept all multicasts. */
1403 memset(mc_filter, 0xff, sizeof(mc_filter));
1404 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1405 } else {
1406 struct dev_mc_list *mclist;
1407 int i;
1408 memset(mc_filter, 0, sizeof(mc_filter));
1409 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1410 i++, mclist = mclist->next) {
1411 int filterbit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1412 filterbit &= 0x3f;
1413 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1414 }
1415 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1416 }
1417 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1418 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1419 return rx_mode;
1420}
1421
1422static void set_rx_mode(struct net_device *dev)
1423{
1424 struct netdev_private *np = netdev_priv(dev);
1425 u32 rx_mode = __set_rx_mode(dev);
1426 spin_lock_irq(&np->lock);
1427 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1428 spin_unlock_irq(&np->lock);
1429}
1430
1431static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1432{
1433 struct netdev_private *np = netdev_priv(dev);
1434
1435 strcpy (info->driver, DRV_NAME);
1436 strcpy (info->version, DRV_VERSION);
1437 strcpy (info->bus_info, pci_name(np->pci_dev));
1438}
1439
1440static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1441{
1442 struct netdev_private *np = netdev_priv(dev);
1443 int rc;
1444
1445 spin_lock_irq(&np->lock);
1446 rc = mii_ethtool_gset(&np->mii_if, cmd);
1447 spin_unlock_irq(&np->lock);
1448
1449 return rc;
1450}
1451
1452static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453{
1454 struct netdev_private *np = netdev_priv(dev);
1455 int rc;
1456
1457 spin_lock_irq(&np->lock);
1458 rc = mii_ethtool_sset(&np->mii_if, cmd);
1459 spin_unlock_irq(&np->lock);
1460
1461 return rc;
1462}
1463
1464static int netdev_nway_reset(struct net_device *dev)
1465{
1466 struct netdev_private *np = netdev_priv(dev);
1467 return mii_nway_restart(&np->mii_if);
1468}
1469
1470static u32 netdev_get_link(struct net_device *dev)
1471{
1472 struct netdev_private *np = netdev_priv(dev);
1473 return mii_link_ok(&np->mii_if);
1474}
1475
1476static u32 netdev_get_msglevel(struct net_device *dev)
1477{
1478 return debug;
1479}
1480
1481static void netdev_set_msglevel(struct net_device *dev, u32 value)
1482{
1483 debug = value;
1484}
1485
1486static struct ethtool_ops netdev_ethtool_ops = {
1487 .get_drvinfo = netdev_get_drvinfo,
1488 .get_settings = netdev_get_settings,
1489 .set_settings = netdev_set_settings,
1490 .nway_reset = netdev_nway_reset,
1491 .get_link = netdev_get_link,
1492 .get_msglevel = netdev_get_msglevel,
1493 .set_msglevel = netdev_set_msglevel,
1494 .get_sg = ethtool_op_get_sg,
1495 .get_tx_csum = ethtool_op_get_tx_csum,
1496};
1497
1498static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1499{
1500 struct mii_ioctl_data *data = if_mii(rq);
1501 struct netdev_private *np = netdev_priv(dev);
1502
1503 switch(cmd) {
1504 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1505 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1506 /* Fall Through */
1507
1508 case SIOCGMIIREG: /* Read MII PHY register. */
1509 spin_lock_irq(&np->lock);
1510 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1511 spin_unlock_irq(&np->lock);
1512 return 0;
1513
1514 case SIOCSMIIREG: /* Write MII PHY register. */
1515 if (!capable(CAP_NET_ADMIN))
1516 return -EPERM;
1517 spin_lock_irq(&np->lock);
1518 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1519 spin_unlock_irq(&np->lock);
1520 return 0;
1521 default:
1522 return -EOPNOTSUPP;
1523 }
1524}
1525
1526static int netdev_close(struct net_device *dev)
1527{
1528 struct netdev_private *np = netdev_priv(dev);
1529 void __iomem *ioaddr = np->base_addr;
1530
1531 netif_stop_queue(dev);
1532
1533 if (debug > 1) {
1534 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x "
1535 "Config %8.8x.\n", dev->name, ioread32(ioaddr + IntrStatus),
1536 ioread32(ioaddr + NetworkConfig));
1537 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1538 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1539 }
1540
1541 /* Stop the chip's Tx and Rx processes. */
1542 spin_lock_irq(&np->lock);
1543 netif_device_detach(dev);
1544 update_csr6(dev, 0);
1545 iowrite32(0x0000, ioaddr + IntrEnable);
1546 spin_unlock_irq(&np->lock);
1547
1548 free_irq(dev->irq, dev);
1549 wmb();
1550 netif_device_attach(dev);
1551
1552 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1553 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1554
1555#ifdef __i386__
1556 if (debug > 2) {
1557 int i;
1558
1559 printk(KERN_DEBUG" Tx ring at %8.8x:\n",
1560 (int)np->tx_ring);
1561 for (i = 0; i < TX_RING_SIZE; i++)
1562 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x.\n",
1563 i, np->tx_ring[i].length,
1564 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1565 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1566 (int)np->rx_ring);
1567 for (i = 0; i < RX_RING_SIZE; i++) {
1568 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1569 i, np->rx_ring[i].length,
1570 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1571 }
1572 }
1573#endif /* __i386__ debugging only */
1574
1575 del_timer_sync(&np->timer);
1576
1577 free_rxtx_rings(np);
1578 free_ringdesc(np);
1579
1580 return 0;
1581}
1582
1583static void __devexit w840_remove1 (struct pci_dev *pdev)
1584{
1585 struct net_device *dev = pci_get_drvdata(pdev);
1586
1587 if (dev) {
1588 struct netdev_private *np = netdev_priv(dev);
1589 unregister_netdev(dev);
1590 pci_release_regions(pdev);
1591 pci_iounmap(pdev, np->base_addr);
1592 free_netdev(dev);
1593 }
1594
1595 pci_set_drvdata(pdev, NULL);
1596}
1597
1598#ifdef CONFIG_PM
1599
1600/*
1601 * suspend/resume synchronization:
1602 * - open, close, do_ioctl:
1603 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1604 * - get_stats:
1605 * spin_lock_irq(np->lock), doesn't touch hw if not present
1606 * - hard_start_xmit:
1607 * netif_stop_queue + spin_unlock_wait(&dev->xmit_lock);
1608 * - tx_timeout:
1609 * netif_device_detach + spin_unlock_wait(&dev->xmit_lock);
1610 * - set_multicast_list
1611 * netif_device_detach + spin_unlock_wait(&dev->xmit_lock);
1612 * - interrupt handler
1613 * doesn't touch hw if not present, synchronize_irq waits for
1614 * running instances of the interrupt handler.
1615 *
1616 * Disabling hw requires clearing csr6 & IntrEnable.
1617 * update_csr6 & all function that write IntrEnable check netif_device_present
1618 * before settings any bits.
1619 *
1620 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1621 * device would cause an irq storm.
1622 */
1623static int w840_suspend (struct pci_dev *pdev, u32 state)
1624{
1625 struct net_device *dev = pci_get_drvdata (pdev);
1626 struct netdev_private *np = netdev_priv(dev);
1627 void __iomem *ioaddr = np->base_addr;
1628
1629 rtnl_lock();
1630 if (netif_running (dev)) {
1631 del_timer_sync(&np->timer);
1632
1633 spin_lock_irq(&np->lock);
1634 netif_device_detach(dev);
1635 update_csr6(dev, 0);
1636 iowrite32(0, ioaddr + IntrEnable);
1637 netif_stop_queue(dev);
1638 spin_unlock_irq(&np->lock);
1639
1640 spin_unlock_wait(&dev->xmit_lock);
1641 synchronize_irq(dev->irq);
1642
1643 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1644
1645 /* no more hardware accesses behind this line. */
1646
1647 if (np->csr6) BUG();
1648 if (ioread32(ioaddr + IntrEnable)) BUG();
1649
1650 /* pci_power_off(pdev, -1); */
1651
1652 free_rxtx_rings(np);
1653 } else {
1654 netif_device_detach(dev);
1655 }
1656 rtnl_unlock();
1657 return 0;
1658}
1659
1660static int w840_resume (struct pci_dev *pdev)
1661{
1662 struct net_device *dev = pci_get_drvdata (pdev);
1663 struct netdev_private *np = netdev_priv(dev);
1664
1665 rtnl_lock();
1666 if (netif_device_present(dev))
1667 goto out; /* device not suspended */
1668 if (netif_running(dev)) {
1669 pci_enable_device(pdev);
1670 /* pci_power_on(pdev); */
1671
1672 spin_lock_irq(&np->lock);
1673 iowrite32(1, np->base_addr+PCIBusCfg);
1674 ioread32(np->base_addr+PCIBusCfg);
1675 udelay(1);
1676 netif_device_attach(dev);
1677 init_rxtx_rings(dev);
1678 init_registers(dev);
1679 spin_unlock_irq(&np->lock);
1680
1681 netif_wake_queue(dev);
1682
1683 mod_timer(&np->timer, jiffies + 1*HZ);
1684 } else {
1685 netif_device_attach(dev);
1686 }
1687out:
1688 rtnl_unlock();
1689 return 0;
1690}
1691#endif
1692
1693static struct pci_driver w840_driver = {
1694 .name = DRV_NAME,
1695 .id_table = w840_pci_tbl,
1696 .probe = w840_probe1,
1697 .remove = __devexit_p(w840_remove1),
1698#ifdef CONFIG_PM
1699 .suspend = w840_suspend,
1700 .resume = w840_resume,
1701#endif
1702};
1703
1704static int __init w840_init(void)
1705{
1706 printk(version);
1707 return pci_module_init(&w840_driver);
1708}
1709
1710static void __exit w840_exit(void)
1711{
1712 pci_unregister_driver(&w840_driver);
1713}
1714
1715module_init(w840_init);
1716module_exit(w840_exit);
diff --git a/drivers/net/tulip/xircom_cb.c b/drivers/net/tulip/xircom_cb.c
new file mode 100644
index 000000000000..26cc4f6378c7
--- /dev/null
+++ b/drivers/net/tulip/xircom_cb.c
@@ -0,0 +1,1277 @@
1/*
2 * xircom_cb: A driver for the (tulip-like) Xircom Cardbus ethernet cards
3 *
4 * This software is (C) by the respective authors, and licensed under the GPL
5 * License.
6 *
7 * Written by Arjan van de Ven for Red Hat, Inc.
8 * Based on work by Jeff Garzik, Doug Ledford and Donald Becker
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 *
14 * $Id: xircom_cb.c,v 1.33 2001/03/19 14:02:07 arjanv Exp $
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/delay.h>
29#include <linux/init.h>
30#include <linux/ethtool.h>
31#include <linux/bitops.h>
32
33#include <asm/uaccess.h>
34#include <asm/io.h>
35
36#ifdef DEBUG
37#define enter(x) printk("Enter: %s, %s line %i\n",x,__FILE__,__LINE__)
38#define leave(x) printk("Leave: %s, %s line %i\n",x,__FILE__,__LINE__)
39#else
40#define enter(x) do {} while (0)
41#define leave(x) do {} while (0)
42#endif
43
44
45MODULE_DESCRIPTION("Xircom Cardbus ethernet driver");
46MODULE_AUTHOR("Arjan van de Ven <arjanv@redhat.com>");
47MODULE_LICENSE("GPL");
48
49
50
51/* IO registers on the card, offsets */
52#define CSR0 0x00
53#define CSR1 0x08
54#define CSR2 0x10
55#define CSR3 0x18
56#define CSR4 0x20
57#define CSR5 0x28
58#define CSR6 0x30
59#define CSR7 0x38
60#define CSR8 0x40
61#define CSR9 0x48
62#define CSR10 0x50
63#define CSR11 0x58
64#define CSR12 0x60
65#define CSR13 0x68
66#define CSR14 0x70
67#define CSR15 0x78
68#define CSR16 0x80
69
70/* PCI registers */
71#define PCI_POWERMGMT 0x40
72
73/* Offsets of the buffers within the descriptor pages, in bytes */
74
75#define NUMDESCRIPTORS 4
76
77static int bufferoffsets[NUMDESCRIPTORS] = {128,2048,4096,6144};
78
79
80struct xircom_private {
81 /* Send and receive buffers, kernel-addressable and dma addressable forms */
82
83 unsigned int *rx_buffer;
84 unsigned int *tx_buffer;
85
86 dma_addr_t rx_dma_handle;
87 dma_addr_t tx_dma_handle;
88
89 struct sk_buff *tx_skb[4];
90
91 unsigned long io_port;
92 int open;
93
94 /* transmit_used is the rotating counter that indicates which transmit
95 descriptor has to be used next */
96 int transmit_used;
97
98 /* Spinlock to serialize register operations.
99 It must be helt while manipulating the following registers:
100 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
101 */
102 spinlock_t lock;
103
104
105 struct pci_dev *pdev;
106 struct net_device *dev;
107 struct net_device_stats stats;
108};
109
110
111/* Function prototypes */
112static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id);
113static void xircom_remove(struct pci_dev *pdev);
114static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
115static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev);
116static int xircom_open(struct net_device *dev);
117static int xircom_close(struct net_device *dev);
118static void xircom_up(struct xircom_private *card);
119static struct net_device_stats *xircom_get_stats(struct net_device *dev);
120#if CONFIG_NET_POLL_CONTROLLER
121static void xircom_poll_controller(struct net_device *dev);
122#endif
123
124static void investigate_read_descriptor(struct net_device *dev,struct xircom_private *card, int descnr, unsigned int bufferoffset);
125static void investigate_write_descriptor(struct net_device *dev, struct xircom_private *card, int descnr, unsigned int bufferoffset);
126static void read_mac_address(struct xircom_private *card);
127static void transceiver_voodoo(struct xircom_private *card);
128static void initialize_card(struct xircom_private *card);
129static void trigger_transmit(struct xircom_private *card);
130static void trigger_receive(struct xircom_private *card);
131static void setup_descriptors(struct xircom_private *card);
132static void remove_descriptors(struct xircom_private *card);
133static int link_status_changed(struct xircom_private *card);
134static void activate_receiver(struct xircom_private *card);
135static void deactivate_receiver(struct xircom_private *card);
136static void activate_transmitter(struct xircom_private *card);
137static void deactivate_transmitter(struct xircom_private *card);
138static void enable_transmit_interrupt(struct xircom_private *card);
139static void enable_receive_interrupt(struct xircom_private *card);
140static void enable_link_interrupt(struct xircom_private *card);
141static void disable_all_interrupts(struct xircom_private *card);
142static int link_status(struct xircom_private *card);
143
144
145
146static struct pci_device_id xircom_pci_table[] = {
147 {0x115D, 0x0003, PCI_ANY_ID, PCI_ANY_ID,},
148 {0,},
149};
150MODULE_DEVICE_TABLE(pci, xircom_pci_table);
151
152static struct pci_driver xircom_ops = {
153 .name = "xircom_cb",
154 .id_table = xircom_pci_table,
155 .probe = xircom_probe,
156 .remove = xircom_remove,
157 .suspend =NULL,
158 .resume =NULL
159};
160
161
162#ifdef DEBUG
163static void print_binary(unsigned int number)
164{
165 int i,i2;
166 char buffer[64];
167 memset(buffer,0,64);
168 i2=0;
169 for (i=31;i>=0;i--) {
170 if (number & (1<<i))
171 buffer[i2++]='1';
172 else
173 buffer[i2++]='0';
174 if ((i&3)==0)
175 buffer[i2++]=' ';
176 }
177 printk("%s\n",buffer);
178}
179#endif
180
181static void netdev_get_drvinfo(struct net_device *dev,
182 struct ethtool_drvinfo *info)
183{
184 struct xircom_private *private = netdev_priv(dev);
185
186 strcpy(info->driver, "xircom_cb");
187 strcpy(info->bus_info, pci_name(private->pdev));
188}
189
190static struct ethtool_ops netdev_ethtool_ops = {
191 .get_drvinfo = netdev_get_drvinfo,
192};
193
194/* xircom_probe is the code that gets called on device insertion.
195 it sets up the hardware and registers the device to the networklayer.
196
197 TODO: Send 1 or 2 "dummy" packets here as the card seems to discard the
198 first two packets that get send, and pump hates that.
199
200 */
201static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id)
202{
203 struct net_device *dev = NULL;
204 struct xircom_private *private;
205 unsigned char chip_rev;
206 unsigned long flags;
207 unsigned short tmp16;
208 enter("xircom_probe");
209
210 /* First do the PCI initialisation */
211
212 if (pci_enable_device(pdev))
213 return -ENODEV;
214
215 /* disable all powermanagement */
216 pci_write_config_dword(pdev, PCI_POWERMGMT, 0x0000);
217
218 pci_set_master(pdev); /* Why isn't this done by pci_enable_device ?*/
219
220 /* clear PCI status, if any */
221 pci_read_config_word (pdev,PCI_STATUS, &tmp16);
222 pci_write_config_word (pdev, PCI_STATUS,tmp16);
223
224 pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
225
226 if (!request_region(pci_resource_start(pdev, 0), 128, "xircom_cb")) {
227 printk(KERN_ERR "xircom_probe: failed to allocate io-region\n");
228 return -ENODEV;
229 }
230
231 /*
232 Before changing the hardware, allocate the memory.
233 This way, we can fail gracefully if not enough memory
234 is available.
235 */
236 dev = alloc_etherdev(sizeof(struct xircom_private));
237 if (!dev) {
238 printk(KERN_ERR "xircom_probe: failed to allocate etherdev\n");
239 goto device_fail;
240 }
241 private = netdev_priv(dev);
242
243 /* Allocate the send/receive buffers */
244 private->rx_buffer = pci_alloc_consistent(pdev,8192,&private->rx_dma_handle);
245 if (private->rx_buffer == NULL) {
246 printk(KERN_ERR "xircom_probe: no memory for rx buffer \n");
247 goto rx_buf_fail;
248 }
249 private->tx_buffer = pci_alloc_consistent(pdev,8192,&private->tx_dma_handle);
250 if (private->tx_buffer == NULL) {
251 printk(KERN_ERR "xircom_probe: no memory for tx buffer \n");
252 goto tx_buf_fail;
253 }
254
255 SET_MODULE_OWNER(dev);
256 SET_NETDEV_DEV(dev, &pdev->dev);
257
258
259 private->dev = dev;
260 private->pdev = pdev;
261 private->io_port = pci_resource_start(pdev, 0);
262 spin_lock_init(&private->lock);
263 dev->irq = pdev->irq;
264 dev->base_addr = private->io_port;
265
266 initialize_card(private);
267 read_mac_address(private);
268 setup_descriptors(private);
269
270 dev->open = &xircom_open;
271 dev->hard_start_xmit = &xircom_start_xmit;
272 dev->stop = &xircom_close;
273 dev->get_stats = &xircom_get_stats;
274 dev->priv = private;
275#ifdef CONFIG_NET_POLL_CONTROLLER
276 dev->poll_controller = &xircom_poll_controller;
277#endif
278 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
279 pci_set_drvdata(pdev, dev);
280
281 if (register_netdev(dev)) {
282 printk(KERN_ERR "xircom_probe: netdevice registration failed.\n");
283 goto reg_fail;
284 }
285
286 printk(KERN_INFO "%s: Xircom cardbus revision %i at irq %i \n", dev->name, chip_rev, pdev->irq);
287 /* start the transmitter to get a heartbeat */
288 /* TODO: send 2 dummy packets here */
289 transceiver_voodoo(private);
290
291 spin_lock_irqsave(&private->lock,flags);
292 activate_transmitter(private);
293 activate_receiver(private);
294 spin_unlock_irqrestore(&private->lock,flags);
295
296 trigger_receive(private);
297
298 leave("xircom_probe");
299 return 0;
300
301reg_fail:
302 kfree(private->tx_buffer);
303tx_buf_fail:
304 kfree(private->rx_buffer);
305rx_buf_fail:
306 free_netdev(dev);
307device_fail:
308 return -ENODEV;
309}
310
311
312/*
313 xircom_remove is called on module-unload or on device-eject.
314 it unregisters the irq, io-region and network device.
315 Interrupts and such are already stopped in the "ifconfig ethX down"
316 code.
317 */
318static void __devexit xircom_remove(struct pci_dev *pdev)
319{
320 struct net_device *dev = pci_get_drvdata(pdev);
321 struct xircom_private *card = netdev_priv(dev);
322
323 enter("xircom_remove");
324 pci_free_consistent(pdev,8192,card->rx_buffer,card->rx_dma_handle);
325 pci_free_consistent(pdev,8192,card->tx_buffer,card->tx_dma_handle);
326
327 release_region(dev->base_addr, 128);
328 unregister_netdev(dev);
329 free_netdev(dev);
330 pci_set_drvdata(pdev, NULL);
331 leave("xircom_remove");
332}
333
334static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
335{
336 struct net_device *dev = (struct net_device *) dev_instance;
337 struct xircom_private *card = netdev_priv(dev);
338 unsigned int status;
339 int i;
340
341 enter("xircom_interrupt\n");
342
343 spin_lock(&card->lock);
344 status = inl(card->io_port+CSR5);
345
346#ifdef DEBUG
347 print_binary(status);
348 printk("tx status 0x%08x 0x%08x \n",card->tx_buffer[0],card->tx_buffer[4]);
349 printk("rx status 0x%08x 0x%08x \n",card->rx_buffer[0],card->rx_buffer[4]);
350#endif
351 /* Handle shared irq and hotplug */
352 if (status == 0 || status == 0xffffffff) {
353 spin_unlock(&card->lock);
354 return IRQ_NONE;
355 }
356
357 if (link_status_changed(card)) {
358 int newlink;
359 printk(KERN_DEBUG "xircom_cb: Link status has changed \n");
360 newlink = link_status(card);
361 printk(KERN_INFO "xircom_cb: Link is %i mbit \n",newlink);
362 if (newlink)
363 netif_carrier_on(dev);
364 else
365 netif_carrier_off(dev);
366
367 }
368
369 /* Clear all remaining interrupts */
370 status |= 0xffffffff; /* FIXME: make this clear only the
371 real existing bits */
372 outl(status,card->io_port+CSR5);
373
374
375 for (i=0;i<NUMDESCRIPTORS;i++)
376 investigate_write_descriptor(dev,card,i,bufferoffsets[i]);
377 for (i=0;i<NUMDESCRIPTORS;i++)
378 investigate_read_descriptor(dev,card,i,bufferoffsets[i]);
379
380
381 spin_unlock(&card->lock);
382 leave("xircom_interrupt");
383 return IRQ_HANDLED;
384}
385
386static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev)
387{
388 struct xircom_private *card;
389 unsigned long flags;
390 int nextdescriptor;
391 int desc;
392 enter("xircom_start_xmit");
393
394 card = netdev_priv(dev);
395 spin_lock_irqsave(&card->lock,flags);
396
397 /* First see if we can free some descriptors */
398 for (desc=0;desc<NUMDESCRIPTORS;desc++)
399 investigate_write_descriptor(dev,card,desc,bufferoffsets[desc]);
400
401
402 nextdescriptor = (card->transmit_used +1) % (NUMDESCRIPTORS);
403 desc = card->transmit_used;
404
405 /* only send the packet if the descriptor is free */
406 if (card->tx_buffer[4*desc]==0) {
407 /* Copy the packet data; zero the memory first as the card
408 sometimes sends more than you ask it to. */
409
410 memset(&card->tx_buffer[bufferoffsets[desc]/4],0,1536);
411 memcpy(&(card->tx_buffer[bufferoffsets[desc]/4]),skb->data,skb->len);
412
413
414 /* FIXME: The specification tells us that the length we send HAS to be a multiple of
415 4 bytes. */
416
417 card->tx_buffer[4*desc+1] = skb->len;
418 if (desc == NUMDESCRIPTORS-1)
419 card->tx_buffer[4*desc+1] |= (1<<25); /* bit 25: last descriptor of the ring */
420
421 card->tx_buffer[4*desc+1] |= 0xF0000000;
422 /* 0xF0... means want interrupts*/
423 card->tx_skb[desc] = skb;
424
425 wmb();
426 /* This gives the descriptor to the card */
427 card->tx_buffer[4*desc] = 0x80000000;
428 trigger_transmit(card);
429 if (((int)card->tx_buffer[nextdescriptor*4])<0) { /* next descriptor is occupied... */
430 netif_stop_queue(dev);
431 }
432 card->transmit_used = nextdescriptor;
433 leave("xircom-start_xmit - sent");
434 spin_unlock_irqrestore(&card->lock,flags);
435 return 0;
436 }
437
438
439
440 /* Uh oh... no free descriptor... drop the packet */
441 netif_stop_queue(dev);
442 spin_unlock_irqrestore(&card->lock,flags);
443 trigger_transmit(card);
444
445 return -EIO;
446}
447
448
449
450
451static int xircom_open(struct net_device *dev)
452{
453 struct xircom_private *xp = netdev_priv(dev);
454 int retval;
455 enter("xircom_open");
456 printk(KERN_INFO "xircom cardbus adaptor found, registering as %s, using irq %i \n",dev->name,dev->irq);
457 retval = request_irq(dev->irq, &xircom_interrupt, SA_SHIRQ, dev->name, dev);
458 if (retval) {
459 leave("xircom_open - No IRQ");
460 return retval;
461 }
462
463 xircom_up(xp);
464 xp->open = 1;
465 leave("xircom_open");
466 return 0;
467}
468
469static int xircom_close(struct net_device *dev)
470{
471 struct xircom_private *card;
472 unsigned long flags;
473
474 enter("xircom_close");
475 card = netdev_priv(dev);
476 netif_stop_queue(dev); /* we don't want new packets */
477
478
479 spin_lock_irqsave(&card->lock,flags);
480
481 disable_all_interrupts(card);
482#if 0
483 /* We can enable this again once we send dummy packets on ifconfig ethX up */
484 deactivate_receiver(card);
485 deactivate_transmitter(card);
486#endif
487 remove_descriptors(card);
488
489 spin_unlock_irqrestore(&card->lock,flags);
490
491 card->open = 0;
492 free_irq(dev->irq,dev);
493
494 leave("xircom_close");
495
496 return 0;
497
498}
499
500
501
502static struct net_device_stats *xircom_get_stats(struct net_device *dev)
503{
504 struct xircom_private *card = netdev_priv(dev);
505 return &card->stats;
506}
507
508
509#ifdef CONFIG_NET_POLL_CONTROLLER
510static void xircom_poll_controller(struct net_device *dev)
511{
512 disable_irq(dev->irq);
513 xircom_interrupt(dev->irq, dev, NULL);
514 enable_irq(dev->irq);
515}
516#endif
517
518
519static void initialize_card(struct xircom_private *card)
520{
521 unsigned int val;
522 unsigned long flags;
523 enter("initialize_card");
524
525
526 spin_lock_irqsave(&card->lock, flags);
527
528 /* First: reset the card */
529 val = inl(card->io_port + CSR0);
530 val |= 0x01; /* Software reset */
531 outl(val, card->io_port + CSR0);
532
533 udelay(100); /* give the card some time to reset */
534
535 val = inl(card->io_port + CSR0);
536 val &= ~0x01; /* disable Software reset */
537 outl(val, card->io_port + CSR0);
538
539
540 val = 0; /* Value 0x00 is a safe and conservative value
541 for the PCI configuration settings */
542 outl(val, card->io_port + CSR0);
543
544
545 disable_all_interrupts(card);
546 deactivate_receiver(card);
547 deactivate_transmitter(card);
548
549 spin_unlock_irqrestore(&card->lock, flags);
550
551 leave("initialize_card");
552}
553
554/*
555trigger_transmit causes the card to check for frames to be transmitted.
556This is accomplished by writing to the CSR1 port. The documentation
557claims that the act of writing is sufficient and that the value is
558ignored; I chose zero.
559*/
560static void trigger_transmit(struct xircom_private *card)
561{
562 unsigned int val;
563 enter("trigger_transmit");
564
565 val = 0;
566 outl(val, card->io_port + CSR1);
567
568 leave("trigger_transmit");
569}
570
571/*
572trigger_receive causes the card to check for empty frames in the
573descriptor list in which packets can be received.
574This is accomplished by writing to the CSR2 port. The documentation
575claims that the act of writing is sufficient and that the value is
576ignored; I chose zero.
577*/
578static void trigger_receive(struct xircom_private *card)
579{
580 unsigned int val;
581 enter("trigger_receive");
582
583 val = 0;
584 outl(val, card->io_port + CSR2);
585
586 leave("trigger_receive");
587}
588
589/*
590setup_descriptors initializes the send and receive buffers to be valid
591descriptors and programs the addresses into the card.
592*/
593static void setup_descriptors(struct xircom_private *card)
594{
595 unsigned int val;
596 unsigned int address;
597 int i;
598 enter("setup_descriptors");
599
600
601 if (card->rx_buffer == NULL)
602 BUG();
603 if (card->tx_buffer == NULL)
604 BUG();
605
606 /* Receive descriptors */
607 memset(card->rx_buffer, 0, 128); /* clear the descriptors */
608 for (i=0;i<NUMDESCRIPTORS;i++ ) {
609
610 /* Rx Descr0: It's empty, let the card own it, no errors -> 0x80000000 */
611 card->rx_buffer[i*4 + 0] = 0x80000000;
612 /* Rx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */
613 card->rx_buffer[i*4 + 1] = 1536;
614 if (i==NUMDESCRIPTORS-1)
615 card->rx_buffer[i*4 + 1] |= (1 << 25); /* bit 25 is "last descriptor" */
616
617 /* Rx Descr2: address of the buffer
618 we store the buffer at the 2nd half of the page */
619
620 address = (unsigned long) card->rx_dma_handle;
621 card->rx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]);
622 /* Rx Desc3: address of 2nd buffer -> 0 */
623 card->rx_buffer[i*4 + 3] = 0;
624 }
625
626 wmb();
627 /* Write the receive descriptor ring address to the card */
628 address = (unsigned long) card->rx_dma_handle;
629 val = cpu_to_le32(address);
630 outl(val, card->io_port + CSR3); /* Receive descr list address */
631
632
633 /* transmit descriptors */
634 memset(card->tx_buffer, 0, 128); /* clear the descriptors */
635
636 for (i=0;i<NUMDESCRIPTORS;i++ ) {
637 /* Tx Descr0: Empty, we own it, no errors -> 0x00000000 */
638 card->tx_buffer[i*4 + 0] = 0x00000000;
639 /* Tx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */
640 card->tx_buffer[i*4 + 1] = 1536;
641 if (i==NUMDESCRIPTORS-1)
642 card->tx_buffer[i*4 + 1] |= (1 << 25); /* bit 25 is "last descriptor" */
643
644 /* Tx Descr2: address of the buffer
645 we store the buffer at the 2nd half of the page */
646 address = (unsigned long) card->tx_dma_handle;
647 card->tx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]);
648 /* Tx Desc3: address of 2nd buffer -> 0 */
649 card->tx_buffer[i*4 + 3] = 0;
650 }
651
652 wmb();
653 /* wite the transmit descriptor ring to the card */
654 address = (unsigned long) card->tx_dma_handle;
655 val =cpu_to_le32(address);
656 outl(val, card->io_port + CSR4); /* xmit descr list address */
657
658 leave("setup_descriptors");
659}
660
661/*
662remove_descriptors informs the card the descriptors are no longer
663valid by setting the address in the card to 0x00.
664*/
665static void remove_descriptors(struct xircom_private *card)
666{
667 unsigned int val;
668 enter("remove_descriptors");
669
670 val = 0;
671 outl(val, card->io_port + CSR3); /* Receive descriptor address */
672 outl(val, card->io_port + CSR4); /* Send descriptor address */
673
674 leave("remove_descriptors");
675}
676
677/*
678link_status_changed returns 1 if the card has indicated that
679the link status has changed. The new link status has to be read from CSR12.
680
681This function also clears the status-bit.
682*/
683static int link_status_changed(struct xircom_private *card)
684{
685 unsigned int val;
686 enter("link_status_changed");
687
688 val = inl(card->io_port + CSR5); /* Status register */
689
690 if ((val & (1 << 27)) == 0) { /* no change */
691 leave("link_status_changed - nochange");
692 return 0;
693 }
694
695 /* clear the event by writing a 1 to the bit in the
696 status register. */
697 val = (1 << 27);
698 outl(val, card->io_port + CSR5);
699
700 leave("link_status_changed - changed");
701 return 1;
702}
703
704
705/*
706transmit_active returns 1 if the transmitter on the card is
707in a non-stopped state.
708*/
709static int transmit_active(struct xircom_private *card)
710{
711 unsigned int val;
712 enter("transmit_active");
713
714 val = inl(card->io_port + CSR5); /* Status register */
715
716 if ((val & (7 << 20)) == 0) { /* transmitter disabled */
717 leave("transmit_active - inactive");
718 return 0;
719 }
720
721 leave("transmit_active - active");
722 return 1;
723}
724
725/*
726receive_active returns 1 if the receiver on the card is
727in a non-stopped state.
728*/
729static int receive_active(struct xircom_private *card)
730{
731 unsigned int val;
732 enter("receive_active");
733
734
735 val = inl(card->io_port + CSR5); /* Status register */
736
737 if ((val & (7 << 17)) == 0) { /* receiver disabled */
738 leave("receive_active - inactive");
739 return 0;
740 }
741
742 leave("receive_active - active");
743 return 1;
744}
745
746/*
747activate_receiver enables the receiver on the card.
748Before being allowed to active the receiver, the receiver
749must be completely de-activated. To achieve this,
750this code actually disables the receiver first; then it waits for the
751receiver to become inactive, then it activates the receiver and then
752it waits for the receiver to be active.
753
754must be called with the lock held and interrupts disabled.
755*/
756static void activate_receiver(struct xircom_private *card)
757{
758 unsigned int val;
759 int counter;
760 enter("activate_receiver");
761
762
763 val = inl(card->io_port + CSR6); /* Operation mode */
764
765 /* If the "active" bit is set and the receiver is already
766 active, no need to do the expensive thing */
767 if ((val&2) && (receive_active(card)))
768 return;
769
770
771 val = val & ~2; /* disable the receiver */
772 outl(val, card->io_port + CSR6);
773
774 counter = 10;
775 while (counter > 0) {
776 if (!receive_active(card))
777 break;
778 /* wait a while */
779 udelay(50);
780 counter--;
781 if (counter <= 0)
782 printk(KERN_ERR "xircom_cb: Receiver failed to deactivate\n");
783 }
784
785 /* enable the receiver */
786 val = inl(card->io_port + CSR6); /* Operation mode */
787 val = val | 2; /* enable the receiver */
788 outl(val, card->io_port + CSR6);
789
790 /* now wait for the card to activate again */
791 counter = 10;
792 while (counter > 0) {
793 if (receive_active(card))
794 break;
795 /* wait a while */
796 udelay(50);
797 counter--;
798 if (counter <= 0)
799 printk(KERN_ERR "xircom_cb: Receiver failed to re-activate\n");
800 }
801
802 leave("activate_receiver");
803}
804
805/*
806deactivate_receiver disables the receiver on the card.
807To achieve this this code disables the receiver first;
808then it waits for the receiver to become inactive.
809
810must be called with the lock held and interrupts disabled.
811*/
812static void deactivate_receiver(struct xircom_private *card)
813{
814 unsigned int val;
815 int counter;
816 enter("deactivate_receiver");
817
818 val = inl(card->io_port + CSR6); /* Operation mode */
819 val = val & ~2; /* disable the receiver */
820 outl(val, card->io_port + CSR6);
821
822 counter = 10;
823 while (counter > 0) {
824 if (!receive_active(card))
825 break;
826 /* wait a while */
827 udelay(50);
828 counter--;
829 if (counter <= 0)
830 printk(KERN_ERR "xircom_cb: Receiver failed to deactivate\n");
831 }
832
833
834 leave("deactivate_receiver");
835}
836
837
838/*
839activate_transmitter enables the transmitter on the card.
840Before being allowed to active the transmitter, the transmitter
841must be completely de-activated. To achieve this,
842this code actually disables the transmitter first; then it waits for the
843transmitter to become inactive, then it activates the transmitter and then
844it waits for the transmitter to be active again.
845
846must be called with the lock held and interrupts disabled.
847*/
848static void activate_transmitter(struct xircom_private *card)
849{
850 unsigned int val;
851 int counter;
852 enter("activate_transmitter");
853
854
855 val = inl(card->io_port + CSR6); /* Operation mode */
856
857 /* If the "active" bit is set and the receiver is already
858 active, no need to do the expensive thing */
859 if ((val&(1<<13)) && (transmit_active(card)))
860 return;
861
862 val = val & ~(1 << 13); /* disable the transmitter */
863 outl(val, card->io_port + CSR6);
864
865 counter = 10;
866 while (counter > 0) {
867 if (!transmit_active(card))
868 break;
869 /* wait a while */
870 udelay(50);
871 counter--;
872 if (counter <= 0)
873 printk(KERN_ERR "xircom_cb: Transmitter failed to deactivate\n");
874 }
875
876 /* enable the transmitter */
877 val = inl(card->io_port + CSR6); /* Operation mode */
878 val = val | (1 << 13); /* enable the transmitter */
879 outl(val, card->io_port + CSR6);
880
881 /* now wait for the card to activate again */
882 counter = 10;
883 while (counter > 0) {
884 if (transmit_active(card))
885 break;
886 /* wait a while */
887 udelay(50);
888 counter--;
889 if (counter <= 0)
890 printk(KERN_ERR "xircom_cb: Transmitter failed to re-activate\n");
891 }
892
893 leave("activate_transmitter");
894}
895
896/*
897deactivate_transmitter disables the transmitter on the card.
898To achieve this this code disables the transmitter first;
899then it waits for the transmitter to become inactive.
900
901must be called with the lock held and interrupts disabled.
902*/
903static void deactivate_transmitter(struct xircom_private *card)
904{
905 unsigned int val;
906 int counter;
907 enter("deactivate_transmitter");
908
909 val = inl(card->io_port + CSR6); /* Operation mode */
910 val = val & ~2; /* disable the transmitter */
911 outl(val, card->io_port + CSR6);
912
913 counter = 20;
914 while (counter > 0) {
915 if (!transmit_active(card))
916 break;
917 /* wait a while */
918 udelay(50);
919 counter--;
920 if (counter <= 0)
921 printk(KERN_ERR "xircom_cb: Transmitter failed to deactivate\n");
922 }
923
924
925 leave("deactivate_transmitter");
926}
927
928
929/*
930enable_transmit_interrupt enables the transmit interrupt
931
932must be called with the lock held and interrupts disabled.
933*/
934static void enable_transmit_interrupt(struct xircom_private *card)
935{
936 unsigned int val;
937 enter("enable_transmit_interrupt");
938
939 val = inl(card->io_port + CSR7); /* Interrupt enable register */
940 val |= 1; /* enable the transmit interrupt */
941 outl(val, card->io_port + CSR7);
942
943 leave("enable_transmit_interrupt");
944}
945
946
947/*
948enable_receive_interrupt enables the receive interrupt
949
950must be called with the lock held and interrupts disabled.
951*/
952static void enable_receive_interrupt(struct xircom_private *card)
953{
954 unsigned int val;
955 enter("enable_receive_interrupt");
956
957 val = inl(card->io_port + CSR7); /* Interrupt enable register */
958 val = val | (1 << 6); /* enable the receive interrupt */
959 outl(val, card->io_port + CSR7);
960
961 leave("enable_receive_interrupt");
962}
963
964/*
965enable_link_interrupt enables the link status change interrupt
966
967must be called with the lock held and interrupts disabled.
968*/
969static void enable_link_interrupt(struct xircom_private *card)
970{
971 unsigned int val;
972 enter("enable_link_interrupt");
973
974 val = inl(card->io_port + CSR7); /* Interrupt enable register */
975 val = val | (1 << 27); /* enable the link status chage interrupt */
976 outl(val, card->io_port + CSR7);
977
978 leave("enable_link_interrupt");
979}
980
981
982
983/*
984disable_all_interrupts disables all interrupts
985
986must be called with the lock held and interrupts disabled.
987*/
988static void disable_all_interrupts(struct xircom_private *card)
989{
990 unsigned int val;
991 enter("enable_all_interrupts");
992
993 val = 0; /* disable all interrupts */
994 outl(val, card->io_port + CSR7);
995
996 leave("disable_all_interrupts");
997}
998
999/*
1000enable_common_interrupts enables several weird interrupts
1001
1002must be called with the lock held and interrupts disabled.
1003*/
1004static void enable_common_interrupts(struct xircom_private *card)
1005{
1006 unsigned int val;
1007 enter("enable_link_interrupt");
1008
1009 val = inl(card->io_port + CSR7); /* Interrupt enable register */
1010 val |= (1<<16); /* Normal Interrupt Summary */
1011 val |= (1<<15); /* Abnormal Interrupt Summary */
1012 val |= (1<<13); /* Fatal bus error */
1013 val |= (1<<8); /* Receive Process Stopped */
1014 val |= (1<<7); /* Receive Buffer Unavailable */
1015 val |= (1<<5); /* Transmit Underflow */
1016 val |= (1<<2); /* Transmit Buffer Unavailable */
1017 val |= (1<<1); /* Transmit Process Stopped */
1018 outl(val, card->io_port + CSR7);
1019
1020 leave("enable_link_interrupt");
1021}
1022
1023/*
1024enable_promisc starts promisc mode
1025
1026must be called with the lock held and interrupts disabled.
1027*/
1028static int enable_promisc(struct xircom_private *card)
1029{
1030 unsigned int val;
1031 enter("enable_promisc");
1032
1033 val = inl(card->io_port + CSR6);
1034 val = val | (1 << 6);
1035 outl(val, card->io_port + CSR6);
1036
1037 leave("enable_promisc");
1038 return 1;
1039}
1040
1041
1042
1043
1044/*
1045link_status() checks the the links status and will return 0 for no link, 10 for 10mbit link and 100 for.. guess what.
1046
1047Must be called in locked state with interrupts disabled
1048*/
1049static int link_status(struct xircom_private *card)
1050{
1051 unsigned int val;
1052 enter("link_status");
1053
1054 val = inb(card->io_port + CSR12);
1055
1056 if (!(val&(1<<2))) /* bit 2 is 0 for 10mbit link, 1 for not an 10mbit link */
1057 return 10;
1058 if (!(val&(1<<1))) /* bit 1 is 0 for 100mbit link, 1 for not an 100mbit link */
1059 return 100;
1060
1061 /* If we get here -> no link at all */
1062
1063 leave("link_status");
1064 return 0;
1065}
1066
1067
1068
1069
1070
1071/*
1072 read_mac_address() reads the MAC address from the NIC and stores it in the "dev" structure.
1073
1074 This function will take the spinlock itself and can, as a result, not be called with the lock helt.
1075 */
1076static void read_mac_address(struct xircom_private *card)
1077{
1078 unsigned char j, tuple, link, data_id, data_count;
1079 unsigned long flags;
1080 int i;
1081
1082 enter("read_mac_address");
1083
1084 spin_lock_irqsave(&card->lock, flags);
1085
1086 outl(1 << 12, card->io_port + CSR9); /* enable boot rom access */
1087 for (i = 0x100; i < 0x1f7; i += link + 2) {
1088 outl(i, card->io_port + CSR10);
1089 tuple = inl(card->io_port + CSR9) & 0xff;
1090 outl(i + 1, card->io_port + CSR10);
1091 link = inl(card->io_port + CSR9) & 0xff;
1092 outl(i + 2, card->io_port + CSR10);
1093 data_id = inl(card->io_port + CSR9) & 0xff;
1094 outl(i + 3, card->io_port + CSR10);
1095 data_count = inl(card->io_port + CSR9) & 0xff;
1096 if ((tuple == 0x22) && (data_id == 0x04) && (data_count == 0x06)) {
1097 /*
1098 * This is it. We have the data we want.
1099 */
1100 for (j = 0; j < 6; j++) {
1101 outl(i + j + 4, card->io_port + CSR10);
1102 card->dev->dev_addr[j] = inl(card->io_port + CSR9) & 0xff;
1103 }
1104 break;
1105 } else if (link == 0) {
1106 break;
1107 }
1108 }
1109 spin_unlock_irqrestore(&card->lock, flags);
1110#ifdef DEBUG
1111 for (i = 0; i < 6; i++)
1112 printk("%c%2.2X", i ? ':' : ' ', card->dev->dev_addr[i]);
1113 printk("\n");
1114#endif
1115 leave("read_mac_address");
1116}
1117
1118
1119/*
1120 transceiver_voodoo() enables the external UTP plug thingy.
1121 it's called voodoo as I stole this code and cannot cross-reference
1122 it with the specification.
1123 */
1124static void transceiver_voodoo(struct xircom_private *card)
1125{
1126 unsigned long flags;
1127
1128 enter("transceiver_voodoo");
1129
1130 /* disable all powermanagement */
1131 pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000);
1132
1133 setup_descriptors(card);
1134
1135 spin_lock_irqsave(&card->lock, flags);
1136
1137 outl(0x0008, card->io_port + CSR15);
1138 udelay(25);
1139 outl(0xa8050000, card->io_port + CSR15);
1140 udelay(25);
1141 outl(0xa00f0000, card->io_port + CSR15);
1142 udelay(25);
1143
1144 spin_unlock_irqrestore(&card->lock, flags);
1145
1146 netif_start_queue(card->dev);
1147 leave("transceiver_voodoo");
1148}
1149
1150
1151static void xircom_up(struct xircom_private *card)
1152{
1153 unsigned long flags;
1154 int i;
1155
1156 enter("xircom_up");
1157
1158 /* disable all powermanagement */
1159 pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000);
1160
1161 setup_descriptors(card);
1162
1163 spin_lock_irqsave(&card->lock, flags);
1164
1165
1166 enable_link_interrupt(card);
1167 enable_transmit_interrupt(card);
1168 enable_receive_interrupt(card);
1169 enable_common_interrupts(card);
1170 enable_promisc(card);
1171
1172 /* The card can have received packets already, read them away now */
1173 for (i=0;i<NUMDESCRIPTORS;i++)
1174 investigate_read_descriptor(card->dev,card,i,bufferoffsets[i]);
1175
1176
1177 spin_unlock_irqrestore(&card->lock, flags);
1178 trigger_receive(card);
1179 trigger_transmit(card);
1180 netif_start_queue(card->dev);
1181 leave("xircom_up");
1182}
1183
1184/* Bufferoffset is in BYTES */
1185static void investigate_read_descriptor(struct net_device *dev,struct xircom_private *card, int descnr, unsigned int bufferoffset)
1186{
1187 int status;
1188
1189 enter("investigate_read_descriptor");
1190 status = card->rx_buffer[4*descnr];
1191
1192 if ((status > 0)) { /* packet received */
1193
1194 /* TODO: discard error packets */
1195
1196 short pkt_len = ((status >> 16) & 0x7ff) - 4; /* minus 4, we don't want the CRC */
1197 struct sk_buff *skb;
1198
1199 if (pkt_len > 1518) {
1200 printk(KERN_ERR "xircom_cb: Packet length %i is bogus \n",pkt_len);
1201 pkt_len = 1518;
1202 }
1203
1204 skb = dev_alloc_skb(pkt_len + 2);
1205 if (skb == NULL) {
1206 card->stats.rx_dropped++;
1207 goto out;
1208 }
1209 skb->dev = dev;
1210 skb_reserve(skb, 2);
1211 eth_copy_and_sum(skb, (unsigned char*)&card->rx_buffer[bufferoffset / 4], pkt_len, 0);
1212 skb_put(skb, pkt_len);
1213 skb->protocol = eth_type_trans(skb, dev);
1214 netif_rx(skb);
1215 dev->last_rx = jiffies;
1216 card->stats.rx_packets++;
1217 card->stats.rx_bytes += pkt_len;
1218
1219 out:
1220 /* give the buffer back to the card */
1221 card->rx_buffer[4*descnr] = 0x80000000;
1222 trigger_receive(card);
1223 }
1224
1225 leave("investigate_read_descriptor");
1226
1227}
1228
1229
1230/* Bufferoffset is in BYTES */
1231static void investigate_write_descriptor(struct net_device *dev, struct xircom_private *card, int descnr, unsigned int bufferoffset)
1232{
1233 int status;
1234
1235 enter("investigate_write_descriptor");
1236
1237 status = card->tx_buffer[4*descnr];
1238#if 0
1239 if (status & 0x8000) { /* Major error */
1240 printk(KERN_ERR "Major transmit error status %x \n", status);
1241 card->tx_buffer[4*descnr] = 0;
1242 netif_wake_queue (dev);
1243 }
1244#endif
1245 if (status > 0) { /* bit 31 is 0 when done */
1246 if (card->tx_skb[descnr]!=NULL) {
1247 card->stats.tx_bytes += card->tx_skb[descnr]->len;
1248 dev_kfree_skb_irq(card->tx_skb[descnr]);
1249 }
1250 card->tx_skb[descnr] = NULL;
1251 /* Bit 8 in the status field is 1 if there was a collision */
1252 if (status&(1<<8))
1253 card->stats.collisions++;
1254 card->tx_buffer[4*descnr] = 0; /* descriptor is free again */
1255 netif_wake_queue (dev);
1256 card->stats.tx_packets++;
1257 }
1258
1259 leave("investigate_write_descriptor");
1260
1261}
1262
1263
1264static int __init xircom_init(void)
1265{
1266 pci_register_driver(&xircom_ops);
1267 return 0;
1268}
1269
1270static void __exit xircom_exit(void)
1271{
1272 pci_unregister_driver(&xircom_ops);
1273}
1274
1275module_init(xircom_init)
1276module_exit(xircom_exit)
1277
diff --git a/drivers/net/tulip/xircom_tulip_cb.c b/drivers/net/tulip/xircom_tulip_cb.c
new file mode 100644
index 000000000000..32ccb26890c3
--- /dev/null
+++ b/drivers/net/tulip/xircom_tulip_cb.c
@@ -0,0 +1,1748 @@
1/* xircom_tulip_cb.c: A Xircom CBE-100 ethernet driver for Linux. */
2/*
3 Written/copyright 1994-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 The author may be reached as becker@scyld.com, or C/O
9 Scyld Computing Corporation
10 410 Severn Ave., Suite 210
11 Annapolis MD 21403
12
13 -----------------------------------------------------------
14
15 Linux kernel-specific changes:
16
17 LK1.0 (Ion Badulescu)
18 - Major cleanup
19 - Use 2.4 PCI API
20 - Support ethtool
21 - Rewrite perfect filter/hash code
22 - Use interrupts for media changes
23
24 LK1.1 (Ion Badulescu)
25 - Disallow negotiation of unsupported full-duplex modes
26*/
27
28#define DRV_NAME "xircom_tulip_cb"
29#define DRV_VERSION "0.91+LK1.1"
30#define DRV_RELDATE "October 11, 2001"
31
32#define CARDBUS 1
33
34/* A few user-configurable values. */
35
36#define xircom_debug debug
37#ifdef XIRCOM_DEBUG
38static int xircom_debug = XIRCOM_DEBUG;
39#else
40static int xircom_debug = 1;
41#endif
42
43/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
44static int max_interrupt_work = 25;
45
46#define MAX_UNITS 4
47/* Used to pass the full-duplex flag, etc. */
48static int full_duplex[MAX_UNITS];
49static int options[MAX_UNITS];
50static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
51
52/* Keep the ring sizes a power of two for efficiency.
53 Making the Tx ring too large decreases the effectiveness of channel
54 bonding and packet priority.
55 There are no ill effects from too-large receive rings. */
56#define TX_RING_SIZE 16
57#define RX_RING_SIZE 32
58
59/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
60#ifdef __alpha__
61static int rx_copybreak = 1518;
62#else
63static int rx_copybreak = 100;
64#endif
65
66/*
67 Set the bus performance register.
68 Typical: Set 16 longword cache alignment, no burst limit.
69 Cache alignment bits 15:14 Burst length 13:8
70 0000 No alignment 0x00000000 unlimited 0800 8 longwords
71 4000 8 longwords 0100 1 longword 1000 16 longwords
72 8000 16 longwords 0200 2 longwords 2000 32 longwords
73 C000 32 longwords 0400 4 longwords
74 Warning: many older 486 systems are broken and require setting 0x00A04800
75 8 longword cache alignment, 8 longword burst.
76 ToDo: Non-Intel setting could be better.
77*/
78
79#if defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
80static int csr0 = 0x01A00000 | 0xE000;
81#elif defined(__powerpc__)
82static int csr0 = 0x01B00000 | 0x8000;
83#elif defined(__sparc__)
84static int csr0 = 0x01B00080 | 0x8000;
85#elif defined(__i386__)
86static int csr0 = 0x01A00000 | 0x8000;
87#else
88#warning Processor architecture undefined!
89static int csr0 = 0x00A00000 | 0x4800;
90#endif
91
92/* Operational parameters that usually are not changed. */
93/* Time in jiffies before concluding the transmitter is hung. */
94#define TX_TIMEOUT (4 * HZ)
95#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
96#define PKT_SETUP_SZ 192 /* Size of the setup frame */
97
98/* PCI registers */
99#define PCI_POWERMGMT 0x40
100
101#include <linux/config.h>
102#include <linux/module.h>
103#include <linux/moduleparam.h>
104#include <linux/kernel.h>
105#include <linux/pci.h>
106#include <linux/netdevice.h>
107#include <linux/etherdevice.h>
108#include <linux/delay.h>
109#include <linux/init.h>
110#include <linux/mii.h>
111#include <linux/ethtool.h>
112#include <linux/crc32.h>
113
114#include <asm/io.h>
115#include <asm/processor.h> /* Processor type for cache alignment. */
116#include <asm/uaccess.h>
117
118
119/* These identify the driver base version and may not be removed. */
120static char version[] __devinitdata =
121KERN_INFO DRV_NAME ".c derived from tulip.c:v0.91 4/14/99 becker@scyld.com\n"
122KERN_INFO " unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE "\n";
123
124MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
125MODULE_DESCRIPTION("Xircom CBE-100 ethernet driver");
126MODULE_LICENSE("GPL v2");
127MODULE_VERSION(DRV_VERSION);
128
129module_param(debug, int, 0);
130module_param(max_interrupt_work, int, 0);
131module_param(rx_copybreak, int, 0);
132module_param(csr0, int, 0);
133
134module_param_array(options, int, NULL, 0);
135module_param_array(full_duplex, int, NULL, 0);
136
137#define RUN_AT(x) (jiffies + (x))
138
139/*
140 Theory of Operation
141
142I. Board Compatibility
143
144This device driver was forked from the driver for the DECchip "Tulip",
145Digital's single-chip ethernet controllers for PCI. It supports Xircom's
146almost-Tulip-compatible CBE-100 CardBus adapters.
147
148II. Board-specific settings
149
150PCI bus devices are configured by the system at boot time, so no jumpers
151need to be set on the board. The system BIOS preferably should assign the
152PCI INTA signal to an otherwise unused system IRQ line.
153
154III. Driver operation
155
156IIIa. Ring buffers
157
158The Xircom can use either ring buffers or lists of Tx and Rx descriptors.
159This driver uses statically allocated rings of Rx and Tx descriptors, set at
160compile time by RX/TX_RING_SIZE. This version of the driver allocates skbuffs
161for the Rx ring buffers at open() time and passes the skb->data field to the
162Xircom as receive data buffers. When an incoming frame is less than
163RX_COPYBREAK bytes long, a fresh skbuff is allocated and the frame is
164copied to the new skbuff. When the incoming frame is larger, the skbuff is
165passed directly up the protocol stack and replaced by a newly allocated
166skbuff.
167
168The RX_COPYBREAK value is chosen to trade-off the memory wasted by
169using a full-sized skbuff for small frames vs. the copying costs of larger
170frames. For small frames the copying cost is negligible (esp. considering
171that we are pre-loading the cache with immediately useful header
172information). For large frames the copying cost is non-trivial, and the
173larger copy might flush the cache of useful data. A subtle aspect of this
174choice is that the Xircom only receives into longword aligned buffers, thus
175the IP header at offset 14 isn't longword aligned for further processing.
176Copied frames are put into the new skbuff at an offset of "+2", thus copying
177has the beneficial effect of aligning the IP header and preloading the
178cache.
179
180IIIC. Synchronization
181The driver runs as two independent, single-threaded flows of control. One
182is the send-packet routine, which enforces single-threaded use by the
183dev->tbusy flag. The other thread is the interrupt handler, which is single
184threaded by the hardware and other software.
185
186The send packet thread has partial control over the Tx ring and 'dev->tbusy'
187flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
188queue slot is empty, it clears the tbusy flag when finished otherwise it sets
189the 'tp->tx_full' flag.
190
191The interrupt handler has exclusive control over the Rx ring and records stats
192from the Tx ring. (The Tx-done interrupt can't be selectively turned off, so
193we can't avoid the interrupt overhead by having the Tx routine reap the Tx
194stats.) After reaping the stats, it marks the queue entry as empty by setting
195the 'base' to zero. Iff the 'tp->tx_full' flag is set, it clears both the
196tx_full and tbusy flags.
197
198IV. Notes
199
200IVb. References
201
202http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203http://www.digital.com (search for current 21*4* datasheets and "21X4 SROM")
204http://www.national.com/pf/DP/DP83840A.html
205
206IVc. Errata
207
208*/
209
210/* A full-duplex map for media types. */
211enum MediaIs {
212 MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8,
213 MediaIs100=16};
214static const char media_cap[] =
215{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20 };
216
217/* Offsets to the Command and Status Registers, "CSRs". All accesses
218 must be longword instructions and quadword aligned. */
219enum xircom_offsets {
220 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
221 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
222 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x04, };
223
224/* The bits in the CSR5 status registers, mostly interrupt sources. */
225enum status_bits {
226 LinkChange=0x08000000,
227 NormalIntr=0x10000, NormalIntrMask=0x00014045,
228 AbnormalIntr=0x8000, AbnormalIntrMask=0x0a00a5a2,
229 ReservedIntrMask=0xe0001a18,
230 EarlyRxIntr=0x4000, BusErrorIntr=0x2000,
231 EarlyTxIntr=0x400, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,
232 TxFIFOUnderflow=0x20, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,
233};
234
235enum csr0_control_bits {
236 EnableMWI=0x01000000, EnableMRL=0x00800000,
237 EnableMRM=0x00200000, EqualBusPrio=0x02,
238 SoftwareReset=0x01,
239};
240
241enum csr6_control_bits {
242 ReceiveAllBit=0x40000000, AllMultiBit=0x80, PromiscBit=0x40,
243 HashFilterBit=0x01, FullDuplexBit=0x0200,
244 TxThresh10=0x400000, TxStoreForw=0x200000,
245 TxThreshMask=0xc000, TxThreshShift=14,
246 EnableTx=0x2000, EnableRx=0x02,
247 ReservedZeroMask=0x8d930134, ReservedOneMask=0x320c0000,
248 EnableTxRx=(EnableTx | EnableRx),
249};
250
251
252enum tbl_flag {
253 HAS_MII=1, HAS_ACPI=2,
254};
255static struct xircom_chip_table {
256 char *chip_name;
257 int valid_intrs; /* CSR7 interrupt enable settings */
258 int flags;
259} xircom_tbl[] = {
260 { "Xircom Cardbus Adapter",
261 LinkChange | NormalIntr | AbnormalIntr | BusErrorIntr |
262 RxDied | RxNoBuf | RxIntr | TxFIFOUnderflow | TxNoBuf | TxDied | TxIntr,
263 HAS_MII | HAS_ACPI, },
264 { NULL, },
265};
266/* This matches the table above. */
267enum chips {
268 X3201_3,
269};
270
271
272/* The Xircom Rx and Tx buffer descriptors. */
273struct xircom_rx_desc {
274 s32 status;
275 s32 length;
276 u32 buffer1, buffer2;
277};
278
279struct xircom_tx_desc {
280 s32 status;
281 s32 length;
282 u32 buffer1, buffer2; /* We use only buffer 1. */
283};
284
285enum tx_desc0_status_bits {
286 Tx0DescOwned=0x80000000, Tx0DescError=0x8000, Tx0NoCarrier=0x0800,
287 Tx0LateColl=0x0200, Tx0ManyColl=0x0100, Tx0Underflow=0x02,
288};
289enum tx_desc1_status_bits {
290 Tx1ComplIntr=0x80000000, Tx1LastSeg=0x40000000, Tx1FirstSeg=0x20000000,
291 Tx1SetupPkt=0x08000000, Tx1DisableCRC=0x04000000, Tx1RingWrap=0x02000000,
292 Tx1ChainDesc=0x01000000, Tx1NoPad=0x800000, Tx1HashSetup=0x400000,
293 Tx1WholePkt=(Tx1FirstSeg | Tx1LastSeg),
294};
295enum rx_desc0_status_bits {
296 Rx0DescOwned=0x80000000, Rx0DescError=0x8000, Rx0NoSpace=0x4000,
297 Rx0Runt=0x0800, Rx0McastPkt=0x0400, Rx0FirstSeg=0x0200, Rx0LastSeg=0x0100,
298 Rx0HugeFrame=0x80, Rx0CRCError=0x02,
299 Rx0WholePkt=(Rx0FirstSeg | Rx0LastSeg),
300};
301enum rx_desc1_status_bits {
302 Rx1RingWrap=0x02000000, Rx1ChainDesc=0x01000000,
303};
304
305struct xircom_private {
306 struct xircom_rx_desc rx_ring[RX_RING_SIZE];
307 struct xircom_tx_desc tx_ring[TX_RING_SIZE];
308 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
309 struct sk_buff* tx_skbuff[TX_RING_SIZE];
310#ifdef CARDBUS
311 /* The X3201-3 requires 4-byte aligned tx bufs */
312 struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE];
313#endif
314 /* The addresses of receive-in-place skbuffs. */
315 struct sk_buff* rx_skbuff[RX_RING_SIZE];
316 u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)]; /* Pseudo-Tx frame to init address table. */
317 int chip_id;
318 struct net_device_stats stats;
319 unsigned int cur_rx, cur_tx; /* The next free ring entry */
320 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
321 unsigned int tx_full:1; /* The Tx queue is full. */
322 unsigned int speed100:1;
323 unsigned int full_duplex:1; /* Full-duplex operation requested. */
324 unsigned int autoneg:1;
325 unsigned int default_port:4; /* Last dev->if_port value. */
326 unsigned int open:1;
327 unsigned int csr0; /* CSR0 setting. */
328 unsigned int csr6; /* Current CSR6 control settings. */
329 u16 to_advertise; /* NWay capabilities advertised. */
330 u16 advertising[4];
331 signed char phys[4], mii_cnt; /* MII device addresses. */
332 int saved_if_port;
333 struct pci_dev *pdev;
334 spinlock_t lock;
335};
336
337static int mdio_read(struct net_device *dev, int phy_id, int location);
338static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
339static void xircom_up(struct net_device *dev);
340static void xircom_down(struct net_device *dev);
341static int xircom_open(struct net_device *dev);
342static void xircom_tx_timeout(struct net_device *dev);
343static void xircom_init_ring(struct net_device *dev);
344static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev);
345static int xircom_rx(struct net_device *dev);
346static void xircom_media_change(struct net_device *dev);
347static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
348static int xircom_close(struct net_device *dev);
349static struct net_device_stats *xircom_get_stats(struct net_device *dev);
350static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
351static void set_rx_mode(struct net_device *dev);
352static void check_duplex(struct net_device *dev);
353static struct ethtool_ops ops;
354
355
356/* The Xircom cards are picky about when certain bits in CSR6 can be
357 manipulated. Keith Owens <kaos@ocs.com.au>. */
358static void outl_CSR6(u32 newcsr6, long ioaddr)
359{
360 const int strict_bits =
361 TxThresh10 | TxStoreForw | TxThreshMask | EnableTxRx | FullDuplexBit;
362 int csr5, csr5_22_20, csr5_19_17, currcsr6, attempts = 200;
363 unsigned long flags;
364 save_flags(flags);
365 cli();
366 /* mask out the reserved bits that always read 0 on the Xircom cards */
367 newcsr6 &= ~ReservedZeroMask;
368 /* or in the reserved bits that always read 1 */
369 newcsr6 |= ReservedOneMask;
370 currcsr6 = inl(ioaddr + CSR6);
371 if (((newcsr6 & strict_bits) == (currcsr6 & strict_bits)) ||
372 ((currcsr6 & ~EnableTxRx) == 0)) {
373 outl(newcsr6, ioaddr + CSR6); /* safe */
374 restore_flags(flags);
375 return;
376 }
377 /* make sure the transmitter and receiver are stopped first */
378 currcsr6 &= ~EnableTxRx;
379 while (1) {
380 csr5 = inl(ioaddr + CSR5);
381 if (csr5 == 0xffffffff)
382 break; /* cannot read csr5, card removed? */
383 csr5_22_20 = csr5 & 0x700000;
384 csr5_19_17 = csr5 & 0x0e0000;
385 if ((csr5_22_20 == 0 || csr5_22_20 == 0x600000) &&
386 (csr5_19_17 == 0 || csr5_19_17 == 0x80000 || csr5_19_17 == 0xc0000))
387 break; /* both are stopped or suspended */
388 if (!--attempts) {
389 printk(KERN_INFO DRV_NAME ": outl_CSR6 too many attempts,"
390 "csr5=0x%08x\n", csr5);
391 outl(newcsr6, ioaddr + CSR6); /* unsafe but do it anyway */
392 restore_flags(flags);
393 return;
394 }
395 outl(currcsr6, ioaddr + CSR6);
396 udelay(1);
397 }
398 /* now it is safe to change csr6 */
399 outl(newcsr6, ioaddr + CSR6);
400 restore_flags(flags);
401}
402
403
404static void __devinit read_mac_address(struct net_device *dev)
405{
406 long ioaddr = dev->base_addr;
407 int i, j;
408 unsigned char tuple, link, data_id, data_count;
409
410 /* Xircom has its address stored in the CIS;
411 * we access it through the boot rom interface for now
412 * this might not work, as the CIS is not parsed but I
413 * (danilo) use the offset I found on my card's CIS !!!
414 *
415 * Doug Ledford: I changed this routine around so that it
416 * walks the CIS memory space, parsing the config items, and
417 * finds the proper lan_node_id tuple and uses the data
418 * stored there.
419 */
420 outl(1 << 12, ioaddr + CSR9); /* enable boot rom access */
421 for (i = 0x100; i < 0x1f7; i += link+2) {
422 outl(i, ioaddr + CSR10);
423 tuple = inl(ioaddr + CSR9) & 0xff;
424 outl(i + 1, ioaddr + CSR10);
425 link = inl(ioaddr + CSR9) & 0xff;
426 outl(i + 2, ioaddr + CSR10);
427 data_id = inl(ioaddr + CSR9) & 0xff;
428 outl(i + 3, ioaddr + CSR10);
429 data_count = inl(ioaddr + CSR9) & 0xff;
430 if ( (tuple == 0x22) &&
431 (data_id == 0x04) && (data_count == 0x06) ) {
432 /*
433 * This is it. We have the data we want.
434 */
435 for (j = 0; j < 6; j++) {
436 outl(i + j + 4, ioaddr + CSR10);
437 dev->dev_addr[j] = inl(ioaddr + CSR9) & 0xff;
438 }
439 break;
440 } else if (link == 0) {
441 break;
442 }
443 }
444}
445
446
447/*
448 * locate the MII interfaces and initialize them.
449 * we disable full-duplex modes here,
450 * because we don't know how to handle them.
451 */
452static void find_mii_transceivers(struct net_device *dev)
453{
454 struct xircom_private *tp = netdev_priv(dev);
455 int phy, phy_idx;
456
457 if (media_cap[tp->default_port] & MediaIsMII) {
458 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
459 tp->to_advertise = media2advert[tp->default_port - 9];
460 } else
461 tp->to_advertise =
462 /*ADVERTISE_100BASE4 | ADVERTISE_100FULL |*/ ADVERTISE_100HALF |
463 /*ADVERTISE_10FULL |*/ ADVERTISE_10HALF | ADVERTISE_CSMA;
464
465 /* Find the connected MII xcvrs.
466 Doing this in open() would allow detecting external xcvrs later,
467 but takes much time. */
468 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
469 int mii_status = mdio_read(dev, phy, MII_BMSR);
470 if ((mii_status & (BMSR_100BASE4 | BMSR_100HALF | BMSR_10HALF)) == BMSR_100BASE4 ||
471 ((mii_status & BMSR_100BASE4) == 0 &&
472 (mii_status & (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | BMSR_10HALF)) != 0)) {
473 int mii_reg0 = mdio_read(dev, phy, MII_BMCR);
474 int mii_advert = mdio_read(dev, phy, MII_ADVERTISE);
475 int reg4 = ((mii_status >> 6) & tp->to_advertise) | ADVERTISE_CSMA;
476 tp->phys[phy_idx] = phy;
477 tp->advertising[phy_idx++] = reg4;
478 printk(KERN_INFO "%s: MII transceiver #%d "
479 "config %4.4x status %4.4x advertising %4.4x.\n",
480 dev->name, phy, mii_reg0, mii_status, mii_advert);
481 }
482 }
483 tp->mii_cnt = phy_idx;
484 if (phy_idx == 0) {
485 printk(KERN_INFO "%s: ***WARNING***: No MII transceiver found!\n",
486 dev->name);
487 tp->phys[0] = 0;
488 }
489}
490
491
492/*
493 * To quote Arjan van de Ven:
494 * transceiver_voodoo() enables the external UTP plug thingy.
495 * it's called voodoo as I stole this code and cannot cross-reference
496 * it with the specification.
497 * Actually it seems to go like this:
498 * - GPIO2 enables the MII itself so we can talk to it. The MII gets reset
499 * so any prior MII settings are lost.
500 * - GPIO0 enables the TP port so the MII can talk to the network.
501 * - a software reset will reset both GPIO pins.
502 * I also moved the software reset here, because doing it in xircom_up()
503 * required enabling the GPIO pins each time, which reset the MII each time.
504 * Thus we couldn't control the MII -- which sucks because we don't know
505 * how to handle full-duplex modes so we *must* disable them.
506 */
507static void transceiver_voodoo(struct net_device *dev)
508{
509 struct xircom_private *tp = netdev_priv(dev);
510 long ioaddr = dev->base_addr;
511
512 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
513 outl(SoftwareReset, ioaddr + CSR0);
514 udelay(2);
515
516 /* Deassert reset. */
517 outl(tp->csr0, ioaddr + CSR0);
518
519 /* Reset the xcvr interface and turn on heartbeat. */
520 outl(0x0008, ioaddr + CSR15);
521 udelay(5); /* The delays are Xircom-recommended to give the
522 * chipset time to reset the actual hardware
523 * on the PCMCIA card
524 */
525 outl(0xa8050000, ioaddr + CSR15);
526 udelay(5);
527 outl(0xa00f0000, ioaddr + CSR15);
528 udelay(5);
529
530 outl_CSR6(0, ioaddr);
531 //outl_CSR6(FullDuplexBit, ioaddr);
532}
533
534
535static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
536{
537 struct net_device *dev;
538 struct xircom_private *tp;
539 static int board_idx = -1;
540 int chip_idx = id->driver_data;
541 long ioaddr;
542 int i;
543 u8 chip_rev;
544
545/* when built into the kernel, we only print version if device is found */
546#ifndef MODULE
547 static int printed_version;
548 if (!printed_version++)
549 printk(version);
550#endif
551
552 //printk(KERN_INFO "xircom_init_one(%s)\n", pci_name(pdev));
553
554 board_idx++;
555
556 if (pci_enable_device(pdev))
557 return -ENODEV;
558
559 pci_set_master(pdev);
560
561 ioaddr = pci_resource_start(pdev, 0);
562 dev = alloc_etherdev(sizeof(*tp));
563 if (!dev) {
564 printk (KERN_ERR DRV_NAME "%d: cannot alloc etherdev, aborting\n", board_idx);
565 return -ENOMEM;
566 }
567 SET_MODULE_OWNER(dev);
568 SET_NETDEV_DEV(dev, &pdev->dev);
569
570 dev->base_addr = ioaddr;
571 dev->irq = pdev->irq;
572
573 if (pci_request_regions(pdev, dev->name)) {
574 printk (KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", board_idx);
575 goto err_out_free_netdev;
576 }
577
578 /* Bring the chip out of sleep mode.
579 Caution: Snooze mode does not work with some boards! */
580 if (xircom_tbl[chip_idx].flags & HAS_ACPI)
581 pci_write_config_dword(pdev, PCI_POWERMGMT, 0);
582
583 /* Stop the chip's Tx and Rx processes. */
584 outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr);
585 /* Clear the missed-packet counter. */
586 (volatile int)inl(ioaddr + CSR8);
587
588 tp = netdev_priv(dev);
589
590 spin_lock_init(&tp->lock);
591 tp->pdev = pdev;
592 tp->chip_id = chip_idx;
593 /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles. */
594 /* XXX: is this necessary for Xircom? */
595 tp->csr0 = csr0 & ~EnableMWI;
596
597 pci_set_drvdata(pdev, dev);
598
599 /* The lower four bits are the media type. */
600 if (board_idx >= 0 && board_idx < MAX_UNITS) {
601 tp->default_port = options[board_idx] & 15;
602 if ((options[board_idx] & 0x90) || full_duplex[board_idx] > 0)
603 tp->full_duplex = 1;
604 if (mtu[board_idx] > 0)
605 dev->mtu = mtu[board_idx];
606 }
607 if (dev->mem_start)
608 tp->default_port = dev->mem_start;
609 if (tp->default_port) {
610 if (media_cap[tp->default_port] & MediaAlwaysFD)
611 tp->full_duplex = 1;
612 }
613 if (tp->full_duplex)
614 tp->autoneg = 0;
615 else
616 tp->autoneg = 1;
617 tp->speed100 = 1;
618
619 /* The Xircom-specific entries in the device structure. */
620 dev->open = &xircom_open;
621 dev->hard_start_xmit = &xircom_start_xmit;
622 dev->stop = &xircom_close;
623 dev->get_stats = &xircom_get_stats;
624 dev->do_ioctl = &xircom_ioctl;
625#ifdef HAVE_MULTICAST
626 dev->set_multicast_list = &set_rx_mode;
627#endif
628 dev->tx_timeout = xircom_tx_timeout;
629 dev->watchdog_timeo = TX_TIMEOUT;
630 SET_ETHTOOL_OPS(dev, &ops);
631
632 transceiver_voodoo(dev);
633
634 read_mac_address(dev);
635
636 if (register_netdev(dev))
637 goto err_out_cleardev;
638
639 pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
640 printk(KERN_INFO "%s: %s rev %d at %#3lx,",
641 dev->name, xircom_tbl[chip_idx].chip_name, chip_rev, ioaddr);
642 for (i = 0; i < 6; i++)
643 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
644 printk(", IRQ %d.\n", dev->irq);
645
646 if (xircom_tbl[chip_idx].flags & HAS_MII) {
647 find_mii_transceivers(dev);
648 check_duplex(dev);
649 }
650
651 return 0;
652
653err_out_cleardev:
654 pci_set_drvdata(pdev, NULL);
655 pci_release_regions(pdev);
656err_out_free_netdev:
657 free_netdev(dev);
658 return -ENODEV;
659}
660
661
662/* MII transceiver control section.
663 Read and write the MII registers using software-generated serial
664 MDIO protocol. See the MII specifications or DP83840A data sheet
665 for details. */
666
667/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
668 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
669 "overclocking" issues or future 66Mhz PCI. */
670#define mdio_delay() inl(mdio_addr)
671
672/* Read and write the MII registers using software-generated serial
673 MDIO protocol. It is just different enough from the EEPROM protocol
674 to not share code. The maxium data clock rate is 2.5 Mhz. */
675#define MDIO_SHIFT_CLK 0x10000
676#define MDIO_DATA_WRITE0 0x00000
677#define MDIO_DATA_WRITE1 0x20000
678#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
679#define MDIO_ENB_IN 0x40000
680#define MDIO_DATA_READ 0x80000
681
682static int mdio_read(struct net_device *dev, int phy_id, int location)
683{
684 int i;
685 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
686 int retval = 0;
687 long ioaddr = dev->base_addr;
688 long mdio_addr = ioaddr + CSR9;
689
690 /* Establish sync by sending at least 32 logic ones. */
691 for (i = 32; i >= 0; i--) {
692 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
693 mdio_delay();
694 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
695 mdio_delay();
696 }
697 /* Shift the read command bits out. */
698 for (i = 15; i >= 0; i--) {
699 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
700
701 outl(MDIO_ENB | dataval, mdio_addr);
702 mdio_delay();
703 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
704 mdio_delay();
705 }
706 /* Read the two transition, 16 data, and wire-idle bits. */
707 for (i = 19; i > 0; i--) {
708 outl(MDIO_ENB_IN, mdio_addr);
709 mdio_delay();
710 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
711 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
712 mdio_delay();
713 }
714 return (retval>>1) & 0xffff;
715}
716
717
718static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
719{
720 int i;
721 int cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
722 long ioaddr = dev->base_addr;
723 long mdio_addr = ioaddr + CSR9;
724
725 /* Establish sync by sending 32 logic ones. */
726 for (i = 32; i >= 0; i--) {
727 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
728 mdio_delay();
729 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
730 mdio_delay();
731 }
732 /* Shift the command bits out. */
733 for (i = 31; i >= 0; i--) {
734 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
735 outl(MDIO_ENB | dataval, mdio_addr);
736 mdio_delay();
737 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
738 mdio_delay();
739 }
740 /* Clear out extra bits. */
741 for (i = 2; i > 0; i--) {
742 outl(MDIO_ENB_IN, mdio_addr);
743 mdio_delay();
744 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
745 mdio_delay();
746 }
747 return;
748}
749
750
751static void
752xircom_up(struct net_device *dev)
753{
754 struct xircom_private *tp = netdev_priv(dev);
755 long ioaddr = dev->base_addr;
756 int i;
757
758 xircom_init_ring(dev);
759 /* Clear the tx ring */
760 for (i = 0; i < TX_RING_SIZE; i++) {
761 tp->tx_skbuff[i] = NULL;
762 tp->tx_ring[i].status = 0;
763 }
764
765 if (xircom_debug > 1)
766 printk(KERN_DEBUG "%s: xircom_up() irq %d.\n", dev->name, dev->irq);
767
768 outl(virt_to_bus(tp->rx_ring), ioaddr + CSR3);
769 outl(virt_to_bus(tp->tx_ring), ioaddr + CSR4);
770
771 tp->saved_if_port = dev->if_port;
772 if (dev->if_port == 0)
773 dev->if_port = tp->default_port;
774
775 tp->csr6 = TxThresh10 /*| FullDuplexBit*/; /* XXX: why 10 and not 100? */
776
777 set_rx_mode(dev);
778
779 /* Start the chip's Tx to process setup frame. */
780 outl_CSR6(tp->csr6, ioaddr);
781 outl_CSR6(tp->csr6 | EnableTx, ioaddr);
782
783 /* Acknowledge all outstanding interrupts sources */
784 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
785 /* Enable interrupts by setting the interrupt mask. */
786 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
787 /* Enable Rx */
788 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
789 /* Rx poll demand */
790 outl(0, ioaddr + CSR2);
791
792 /* Tell the net layer we're ready */
793 netif_start_queue (dev);
794
795 /* Check current media state */
796 xircom_media_change(dev);
797
798 if (xircom_debug > 2) {
799 printk(KERN_DEBUG "%s: Done xircom_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
800 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5),
801 inl(ioaddr + CSR6));
802 }
803}
804
805
806static int
807xircom_open(struct net_device *dev)
808{
809 struct xircom_private *tp = netdev_priv(dev);
810
811 if (request_irq(dev->irq, &xircom_interrupt, SA_SHIRQ, dev->name, dev))
812 return -EAGAIN;
813
814 xircom_up(dev);
815 tp->open = 1;
816
817 return 0;
818}
819
820
821static void xircom_tx_timeout(struct net_device *dev)
822{
823 struct xircom_private *tp = netdev_priv(dev);
824 long ioaddr = dev->base_addr;
825
826 if (media_cap[dev->if_port] & MediaIsMII) {
827 /* Do nothing -- the media monitor should handle this. */
828 if (xircom_debug > 1)
829 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
830 dev->name);
831 }
832
833#if defined(way_too_many_messages)
834 if (xircom_debug > 3) {
835 int i;
836 for (i = 0; i < RX_RING_SIZE; i++) {
837 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
838 int j;
839 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
840 "%2.2x %2.2x %2.2x.\n",
841 i, (unsigned int)tp->rx_ring[i].status,
842 (unsigned int)tp->rx_ring[i].length,
843 (unsigned int)tp->rx_ring[i].buffer1,
844 (unsigned int)tp->rx_ring[i].buffer2,
845 buf[0], buf[1], buf[2]);
846 for (j = 0; buf[j] != 0xee && j < 1600; j++)
847 if (j < 100) printk(" %2.2x", buf[j]);
848 printk(" j=%d.\n", j);
849 }
850 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
851 for (i = 0; i < RX_RING_SIZE; i++)
852 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
853 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
854 for (i = 0; i < TX_RING_SIZE; i++)
855 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
856 printk("\n");
857 }
858#endif
859
860 /* Stop and restart the chip's Tx/Rx processes . */
861 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
862 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
863 /* Trigger an immediate transmit demand. */
864 outl(0, ioaddr + CSR1);
865
866 dev->trans_start = jiffies;
867 netif_wake_queue (dev);
868 tp->stats.tx_errors++;
869}
870
871
872/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
873static void xircom_init_ring(struct net_device *dev)
874{
875 struct xircom_private *tp = netdev_priv(dev);
876 int i;
877
878 tp->tx_full = 0;
879 tp->cur_rx = tp->cur_tx = 0;
880 tp->dirty_rx = tp->dirty_tx = 0;
881
882 for (i = 0; i < RX_RING_SIZE; i++) {
883 tp->rx_ring[i].status = 0;
884 tp->rx_ring[i].length = PKT_BUF_SZ;
885 tp->rx_ring[i].buffer2 = virt_to_bus(&tp->rx_ring[i+1]);
886 tp->rx_skbuff[i] = NULL;
887 }
888 /* Mark the last entry as wrapping the ring. */
889 tp->rx_ring[i-1].length = PKT_BUF_SZ | Rx1RingWrap;
890 tp->rx_ring[i-1].buffer2 = virt_to_bus(&tp->rx_ring[0]);
891
892 for (i = 0; i < RX_RING_SIZE; i++) {
893 /* Note the receive buffer must be longword aligned.
894 dev_alloc_skb() provides 16 byte alignment. But do *not*
895 use skb_reserve() to align the IP header! */
896 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
897 tp->rx_skbuff[i] = skb;
898 if (skb == NULL)
899 break;
900 skb->dev = dev; /* Mark as being used by this device. */
901 tp->rx_ring[i].status = Rx0DescOwned; /* Owned by Xircom chip */
902 tp->rx_ring[i].buffer1 = virt_to_bus(skb->tail);
903 }
904 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
905
906 /* The Tx buffer descriptor is filled in as needed, but we
907 do need to clear the ownership bit. */
908 for (i = 0; i < TX_RING_SIZE; i++) {
909 tp->tx_skbuff[i] = NULL;
910 tp->tx_ring[i].status = 0;
911 tp->tx_ring[i].buffer2 = virt_to_bus(&tp->tx_ring[i+1]);
912#ifdef CARDBUS
913 if (tp->chip_id == X3201_3)
914 tp->tx_aligned_skbuff[i] = dev_alloc_skb(PKT_BUF_SZ);
915#endif /* CARDBUS */
916 }
917 tp->tx_ring[i-1].buffer2 = virt_to_bus(&tp->tx_ring[0]);
918}
919
920
921static int
922xircom_start_xmit(struct sk_buff *skb, struct net_device *dev)
923{
924 struct xircom_private *tp = netdev_priv(dev);
925 int entry;
926 u32 flag;
927
928 /* Caution: the write order is important here, set the base address
929 with the "ownership" bits last. */
930
931 /* Calculate the next Tx descriptor entry. */
932 entry = tp->cur_tx % TX_RING_SIZE;
933
934 tp->tx_skbuff[entry] = skb;
935#ifdef CARDBUS
936 if (tp->chip_id == X3201_3) {
937 memcpy(tp->tx_aligned_skbuff[entry]->data,skb->data,skb->len);
938 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->tx_aligned_skbuff[entry]->data);
939 } else
940#endif
941 tp->tx_ring[entry].buffer1 = virt_to_bus(skb->data);
942
943 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
944 flag = Tx1WholePkt; /* No interrupt */
945 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
946 flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */
947 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
948 flag = Tx1WholePkt; /* No Tx-done intr. */
949 } else {
950 /* Leave room for set_rx_mode() to fill entries. */
951 flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */
952 tp->tx_full = 1;
953 }
954 if (entry == TX_RING_SIZE - 1)
955 flag |= Tx1WholePkt | Tx1ComplIntr | Tx1RingWrap;
956
957 tp->tx_ring[entry].length = skb->len | flag;
958 tp->tx_ring[entry].status = Tx0DescOwned; /* Pass ownership to the chip. */
959 tp->cur_tx++;
960 if (tp->tx_full)
961 netif_stop_queue (dev);
962 else
963 netif_wake_queue (dev);
964
965 /* Trigger an immediate transmit demand. */
966 outl(0, dev->base_addr + CSR1);
967
968 dev->trans_start = jiffies;
969
970 return 0;
971}
972
973
974static void xircom_media_change(struct net_device *dev)
975{
976 struct xircom_private *tp = netdev_priv(dev);
977 long ioaddr = dev->base_addr;
978 u16 reg0, reg1, reg4, reg5;
979 u32 csr6 = inl(ioaddr + CSR6), newcsr6;
980
981 /* reset status first */
982 mdio_read(dev, tp->phys[0], MII_BMCR);
983 mdio_read(dev, tp->phys[0], MII_BMSR);
984
985 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
986 reg1 = mdio_read(dev, tp->phys[0], MII_BMSR);
987
988 if (reg1 & BMSR_LSTATUS) {
989 /* link is up */
990 if (reg0 & BMCR_ANENABLE) {
991 /* autonegotiation is enabled */
992 reg4 = mdio_read(dev, tp->phys[0], MII_ADVERTISE);
993 reg5 = mdio_read(dev, tp->phys[0], MII_LPA);
994 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
995 tp->speed100 = 1;
996 tp->full_duplex = 1;
997 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
998 tp->speed100 = 1;
999 tp->full_duplex = 0;
1000 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1001 tp->speed100 = 0;
1002 tp->full_duplex = 1;
1003 } else {
1004 tp->speed100 = 0;
1005 tp->full_duplex = 0;
1006 }
1007 } else {
1008 /* autonegotiation is disabled */
1009 if (reg0 & BMCR_SPEED100)
1010 tp->speed100 = 1;
1011 else
1012 tp->speed100 = 0;
1013 if (reg0 & BMCR_FULLDPLX)
1014 tp->full_duplex = 1;
1015 else
1016 tp->full_duplex = 0;
1017 }
1018 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1019 dev->name,
1020 tp->speed100 ? "100" : "10",
1021 tp->full_duplex ? "full" : "half");
1022 netif_carrier_on(dev);
1023 newcsr6 = csr6 & ~FullDuplexBit;
1024 if (tp->full_duplex)
1025 newcsr6 |= FullDuplexBit;
1026 if (newcsr6 != csr6)
1027 outl_CSR6(newcsr6, ioaddr + CSR6);
1028 } else {
1029 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1030 netif_carrier_off(dev);
1031 }
1032}
1033
1034
1035static void check_duplex(struct net_device *dev)
1036{
1037 struct xircom_private *tp = netdev_priv(dev);
1038 u16 reg0;
1039
1040 mdio_write(dev, tp->phys[0], MII_BMCR, BMCR_RESET);
1041 udelay(500);
1042 while (mdio_read(dev, tp->phys[0], MII_BMCR) & BMCR_RESET);
1043
1044 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1045 mdio_write(dev, tp->phys[0], MII_ADVERTISE, tp->advertising[0]);
1046
1047 if (tp->autoneg) {
1048 reg0 &= ~(BMCR_SPEED100 | BMCR_FULLDPLX);
1049 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1050 } else {
1051 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1052 if (tp->speed100)
1053 reg0 |= BMCR_SPEED100;
1054 if (tp->full_duplex)
1055 reg0 |= BMCR_FULLDPLX;
1056 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1057 dev->name,
1058 tp->speed100 ? "100" : "10",
1059 tp->full_duplex ? "full" : "half");
1060 }
1061 mdio_write(dev, tp->phys[0], MII_BMCR, reg0);
1062}
1063
1064
1065/* The interrupt handler does all of the Rx thread work and cleans up
1066 after the Tx thread. */
1067static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1068{
1069 struct net_device *dev = dev_instance;
1070 struct xircom_private *tp = netdev_priv(dev);
1071 long ioaddr = dev->base_addr;
1072 int csr5, work_budget = max_interrupt_work;
1073 int handled = 0;
1074
1075 spin_lock (&tp->lock);
1076
1077 do {
1078 csr5 = inl(ioaddr + CSR5);
1079 /* Acknowledge all of the current interrupt sources ASAP. */
1080 outl(csr5 & 0x0001ffff, ioaddr + CSR5);
1081
1082 if (xircom_debug > 4)
1083 printk(KERN_DEBUG "%s: interrupt csr5=%#8.8x new csr5=%#8.8x.\n",
1084 dev->name, csr5, inl(dev->base_addr + CSR5));
1085
1086 if (csr5 == 0xffffffff)
1087 break; /* all bits set, assume PCMCIA card removed */
1088
1089 if ((csr5 & (NormalIntr|AbnormalIntr)) == 0)
1090 break;
1091
1092 handled = 1;
1093
1094 if (csr5 & (RxIntr | RxNoBuf))
1095 work_budget -= xircom_rx(dev);
1096
1097 if (csr5 & (TxNoBuf | TxDied | TxIntr)) {
1098 unsigned int dirty_tx;
1099
1100 for (dirty_tx = tp->dirty_tx; tp->cur_tx - dirty_tx > 0;
1101 dirty_tx++) {
1102 int entry = dirty_tx % TX_RING_SIZE;
1103 int status = tp->tx_ring[entry].status;
1104
1105 if (status < 0)
1106 break; /* It still hasn't been Txed */
1107 /* Check for Rx filter setup frames. */
1108 if (tp->tx_skbuff[entry] == NULL)
1109 continue;
1110
1111 if (status & Tx0DescError) {
1112 /* There was an major error, log it. */
1113#ifndef final_version
1114 if (xircom_debug > 1)
1115 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1116 dev->name, status);
1117#endif
1118 tp->stats.tx_errors++;
1119 if (status & Tx0ManyColl) {
1120 tp->stats.tx_aborted_errors++;
1121 }
1122 if (status & Tx0NoCarrier) tp->stats.tx_carrier_errors++;
1123 if (status & Tx0LateColl) tp->stats.tx_window_errors++;
1124 if (status & Tx0Underflow) tp->stats.tx_fifo_errors++;
1125 } else {
1126 tp->stats.tx_bytes += tp->tx_ring[entry].length & 0x7ff;
1127 tp->stats.collisions += (status >> 3) & 15;
1128 tp->stats.tx_packets++;
1129 }
1130
1131 /* Free the original skb. */
1132 dev_kfree_skb_irq(tp->tx_skbuff[entry]);
1133 tp->tx_skbuff[entry] = NULL;
1134 }
1135
1136#ifndef final_version
1137 if (tp->cur_tx - dirty_tx > TX_RING_SIZE) {
1138 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1139 dev->name, dirty_tx, tp->cur_tx, tp->tx_full);
1140 dirty_tx += TX_RING_SIZE;
1141 }
1142#endif
1143
1144 if (tp->tx_full &&
1145 tp->cur_tx - dirty_tx < TX_RING_SIZE - 2)
1146 /* The ring is no longer full */
1147 tp->tx_full = 0;
1148
1149 if (tp->tx_full)
1150 netif_stop_queue (dev);
1151 else
1152 netif_wake_queue (dev);
1153
1154 tp->dirty_tx = dirty_tx;
1155 if (csr5 & TxDied) {
1156 if (xircom_debug > 2)
1157 printk(KERN_WARNING "%s: The transmitter stopped."
1158 " CSR5 is %x, CSR6 %x, new CSR6 %x.\n",
1159 dev->name, csr5, inl(ioaddr + CSR6), tp->csr6);
1160 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
1161 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1162 }
1163 }
1164
1165 /* Log errors. */
1166 if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */
1167 if (csr5 & LinkChange)
1168 xircom_media_change(dev);
1169 if (csr5 & TxFIFOUnderflow) {
1170 if ((tp->csr6 & TxThreshMask) != TxThreshMask)
1171 tp->csr6 += (1 << TxThreshShift); /* Bump up the Tx threshold */
1172 else
1173 tp->csr6 |= TxStoreForw; /* Store-n-forward. */
1174 /* Restart the transmit process. */
1175 outl_CSR6(tp->csr6 | EnableRx, ioaddr);
1176 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1177 }
1178 if (csr5 & RxDied) { /* Missed a Rx frame. */
1179 tp->stats.rx_errors++;
1180 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1181 outl_CSR6(tp->csr6 | EnableTxRx, ioaddr);
1182 }
1183 /* Clear all error sources, included undocumented ones! */
1184 outl(0x0800f7ba, ioaddr + CSR5);
1185 }
1186 if (--work_budget < 0) {
1187 if (xircom_debug > 1)
1188 printk(KERN_WARNING "%s: Too much work during an interrupt, "
1189 "csr5=0x%8.8x.\n", dev->name, csr5);
1190 /* Acknowledge all interrupt sources. */
1191 outl(0x8001ffff, ioaddr + CSR5);
1192 break;
1193 }
1194 } while (1);
1195
1196 if (xircom_debug > 3)
1197 printk(KERN_DEBUG "%s: exiting interrupt, csr5=%#4.4x.\n",
1198 dev->name, inl(ioaddr + CSR5));
1199
1200 spin_unlock (&tp->lock);
1201 return IRQ_RETVAL(handled);
1202}
1203
1204
1205static int
1206xircom_rx(struct net_device *dev)
1207{
1208 struct xircom_private *tp = netdev_priv(dev);
1209 int entry = tp->cur_rx % RX_RING_SIZE;
1210 int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx;
1211 int work_done = 0;
1212
1213 if (xircom_debug > 4)
1214 printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry,
1215 tp->rx_ring[entry].status);
1216 /* If we own the next entry, it's a new packet. Send it up. */
1217 while (tp->rx_ring[entry].status >= 0) {
1218 s32 status = tp->rx_ring[entry].status;
1219
1220 if (xircom_debug > 5)
1221 printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry,
1222 tp->rx_ring[entry].status);
1223 if (--rx_work_limit < 0)
1224 break;
1225 if ((status & 0x38008300) != 0x0300) {
1226 if ((status & 0x38000300) != 0x0300) {
1227 /* Ignore earlier buffers. */
1228 if ((status & 0xffff) != 0x7fff) {
1229 if (xircom_debug > 1)
1230 printk(KERN_WARNING "%s: Oversized Ethernet frame "
1231 "spanned multiple buffers, status %8.8x!\n",
1232 dev->name, status);
1233 tp->stats.rx_length_errors++;
1234 }
1235 } else if (status & Rx0DescError) {
1236 /* There was a fatal error. */
1237 if (xircom_debug > 2)
1238 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1239 dev->name, status);
1240 tp->stats.rx_errors++; /* end of a packet.*/
1241 if (status & (Rx0Runt | Rx0HugeFrame)) tp->stats.rx_length_errors++;
1242 if (status & Rx0CRCError) tp->stats.rx_crc_errors++;
1243 }
1244 } else {
1245 /* Omit the four octet CRC from the length. */
1246 short pkt_len = ((status >> 16) & 0x7ff) - 4;
1247 struct sk_buff *skb;
1248
1249#ifndef final_version
1250 if (pkt_len > 1518) {
1251 printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n",
1252 dev->name, pkt_len, pkt_len);
1253 pkt_len = 1518;
1254 tp->stats.rx_length_errors++;
1255 }
1256#endif
1257 /* Check if the packet is long enough to accept without copying
1258 to a minimally-sized skbuff. */
1259 if (pkt_len < rx_copybreak
1260 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1261 skb->dev = dev;
1262 skb_reserve(skb, 2); /* 16 byte align the IP header */
1263#if ! defined(__alpha__)
1264 eth_copy_and_sum(skb, bus_to_virt(tp->rx_ring[entry].buffer1),
1265 pkt_len, 0);
1266 skb_put(skb, pkt_len);
1267#else
1268 memcpy(skb_put(skb, pkt_len),
1269 bus_to_virt(tp->rx_ring[entry].buffer1), pkt_len);
1270#endif
1271 work_done++;
1272 } else { /* Pass up the skb already on the Rx ring. */
1273 skb_put(skb = tp->rx_skbuff[entry], pkt_len);
1274 tp->rx_skbuff[entry] = NULL;
1275 }
1276 skb->protocol = eth_type_trans(skb, dev);
1277 netif_rx(skb);
1278 dev->last_rx = jiffies;
1279 tp->stats.rx_packets++;
1280 tp->stats.rx_bytes += pkt_len;
1281 }
1282 entry = (++tp->cur_rx) % RX_RING_SIZE;
1283 }
1284
1285 /* Refill the Rx ring buffers. */
1286 for (; tp->cur_rx - tp->dirty_rx > 0; tp->dirty_rx++) {
1287 entry = tp->dirty_rx % RX_RING_SIZE;
1288 if (tp->rx_skbuff[entry] == NULL) {
1289 struct sk_buff *skb;
1290 skb = tp->rx_skbuff[entry] = dev_alloc_skb(PKT_BUF_SZ);
1291 if (skb == NULL)
1292 break;
1293 skb->dev = dev; /* Mark as being used by this device. */
1294 tp->rx_ring[entry].buffer1 = virt_to_bus(skb->tail);
1295 work_done++;
1296 }
1297 tp->rx_ring[entry].status = Rx0DescOwned;
1298 }
1299
1300 return work_done;
1301}
1302
1303
1304static void
1305xircom_down(struct net_device *dev)
1306{
1307 long ioaddr = dev->base_addr;
1308 struct xircom_private *tp = netdev_priv(dev);
1309
1310 /* Disable interrupts by clearing the interrupt mask. */
1311 outl(0, ioaddr + CSR7);
1312 /* Stop the chip's Tx and Rx processes. */
1313 outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr);
1314
1315 if (inl(ioaddr + CSR6) != 0xffffffff)
1316 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1317
1318 dev->if_port = tp->saved_if_port;
1319}
1320
1321
1322static int
1323xircom_close(struct net_device *dev)
1324{
1325 long ioaddr = dev->base_addr;
1326 struct xircom_private *tp = netdev_priv(dev);
1327 int i;
1328
1329 if (xircom_debug > 1)
1330 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1331 dev->name, inl(ioaddr + CSR5));
1332
1333 netif_stop_queue(dev);
1334
1335 if (netif_device_present(dev))
1336 xircom_down(dev);
1337
1338 free_irq(dev->irq, dev);
1339
1340 /* Free all the skbuffs in the Rx queue. */
1341 for (i = 0; i < RX_RING_SIZE; i++) {
1342 struct sk_buff *skb = tp->rx_skbuff[i];
1343 tp->rx_skbuff[i] = NULL;
1344 tp->rx_ring[i].status = 0; /* Not owned by Xircom chip. */
1345 tp->rx_ring[i].length = 0;
1346 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
1347 if (skb) {
1348 dev_kfree_skb(skb);
1349 }
1350 }
1351 for (i = 0; i < TX_RING_SIZE; i++) {
1352 if (tp->tx_skbuff[i])
1353 dev_kfree_skb(tp->tx_skbuff[i]);
1354 tp->tx_skbuff[i] = NULL;
1355 }
1356
1357 tp->open = 0;
1358 return 0;
1359}
1360
1361
1362static struct net_device_stats *xircom_get_stats(struct net_device *dev)
1363{
1364 struct xircom_private *tp = netdev_priv(dev);
1365 long ioaddr = dev->base_addr;
1366
1367 if (netif_device_present(dev))
1368 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
1369
1370 return &tp->stats;
1371}
1372
1373static int xircom_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1374{
1375 struct xircom_private *tp = netdev_priv(dev);
1376 ecmd->supported =
1377 SUPPORTED_10baseT_Half |
1378 SUPPORTED_10baseT_Full |
1379 SUPPORTED_100baseT_Half |
1380 SUPPORTED_100baseT_Full |
1381 SUPPORTED_Autoneg |
1382 SUPPORTED_MII;
1383
1384 ecmd->advertising = ADVERTISED_MII;
1385 if (tp->advertising[0] & ADVERTISE_10HALF)
1386 ecmd->advertising |= ADVERTISED_10baseT_Half;
1387 if (tp->advertising[0] & ADVERTISE_10FULL)
1388 ecmd->advertising |= ADVERTISED_10baseT_Full;
1389 if (tp->advertising[0] & ADVERTISE_100HALF)
1390 ecmd->advertising |= ADVERTISED_100baseT_Half;
1391 if (tp->advertising[0] & ADVERTISE_100FULL)
1392 ecmd->advertising |= ADVERTISED_100baseT_Full;
1393 if (tp->autoneg) {
1394 ecmd->advertising |= ADVERTISED_Autoneg;
1395 ecmd->autoneg = AUTONEG_ENABLE;
1396 } else
1397 ecmd->autoneg = AUTONEG_DISABLE;
1398
1399 ecmd->port = PORT_MII;
1400 ecmd->transceiver = XCVR_INTERNAL;
1401 ecmd->phy_address = tp->phys[0];
1402 ecmd->speed = tp->speed100 ? SPEED_100 : SPEED_10;
1403 ecmd->duplex = tp->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1404 ecmd->maxtxpkt = TX_RING_SIZE / 2;
1405 ecmd->maxrxpkt = 0;
1406 return 0;
1407}
1408
1409static int xircom_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1410{
1411 struct xircom_private *tp = netdev_priv(dev);
1412 u16 autoneg, speed100, full_duplex;
1413
1414 autoneg = (ecmd->autoneg == AUTONEG_ENABLE);
1415 speed100 = (ecmd->speed == SPEED_100);
1416 full_duplex = (ecmd->duplex == DUPLEX_FULL);
1417
1418 tp->autoneg = autoneg;
1419 if (speed100 != tp->speed100 ||
1420 full_duplex != tp->full_duplex) {
1421 tp->speed100 = speed100;
1422 tp->full_duplex = full_duplex;
1423 /* change advertising bits */
1424 tp->advertising[0] &= ~(ADVERTISE_10HALF |
1425 ADVERTISE_10FULL |
1426 ADVERTISE_100HALF |
1427 ADVERTISE_100FULL |
1428 ADVERTISE_100BASE4);
1429 if (speed100) {
1430 if (full_duplex)
1431 tp->advertising[0] |= ADVERTISE_100FULL;
1432 else
1433 tp->advertising[0] |= ADVERTISE_100HALF;
1434 } else {
1435 if (full_duplex)
1436 tp->advertising[0] |= ADVERTISE_10FULL;
1437 else
1438 tp->advertising[0] |= ADVERTISE_10HALF;
1439 }
1440 }
1441 check_duplex(dev);
1442 return 0;
1443}
1444
1445static void xircom_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1446{
1447 struct xircom_private *tp = netdev_priv(dev);
1448 strcpy(info->driver, DRV_NAME);
1449 strcpy(info->version, DRV_VERSION);
1450 strcpy(info->bus_info, pci_name(tp->pdev));
1451}
1452
1453static struct ethtool_ops ops = {
1454 .get_settings = xircom_get_settings,
1455 .set_settings = xircom_set_settings,
1456 .get_drvinfo = xircom_get_drvinfo,
1457};
1458
1459/* Provide ioctl() calls to examine the MII xcvr state. */
1460static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1461{
1462 struct xircom_private *tp = netdev_priv(dev);
1463 u16 *data = (u16 *)&rq->ifr_ifru;
1464 int phy = tp->phys[0] & 0x1f;
1465 unsigned long flags;
1466
1467 switch(cmd) {
1468 /* Legacy mii-diag interface */
1469 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1470 if (tp->mii_cnt)
1471 data[0] = phy;
1472 else
1473 return -ENODEV;
1474 return 0;
1475 case SIOCGMIIREG: /* Read MII PHY register. */
1476 save_flags(flags);
1477 cli();
1478 data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f);
1479 restore_flags(flags);
1480 return 0;
1481 case SIOCSMIIREG: /* Write MII PHY register. */
1482 if (!capable(CAP_NET_ADMIN))
1483 return -EPERM;
1484 save_flags(flags);
1485 cli();
1486 if (data[0] == tp->phys[0]) {
1487 u16 value = data[2];
1488 switch (data[1]) {
1489 case 0:
1490 if (value & (BMCR_RESET | BMCR_ANENABLE))
1491 /* Autonegotiation. */
1492 tp->autoneg = 1;
1493 else {
1494 tp->full_duplex = (value & BMCR_FULLDPLX) ? 1 : 0;
1495 tp->autoneg = 0;
1496 }
1497 break;
1498 case 4:
1499 tp->advertising[0] = value;
1500 break;
1501 }
1502 check_duplex(dev);
1503 }
1504 mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1505 restore_flags(flags);
1506 return 0;
1507 default:
1508 return -EOPNOTSUPP;
1509 }
1510
1511 return -EOPNOTSUPP;
1512}
1513
1514/* Set or clear the multicast filter for this adaptor.
1515 Note that we only use exclusion around actually queueing the
1516 new frame, not around filling tp->setup_frame. This is non-deterministic
1517 when re-entered but still correct. */
1518static void set_rx_mode(struct net_device *dev)
1519{
1520 struct xircom_private *tp = netdev_priv(dev);
1521 struct dev_mc_list *mclist;
1522 long ioaddr = dev->base_addr;
1523 int csr6 = inl(ioaddr + CSR6);
1524 u16 *eaddrs, *setup_frm;
1525 u32 tx_flags;
1526 int i;
1527
1528 tp->csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit);
1529 csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit);
1530 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1531 tp->csr6 |= PromiscBit;
1532 csr6 |= PromiscBit;
1533 goto out;
1534 }
1535
1536 if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1537 /* Too many to filter well -- accept all multicasts. */
1538 tp->csr6 |= AllMultiBit;
1539 csr6 |= AllMultiBit;
1540 goto out;
1541 }
1542
1543 tx_flags = Tx1WholePkt | Tx1SetupPkt | PKT_SETUP_SZ;
1544
1545 /* Note that only the low-address shortword of setup_frame is valid! */
1546 setup_frm = tp->setup_frame;
1547 mclist = dev->mc_list;
1548
1549 /* Fill the first entry with our physical address. */
1550 eaddrs = (u16 *)dev->dev_addr;
1551 *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2;
1552 *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2;
1553 *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2;
1554
1555 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1556 u32 *hash_table = (u32 *)(tp->setup_frame + 4 * 12);
1557 u32 hash, hash2;
1558
1559 tx_flags |= Tx1HashSetup;
1560 tp->csr6 |= HashFilterBit;
1561 csr6 |= HashFilterBit;
1562
1563 /* Fill the unused 3 entries with the broadcast address.
1564 At least one entry *must* contain the broadcast address!!!*/
1565 for (i = 0; i < 3; i++) {
1566 *setup_frm = 0xffff; setup_frm += 2;
1567 *setup_frm = 0xffff; setup_frm += 2;
1568 *setup_frm = 0xffff; setup_frm += 2;
1569 }
1570
1571 /* Truly brain-damaged hash filter layout */
1572 /* XXX: not sure if I should take the last or the first 9 bits */
1573 for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) {
1574 u32 *hptr;
1575 hash = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
1576 if (hash < 384) {
1577 hash2 = hash + ((hash >> 4) << 4) +
1578 ((hash >> 5) << 5);
1579 } else {
1580 hash -= 384;
1581 hash2 = 64 + hash + (hash >> 4) * 80;
1582 }
1583 hptr = &hash_table[hash2 & ~0x1f];
1584 *hptr |= cpu_to_le32(1 << (hash2 & 0x1f));
1585 }
1586 } else {
1587 /* We have <= 14 mcast addresses so we can use Xircom's
1588 wonderful 16-address perfect filter. */
1589 for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) {
1590 eaddrs = (u16 *)mclist->dmi_addr;
1591 *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2;
1592 *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2;
1593 *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2;
1594 }
1595 /* Fill the unused entries with the broadcast address.
1596 At least one entry *must* contain the broadcast address!!!*/
1597 for (; i < 15; i++) {
1598 *setup_frm = 0xffff; setup_frm += 2;
1599 *setup_frm = 0xffff; setup_frm += 2;
1600 *setup_frm = 0xffff; setup_frm += 2;
1601 }
1602 }
1603
1604 /* Now add this frame to the Tx list. */
1605 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1606 /* Same setup recently queued, we need not add it. */
1607 /* XXX: Huh? All it means is that the Tx list is full...*/
1608 } else {
1609 unsigned long flags;
1610 unsigned int entry;
1611 int dummy = -1;
1612
1613 save_flags(flags); cli();
1614 entry = tp->cur_tx++ % TX_RING_SIZE;
1615
1616 if (entry != 0) {
1617 /* Avoid a chip errata by prefixing a dummy entry. */
1618 tp->tx_skbuff[entry] = NULL;
1619 tp->tx_ring[entry].length =
1620 (entry == TX_RING_SIZE - 1) ? Tx1RingWrap : 0;
1621 tp->tx_ring[entry].buffer1 = 0;
1622 /* race with chip, set Tx0DescOwned later */
1623 dummy = entry;
1624 entry = tp->cur_tx++ % TX_RING_SIZE;
1625 }
1626
1627 tp->tx_skbuff[entry] = NULL;
1628 /* Put the setup frame on the Tx list. */
1629 if (entry == TX_RING_SIZE - 1)
1630 tx_flags |= Tx1RingWrap; /* Wrap ring. */
1631 tp->tx_ring[entry].length = tx_flags;
1632 tp->tx_ring[entry].buffer1 = virt_to_bus(tp->setup_frame);
1633 tp->tx_ring[entry].status = Tx0DescOwned;
1634 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2) {
1635 tp->tx_full = 1;
1636 netif_stop_queue (dev);
1637 }
1638 if (dummy >= 0)
1639 tp->tx_ring[dummy].status = Tx0DescOwned;
1640 restore_flags(flags);
1641 /* Trigger an immediate transmit demand. */
1642 outl(0, ioaddr + CSR1);
1643 }
1644
1645out:
1646 outl_CSR6(csr6, ioaddr);
1647}
1648
1649
1650static struct pci_device_id xircom_pci_table[] = {
1651 { 0x115D, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, X3201_3 },
1652 {0},
1653};
1654MODULE_DEVICE_TABLE(pci, xircom_pci_table);
1655
1656
1657#ifdef CONFIG_PM
1658static int xircom_suspend(struct pci_dev *pdev, u32 state)
1659{
1660 struct net_device *dev = pci_get_drvdata(pdev);
1661 struct xircom_private *tp = netdev_priv(dev);
1662 printk(KERN_INFO "xircom_suspend(%s)\n", dev->name);
1663 if (tp->open)
1664 xircom_down(dev);
1665
1666 pci_save_state(pdev);
1667 pci_disable_device(pdev);
1668 pci_set_power_state(pdev, 3);
1669
1670 return 0;
1671}
1672
1673
1674static int xircom_resume(struct pci_dev *pdev)
1675{
1676 struct net_device *dev = pci_get_drvdata(pdev);
1677 struct xircom_private *tp = netdev_priv(dev);
1678 printk(KERN_INFO "xircom_resume(%s)\n", dev->name);
1679
1680 pci_set_power_state(pdev,0);
1681 pci_enable_device(pdev);
1682 pci_restore_state(pdev);
1683
1684 /* Bring the chip out of sleep mode.
1685 Caution: Snooze mode does not work with some boards! */
1686 if (xircom_tbl[tp->chip_id].flags & HAS_ACPI)
1687 pci_write_config_dword(tp->pdev, PCI_POWERMGMT, 0);
1688
1689 transceiver_voodoo(dev);
1690 if (xircom_tbl[tp->chip_id].flags & HAS_MII)
1691 check_duplex(dev);
1692
1693 if (tp->open)
1694 xircom_up(dev);
1695 return 0;
1696}
1697#endif /* CONFIG_PM */
1698
1699
1700static void __devexit xircom_remove_one(struct pci_dev *pdev)
1701{
1702 struct net_device *dev = pci_get_drvdata(pdev);
1703
1704 printk(KERN_INFO "xircom_remove_one(%s)\n", dev->name);
1705 unregister_netdev(dev);
1706 pci_release_regions(pdev);
1707 free_netdev(dev);
1708 pci_set_drvdata(pdev, NULL);
1709}
1710
1711
1712static struct pci_driver xircom_driver = {
1713 .name = DRV_NAME,
1714 .id_table = xircom_pci_table,
1715 .probe = xircom_init_one,
1716 .remove = __devexit_p(xircom_remove_one),
1717#ifdef CONFIG_PM
1718 .suspend = xircom_suspend,
1719 .resume = xircom_resume
1720#endif /* CONFIG_PM */
1721};
1722
1723
1724static int __init xircom_init(void)
1725{
1726/* when a module, this is printed whether or not devices are found in probe */
1727#ifdef MODULE
1728 printk(version);
1729#endif
1730 return pci_module_init(&xircom_driver);
1731}
1732
1733
1734static void __exit xircom_exit(void)
1735{
1736 pci_unregister_driver(&xircom_driver);
1737}
1738
1739module_init(xircom_init)
1740module_exit(xircom_exit)
1741
1742/*
1743 * Local variables:
1744 * c-indent-level: 4
1745 * c-basic-offset: 4
1746 * tab-width: 4
1747 * End:
1748 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 22:19:15 -0400