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authorJeff Garzik <jeff@garzik.org>2006-05-26 21:39:03 -0400
committerJeff Garzik <jeff@garzik.org>2006-05-26 21:39:03 -0400
commitf3b197ac26ed0e57989856494c495818dcc7f9ac (patch)
tree5451adb0bc6c219d0a794ea32e3c598740c82bdf /drivers/net/tulip/uli526x.c
parent4c0c2fd486b6598e37c77b5d81a08bc2d948aa7b (diff)
[netdrvr] trim trailing whitespace: 8139*.c, epic100, forcedeth, tulip/*
Diffstat (limited to 'drivers/net/tulip/uli526x.c')
-rw-r--r--drivers/net/tulip/uli526x.c80
1 files changed, 40 insertions, 40 deletions
diff --git a/drivers/net/tulip/uli526x.c b/drivers/net/tulip/uli526x.c
index 238e9c72cb3a..8b3a28f53c3d 100644
--- a/drivers/net/tulip/uli526x.c
+++ b/drivers/net/tulip/uli526x.c
@@ -9,7 +9,7 @@
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details. 10 GNU General Public License for more details.
11 11
12 12
13*/ 13*/
14 14
15#define DRV_NAME "uli526x" 15#define DRV_NAME "uli526x"
@@ -185,7 +185,7 @@ struct uli526x_board_info {
185 185
186 /* NIC SROM data */ 186 /* NIC SROM data */
187 unsigned char srom[128]; 187 unsigned char srom[128];
188 u8 init; 188 u8 init;
189}; 189};
190 190
191enum uli526x_offsets { 191enum uli526x_offsets {
@@ -258,7 +258,7 @@ static int __devinit uli526x_init_one (struct pci_dev *pdev,
258 struct uli526x_board_info *db; /* board information structure */ 258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev; 259 struct net_device *dev;
260 int i, err; 260 int i, err;
261 261
262 ULI526X_DBUG(0, "uli526x_init_one()", 0); 262 ULI526X_DBUG(0, "uli526x_init_one()", 0);
263 263
264 if (!printed_version++) 264 if (!printed_version++)
@@ -316,7 +316,7 @@ static int __devinit uli526x_init_one (struct pci_dev *pdev,
316 err = -ENOMEM; 316 err = -ENOMEM;
317 goto err_out_nomem; 317 goto err_out_nomem;
318 } 318 }
319 319
320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; 320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
321 db->first_tx_desc_dma = db->desc_pool_dma_ptr; 321 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
322 db->buf_pool_start = db->buf_pool_ptr; 322 db->buf_pool_start = db->buf_pool_ptr;
@@ -324,14 +324,14 @@ static int __devinit uli526x_init_one (struct pci_dev *pdev,
324 324
325 db->chip_id = ent->driver_data; 325 db->chip_id = ent->driver_data;
326 db->ioaddr = pci_resource_start(pdev, 0); 326 db->ioaddr = pci_resource_start(pdev, 0);
327 327
328 db->pdev = pdev; 328 db->pdev = pdev;
329 db->init = 1; 329 db->init = 1;
330 330
331 dev->base_addr = db->ioaddr; 331 dev->base_addr = db->ioaddr;
332 dev->irq = pdev->irq; 332 dev->irq = pdev->irq;
333 pci_set_drvdata(pdev, dev); 333 pci_set_drvdata(pdev, dev);
334 334
335 /* Register some necessary functions */ 335 /* Register some necessary functions */
336 dev->open = &uli526x_open; 336 dev->open = &uli526x_open;
337 dev->hard_start_xmit = &uli526x_start_xmit; 337 dev->hard_start_xmit = &uli526x_start_xmit;
@@ -341,7 +341,7 @@ static int __devinit uli526x_init_one (struct pci_dev *pdev,
341 dev->ethtool_ops = &netdev_ethtool_ops; 341 dev->ethtool_ops = &netdev_ethtool_ops;
342 spin_lock_init(&db->lock); 342 spin_lock_init(&db->lock);
343 343
344 344
345 /* read 64 word srom data */ 345 /* read 64 word srom data */
346 for (i = 0; i < 64; i++) 346 for (i = 0; i < 64; i++)
347 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); 347 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
@@ -374,7 +374,7 @@ static int __devinit uli526x_init_one (struct pci_dev *pdev,
374 goto err_out_res; 374 goto err_out_res;
375 375
376 printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev)); 376 printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev));
377 377
378 for (i = 0; i < 6; i++) 378 for (i = 0; i < 6; i++)
379 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]); 379 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
380 printk(", irq %d.\n", dev->irq); 380 printk(", irq %d.\n", dev->irq);
@@ -389,7 +389,7 @@ err_out_nomem:
389 if(db->desc_pool_ptr) 389 if(db->desc_pool_ptr)
390 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, 390 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
391 db->desc_pool_ptr, db->desc_pool_dma_ptr); 391 db->desc_pool_ptr, db->desc_pool_dma_ptr);
392 392
393 if(db->buf_pool_ptr != NULL) 393 if(db->buf_pool_ptr != NULL)
394 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, 394 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
395 db->buf_pool_ptr, db->buf_pool_dma_ptr); 395 db->buf_pool_ptr, db->buf_pool_dma_ptr);
@@ -433,7 +433,7 @@ static int uli526x_open(struct net_device *dev)
433{ 433{
434 int ret; 434 int ret;
435 struct uli526x_board_info *db = netdev_priv(dev); 435 struct uli526x_board_info *db = netdev_priv(dev);
436 436
437 ULI526X_DBUG(0, "uli526x_open", 0); 437 ULI526X_DBUG(0, "uli526x_open", 0);
438 438
439 ret = request_irq(dev->irq, &uli526x_interrupt, SA_SHIRQ, dev->name, dev); 439 ret = request_irq(dev->irq, &uli526x_interrupt, SA_SHIRQ, dev->name, dev);
@@ -454,7 +454,7 @@ static int uli526x_open(struct net_device *dev)
454 /* CR6 operation mode decision */ 454 /* CR6 operation mode decision */
455 db->cr6_data |= ULI526X_TXTH_256; 455 db->cr6_data |= ULI526X_TXTH_256;
456 db->cr0_data = CR0_DEFAULT; 456 db->cr0_data = CR0_DEFAULT;
457 457
458 /* Initialize ULI526X board */ 458 /* Initialize ULI526X board */
459 uli526x_init(dev); 459 uli526x_init(dev);
460 460
@@ -604,7 +604,7 @@ static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
604 /* Restore CR7 to enable interrupt */ 604 /* Restore CR7 to enable interrupt */
605 spin_unlock_irqrestore(&db->lock, flags); 605 spin_unlock_irqrestore(&db->lock, flags);
606 outl(db->cr7_data, dev->base_addr + DCR7); 606 outl(db->cr7_data, dev->base_addr + DCR7);
607 607
608 /* free this SKB */ 608 /* free this SKB */
609 dev_kfree_skb(skb); 609 dev_kfree_skb(skb);
610 610
@@ -782,7 +782,7 @@ static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info
782 struct sk_buff *skb; 782 struct sk_buff *skb;
783 int rxlen; 783 int rxlen;
784 u32 rdes0; 784 u32 rdes0;
785 785
786 rxptr = db->rx_ready_ptr; 786 rxptr = db->rx_ready_ptr;
787 787
788 while(db->rx_avail_cnt) { 788 while(db->rx_avail_cnt) {
@@ -821,7 +821,7 @@ static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info
821 if ( !(rdes0 & 0x8000) || 821 if ( !(rdes0 & 0x8000) ||
822 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { 822 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
823 skb = rxptr->rx_skb_ptr; 823 skb = rxptr->rx_skb_ptr;
824 824
825 /* Good packet, send to upper layer */ 825 /* Good packet, send to upper layer */
826 /* Shorst packet used new SKB */ 826 /* Shorst packet used new SKB */
827 if ( (rxlen < RX_COPY_SIZE) && 827 if ( (rxlen < RX_COPY_SIZE) &&
@@ -841,7 +841,7 @@ static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info
841 dev->last_rx = jiffies; 841 dev->last_rx = jiffies;
842 db->stats.rx_packets++; 842 db->stats.rx_packets++;
843 db->stats.rx_bytes += rxlen; 843 db->stats.rx_bytes += rxlen;
844 844
845 } else { 845 } else {
846 /* Reuse SKB buffer when the packet is error */ 846 /* Reuse SKB buffer when the packet is error */
847 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); 847 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
@@ -911,7 +911,7 @@ ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
911 SUPPORTED_100baseT_Full | 911 SUPPORTED_100baseT_Full |
912 SUPPORTED_Autoneg | 912 SUPPORTED_Autoneg |
913 SUPPORTED_MII); 913 SUPPORTED_MII);
914 914
915 ecmd->advertising = (ADVERTISED_10baseT_Half | 915 ecmd->advertising = (ADVERTISED_10baseT_Half |
916 ADVERTISED_10baseT_Full | 916 ADVERTISED_10baseT_Full |
917 ADVERTISED_100baseT_Half | 917 ADVERTISED_100baseT_Half |
@@ -924,13 +924,13 @@ ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
924 ecmd->phy_address = db->phy_addr; 924 ecmd->phy_address = db->phy_addr;
925 925
926 ecmd->transceiver = XCVR_EXTERNAL; 926 ecmd->transceiver = XCVR_EXTERNAL;
927 927
928 ecmd->speed = 10; 928 ecmd->speed = 10;
929 ecmd->duplex = DUPLEX_HALF; 929 ecmd->duplex = DUPLEX_HALF;
930 930
931 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) 931 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
932 { 932 {
933 ecmd->speed = 100; 933 ecmd->speed = 100;
934 } 934 }
935 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) 935 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
936 { 936 {
@@ -939,11 +939,11 @@ ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
939 if(db->link_failed) 939 if(db->link_failed)
940 { 940 {
941 ecmd->speed = -1; 941 ecmd->speed = -1;
942 ecmd->duplex = -1; 942 ecmd->duplex = -1;
943 } 943 }
944 944
945 if (db->media_mode & ULI526X_AUTO) 945 if (db->media_mode & ULI526X_AUTO)
946 { 946 {
947 ecmd->autoneg = AUTONEG_ENABLE; 947 ecmd->autoneg = AUTONEG_ENABLE;
948 } 948 }
949} 949}
@@ -964,15 +964,15 @@ static void netdev_get_drvinfo(struct net_device *dev,
964 964
965static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { 965static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
966 struct uli526x_board_info *np = netdev_priv(dev); 966 struct uli526x_board_info *np = netdev_priv(dev);
967 967
968 ULi_ethtool_gset(np, cmd); 968 ULi_ethtool_gset(np, cmd);
969 969
970 return 0; 970 return 0;
971} 971}
972 972
973static u32 netdev_get_link(struct net_device *dev) { 973static u32 netdev_get_link(struct net_device *dev) {
974 struct uli526x_board_info *np = netdev_priv(dev); 974 struct uli526x_board_info *np = netdev_priv(dev);
975 975
976 if(np->link_failed) 976 if(np->link_failed)
977 return 0; 977 return 0;
978 else 978 else
@@ -1005,11 +1005,11 @@ static void uli526x_timer(unsigned long data)
1005 struct uli526x_board_info *db = netdev_priv(dev); 1005 struct uli526x_board_info *db = netdev_priv(dev);
1006 unsigned long flags; 1006 unsigned long flags;
1007 u8 TmpSpeed=10; 1007 u8 TmpSpeed=10;
1008 1008
1009 //ULI526X_DBUG(0, "uli526x_timer()", 0); 1009 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1010 spin_lock_irqsave(&db->lock, flags); 1010 spin_lock_irqsave(&db->lock, flags);
1011 1011
1012 1012
1013 /* Dynamic reset ULI526X : system error or transmit time-out */ 1013 /* Dynamic reset ULI526X : system error or transmit time-out */
1014 tmp_cr8 = inl(db->ioaddr + DCR8); 1014 tmp_cr8 = inl(db->ioaddr + DCR8);
1015 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { 1015 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
@@ -1021,9 +1021,9 @@ static void uli526x_timer(unsigned long data)
1021 /* TX polling kick monitor */ 1021 /* TX polling kick monitor */
1022 if ( db->tx_packet_cnt && 1022 if ( db->tx_packet_cnt &&
1023 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) { 1023 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1024 outl(0x1, dev->base_addr + DCR1); // Tx polling again 1024 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1025 1025
1026 // TX Timeout 1026 // TX Timeout
1027 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) { 1027 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1028 db->reset_TXtimeout++; 1028 db->reset_TXtimeout++;
1029 db->wait_reset = 1; 1029 db->wait_reset = 1;
@@ -1073,7 +1073,7 @@ static void uli526x_timer(unsigned long data)
1073 uli526x_sense_speed(db) ) 1073 uli526x_sense_speed(db) )
1074 db->link_failed = 1; 1074 db->link_failed = 1;
1075 uli526x_process_mode(db); 1075 uli526x_process_mode(db);
1076 1076
1077 if(db->link_failed==0) 1077 if(db->link_failed==0)
1078 { 1078 {
1079 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) 1079 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
@@ -1404,7 +1404,7 @@ static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1404 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1404 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1405 1405
1406 if ( (phy_mode & 0x24) == 0x24 ) { 1406 if ( (phy_mode & 0x24) == 0x24 ) {
1407 1407
1408 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7); 1408 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1409 if(phy_mode&0x8000) 1409 if(phy_mode&0x8000)
1410 phy_mode = 0x8000; 1410 phy_mode = 0x8000;
@@ -1414,7 +1414,7 @@ static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1414 phy_mode = 0x2000; 1414 phy_mode = 0x2000;
1415 else 1415 else
1416 phy_mode = 0x1000; 1416 phy_mode = 0x1000;
1417 1417
1418 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ 1418 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1419 switch (phy_mode) { 1419 switch (phy_mode) {
1420 case 0x1000: db->op_mode = ULI526X_10MHF; break; 1420 case 0x1000: db->op_mode = ULI526X_10MHF; break;
@@ -1442,7 +1442,7 @@ static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1442static void uli526x_set_phyxcer(struct uli526x_board_info *db) 1442static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1443{ 1443{
1444 u16 phy_reg; 1444 u16 phy_reg;
1445 1445
1446 /* Phyxcer capability setting */ 1446 /* Phyxcer capability setting */
1447 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; 1447 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1448 1448
@@ -1457,7 +1457,7 @@ static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1457 case ULI526X_100MHF: phy_reg |= 0x80; break; 1457 case ULI526X_100MHF: phy_reg |= 0x80; break;
1458 case ULI526X_100MFD: phy_reg |= 0x100; break; 1458 case ULI526X_100MFD: phy_reg |= 0x100; break;
1459 } 1459 }
1460 1460
1461 } 1461 }
1462 1462
1463 /* Write new capability to Phyxcer Reg4 */ 1463 /* Write new capability to Phyxcer Reg4 */
@@ -1556,7 +1556,7 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data
1556 /* Write a word data to PHY controller */ 1556 /* Write a word data to PHY controller */
1557 for ( i = 0x8000; i > 0; i >>= 1) 1557 for ( i = 0x8000; i > 0; i >>= 1)
1558 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); 1558 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1559 1559
1560} 1560}
1561 1561
1562 1562
@@ -1574,7 +1574,7 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1574 return phy_readby_cr10(iobase, phy_addr, offset); 1574 return phy_readby_cr10(iobase, phy_addr, offset);
1575 /* M5261/M5263 Chip */ 1575 /* M5261/M5263 Chip */
1576 ioaddr = iobase + DCR9; 1576 ioaddr = iobase + DCR9;
1577 1577
1578 /* Send 33 synchronization clock to Phy controller */ 1578 /* Send 33 synchronization clock to Phy controller */
1579 for (i = 0; i < 35; i++) 1579 for (i = 0; i < 35; i++)
1580 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 1580 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
@@ -1610,7 +1610,7 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1610static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) 1610static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1611{ 1611{
1612 unsigned long ioaddr,cr10_value; 1612 unsigned long ioaddr,cr10_value;
1613 1613
1614 ioaddr = iobase + DCR10; 1614 ioaddr = iobase + DCR10;
1615 cr10_value = phy_addr; 1615 cr10_value = phy_addr;
1616 cr10_value = (cr10_value<<5) + offset; 1616 cr10_value = (cr10_value<<5) + offset;
@@ -1629,7 +1629,7 @@ static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1629static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data) 1629static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1630{ 1630{
1631 unsigned long ioaddr,cr10_value; 1631 unsigned long ioaddr,cr10_value;
1632 1632
1633 ioaddr = iobase + DCR10; 1633 ioaddr = iobase + DCR10;
1634 cr10_value = phy_addr; 1634 cr10_value = phy_addr;
1635 cr10_value = (cr10_value<<5) + offset; 1635 cr10_value = (cr10_value<<5) + offset;
@@ -1659,7 +1659,7 @@ static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1659static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) 1659static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1660{ 1660{
1661 u16 phy_data; 1661 u16 phy_data;
1662 1662
1663 outl(0x50000 , ioaddr); 1663 outl(0x50000 , ioaddr);
1664 udelay(1); 1664 udelay(1);
1665 phy_data = ( inl(ioaddr) >> 19 ) & 0x1; 1665 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;