Merge branch 'for-2.6.36' into for-2.6.37

Fairly simple conflicts, the most serious ones are the i.MX ones which I
suspect now need another rename.

Conflicts:
	arch/arm/mach-mx2/clock_imx27.c
	arch/arm/mach-mx2/devices.c
	arch/arm/mach-omap2/board-rx51-peripherals.c
	arch/arm/mach-omap2/board-zoom2.c
	sound/soc/fsl/mpc5200_dma.c
	sound/soc/fsl/mpc5200_dma.h
	sound/soc/fsl/mpc8610_hpcd.c
	sound/soc/pxa/spitz.c

1 files changed, 49 insertions, 49 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index ce9c4918c318..4937bd190964 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -53,6 +53,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57765      0x16b4
 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
+#define  TG3PCI_DEVICE_TIGON3_5719       0x1657
 /* 0x04 --> 0x2c unused */
 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
@@ -160,6 +161,7 @@
 #define   ASIC_REV_57780                 0x57780
 #define   ASIC_REV_5717                  0x5717
 #define   ASIC_REV_57765                 0x57785
+#define   ASIC_REV_5719                  0x5719
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -231,6 +233,7 @@
 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
+#define  PCISTATE_ALLOW_APE_PSPACE_WR    0x00040000
 #define TG3PCI_CLOCK_CTRL               0x00000074
 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
@@ -468,6 +471,7 @@
 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
+#define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
 #define MAC_TX_STATUS                   0x00000460
 #define  TX_STATUS_XOFFED                0x00000001
 #define  TX_STATUS_SENT_XOFF             0x00000002
@@ -1071,10 +1075,8 @@
 #define TG3_CPMU_HST_ACC                0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
-/* 0x3620 --> 0x362c unused */
+/* 0x3620 --> 0x3630 unused */
 
-#define TG3_CPMU_STATUS                 0x0000362c
-#define  TG3_CPMU_STATUS_PCIE_FUNC       0x20000000
 #define TG3_CPMU_CLCK_STAT              0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
@@ -1842,6 +1844,10 @@
 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
 /* 0x7d58 --> 0x7e70 unused */
 
+#define TG3_PCIE_PHY_TSTCTL             0x00007e2c
+#define  TG3_PCIE_PHY_TSTCTL_PCIE10      0x00000040
+#define  TG3_PCIE_PHY_TSTCTL_PSCRAM      0x00000020
+
 #define TG3_PCIE_EIDLE_DELAY            0x00007e70
 #define  TG3_PCIE_EIDLE_DELAY_MASK       0x0000001f
 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS    0x0000000c
@@ -2030,31 +2036,9 @@
 
 
 /* Currently this is fixed. */
-#define TG3_PHY_PCIE_ADDR               0x00
 #define TG3_PHY_MII_ADDR                0x01
 
 
-/*** Tigon3 specific PHY PCIE registers. ***/
-
-#define TG3_PCIEPHY_BLOCK_ADDR          0x1f
-#define  TG3_PCIEPHY_XGXS_BLK1          0x0801
-#define  TG3_PCIEPHY_TXB_BLK            0x0861
-#define  TG3_PCIEPHY_BLOCK_SHIFT        4
-
-/* TG3_PCIEPHY_TXB_BLK */
-#define TG3_PCIEPHY_TX0CTRL1            0x15
-#define  TG3_PCIEPHY_TX0CTRL1_TXOCM     0x0003
-#define  TG3_PCIEPHY_TX0CTRL1_RDCTL     0x0008
-#define  TG3_PCIEPHY_TX0CTRL1_TXCMV     0x0030
-#define  TG3_PCIEPHY_TX0CTRL1_TKSEL     0x0040
-#define  TG3_PCIEPHY_TX0CTRL1_NB_EN     0x0400
-
-/* TG3_PCIEPHY_XGXS_BLK1 */
-#define TG3_PCIEPHY_PWRMGMT4            0x1a
-#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
-#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN  0x4000
-
-
 /*** Tigon3 specific PHY MII registers. ***/
 #define  TG3_BMCR_SPEED1000             0x0040
 
@@ -2073,8 +2057,9 @@
 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
 #define  MII_TG3_EXT_STAT_LPASS         0x0100
 
+#define MII_TG3_RXR_COUNTERS            0x14 /* Local/Remote Receiver Counts */
 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
-
+#define MII_TG3_DSP_CONTROL             0x16 /* DSP control register */
 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
 
 #define MII_TG3_DSP_TAP1                0x0001
@@ -2082,6 +2067,7 @@
 #define MII_TG3_DSP_AADJ1CH0            0x001f
 #define MII_TG3_DSP_AADJ1CH3            0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
+#define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
 #define MII_TG3_DSP_EXP8                0x0f08
 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
@@ -2177,6 +2163,8 @@
 /* APE shared memory.  Accessible through BAR1 */
 #define TG3_APE_FW_STATUS               0x400c
 #define  APE_FW_STATUS_READY             0x00000100
+#define TG3_APE_FW_FEATURES             0x4010
+#define  TG3_APE_FW_FEATURE_NCSI         0x00000002
 #define TG3_APE_FW_VERSION              0x4018
 #define  APE_FW_VERSION_MAJMSK           0xff000000
 #define  APE_FW_VERSION_MAJSFT           24
@@ -2191,7 +2179,9 @@
 #define  APE_HOST_SEG_LEN_MAGIC          0x0000001c
 #define TG3_APE_HOST_INIT_COUNT         0x4208
 #define TG3_APE_HOST_DRIVER_ID          0x420c
-#define  APE_HOST_DRIVER_ID_MAGIC        0xf0035100
+#define  APE_HOST_DRIVER_ID_LINUX        0xf0000000
+#define  APE_HOST_DRIVER_ID_MAGIC(maj, min)     \
+        (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
 #define TG3_APE_HOST_BEHAVIOR           0x4210
 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
@@ -2209,6 +2199,11 @@
 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
 
+#define TG3_APE_PER_LOCK_REQ            0x8400
+#define  APE_LOCK_PER_REQ_DRIVER         0x00001000
+#define TG3_APE_PER_LOCK_GRANT          0x8420
+#define  APE_PER_LOCK_GRANT_DRIVER       0x00001000
+
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_GRC                1
 #define TG3_APE_LOCK_MEM                4
@@ -2539,7 +2534,6 @@ struct tg3_link_config {
         /* When we go in and out of low power mode we need
          * to swap with this state.
          */
-        int                             phy_is_low_power;
         u16                             orig_speed;
         u8                              orig_duplex;
         u8                              orig_autoneg;
@@ -2765,8 +2759,8 @@ struct tg3 {
 
 
         /* begin "everything else" cacheline(s) section */
-        struct net_device_stats         net_stats;
-        struct net_device_stats         net_stats_prev;
+        struct rtnl_link_stats64        net_stats;
+        struct rtnl_link_stats64        net_stats_prev;
         struct tg3_ethtool_stats        estats;
         struct tg3_ethtool_stats        estats_prev;
 
@@ -2780,7 +2774,6 @@ struct tg3 {
 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
-#define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
 #define TG3_FLAG_ENABLE_ASF             0x00000020
 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
 #define TG3_FLAG_POLL_SERDES            0x00000080
@@ -2802,7 +2795,6 @@ struct tg3 {
 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
 #define TG3_FLAG_WOL_CAP                0x00400000
 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
-#define TG3_FLAG_10_100_ONLY            0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
 #define TG3_FLAG_CPMU_PRESENT           0x04000000
 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
@@ -2813,22 +2805,15 @@ struct tg3 {
         u32                             tg3_flags2;
 #define TG3_FLG2_RESTART_TIMER          0x00000001
 #define TG3_FLG2_TSO_BUG                0x00000002
-#define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
 #define TG3_FLG2_IS_5788                0x00000008
 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
 #define TG3_FLG2_TSO_CAPABLE            0x00000020
-#define TG3_FLG2_PHY_ADC_BUG            0x00000040
-#define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
-#define TG3_FLG2_PHY_BER_BUG            0x00000100
 #define TG3_FLG2_PCI_EXPRESS            0x00000200
 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
 #define TG3_FLG2_HW_AUTONEG             0x00000800
 #define TG3_FLG2_IS_NIC                 0x00001000
-#define TG3_FLG2_PHY_SERDES             0x00002000
-#define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
 #define TG3_FLG2_FLASH                  0x00008000
 #define TG3_FLG2_HW_TSO_1               0x00010000
-#define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
 #define TG3_FLG2_5705_PLUS              0x00040000
 #define TG3_FLG2_5750_PLUS              0x00080000
 #define TG3_FLG2_HW_TSO_3               0x00100000
@@ -2836,10 +2821,6 @@ struct tg3 {
 #define TG3_FLG2_USING_MSIX             0x00400000
 #define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
                                         TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_MII_SERDES             0x00800000
-#define TG3_FLG2_ANY_SERDES             (TG3_FLG2_PHY_SERDES |  \
-                                        TG3_FLG2_MII_SERDES)
-#define TG3_FLG2_PARALLEL_DETECT        0x01000000
 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
 #define TG3_FLG2_5780_CLASS             0x04000000
 #define TG3_FLG2_HW_TSO_2               0x08000000
@@ -2847,9 +2828,7 @@ struct tg3 {
                                          TG3_FLG2_HW_TSO_2 | \
                                          TG3_FLG2_HW_TSO_3)
 #define TG3_FLG2_1SHOT_MSI              0x10000000
-#define TG3_FLG2_PHY_JITTER_BUG         0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
-#define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
         u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 #define TG3_FLG3_ENABLE_APE             0x00000002
@@ -2857,15 +2836,12 @@ struct tg3 {
 #define TG3_FLG3_5701_DMA_BUG           0x00000008
 #define TG3_FLG3_USE_PHYLIB             0x00000010
 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
-#define TG3_FLG3_PHY_CONNECTED          0x00000080
 #define TG3_FLG3_RGMII_INBAND_DISABLE   0x00000100
 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
 #define TG3_FLG3_CLKREQ_BUG             0x00000800
-#define TG3_FLG3_PHY_ENABLE_APD         0x00001000
 #define TG3_FLG3_5755_PLUS              0x00002000
 #define TG3_FLG3_NO_NVRAM               0x00004000
-#define TG3_FLG3_PHY_IS_FET             0x00010000
 #define TG3_FLG3_ENABLE_RSS             0x00020000
 #define TG3_FLG3_ENABLE_TSS             0x00040000
 #define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
@@ -2873,6 +2849,7 @@ struct tg3 {
 #define TG3_FLG3_SHORT_DMA_BUG          0x00200000
 #define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
 #define TG3_FLG3_L1PLLPD_EN             0x00800000
+#define TG3_FLG3_5717_PLUS              0x01000000
 
         struct timer_list               timer;
         u16                             timer_counter;
@@ -2942,6 +2919,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCM5718C             0x5c0d8a00
 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
+#define TG3_PHY_ID_BCM5719C             0x5c0d8a20
 #define TG3_PHY_ID_BCM5906              0xdc00ac40
 #define TG3_PHY_ID_BCM8002              0x60010140
 #define TG3_PHY_ID_INVALID              0xffffffff
@@ -2965,7 +2943,29 @@ struct tg3 {
          (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
-         (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
+         (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
+         (X) == TG3_PHY_ID_BCM8002)
+
+        u32                             phy_flags;
+#define TG3_PHYFLG_IS_LOW_POWER         0x00000001
+#define TG3_PHYFLG_IS_CONNECTED         0x00000002
+#define TG3_PHYFLG_USE_MI_INTERRUPT     0x00000004
+#define TG3_PHYFLG_PHY_SERDES           0x00000010
+#define TG3_PHYFLG_MII_SERDES           0x00000020
+#define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
+                                        TG3_PHYFLG_MII_SERDES)
+#define TG3_PHYFLG_IS_FET               0x00000040
+#define TG3_PHYFLG_10_100_ONLY          0x00000080
+#define TG3_PHYFLG_ENABLE_APD           0x00000100
+#define TG3_PHYFLG_CAPACITIVE_COUPLING  0x00000200
+#define TG3_PHYFLG_NO_ETH_WIRE_SPEED    0x00000400
+#define TG3_PHYFLG_JITTER_BUG           0x00000800
+#define TG3_PHYFLG_ADJUST_TRIM          0x00001000
+#define TG3_PHYFLG_ADC_BUG              0x00002000
+#define TG3_PHYFLG_5704_A0_BUG          0x00004000
+#define TG3_PHYFLG_BER_BUG              0x00008000
+#define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
+#define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
 
         u32                             led_ctrl;
         u32                             phy_otp;