tg3: Migrate tg3_flags to phy_flags

This patch moves most of the phy related flag definitions over to the
phyflags member and changes the code accordingly.

Reviewed-by: Benjamin Li <benli@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 18 insertions, 18 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5d684d2b4034..4937bd190964 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2774,7 +2774,6 @@ struct tg3 {
 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
-#define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
 #define TG3_FLAG_ENABLE_ASF             0x00000020
 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
 #define TG3_FLAG_POLL_SERDES            0x00000080
@@ -2796,7 +2795,6 @@ struct tg3 {
 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
 #define TG3_FLAG_WOL_CAP                0x00400000
 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
-#define TG3_FLAG_10_100_ONLY            0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
 #define TG3_FLAG_CPMU_PRESENT           0x04000000
 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
@@ -2807,22 +2805,15 @@ struct tg3 {
         u32                             tg3_flags2;
 #define TG3_FLG2_RESTART_TIMER          0x00000001
 #define TG3_FLG2_TSO_BUG                0x00000002
-#define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
 #define TG3_FLG2_IS_5788                0x00000008
 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
 #define TG3_FLG2_TSO_CAPABLE            0x00000020
-#define TG3_FLG2_PHY_ADC_BUG            0x00000040
-#define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
-#define TG3_FLG2_PHY_BER_BUG            0x00000100
 #define TG3_FLG2_PCI_EXPRESS            0x00000200
 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
 #define TG3_FLG2_HW_AUTONEG             0x00000800
 #define TG3_FLG2_IS_NIC                 0x00001000
-#define TG3_FLG2_PHY_SERDES             0x00002000
-#define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
 #define TG3_FLG2_FLASH                  0x00008000
 #define TG3_FLG2_HW_TSO_1               0x00010000
-#define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
 #define TG3_FLG2_5705_PLUS              0x00040000
 #define TG3_FLG2_5750_PLUS              0x00080000
 #define TG3_FLG2_HW_TSO_3               0x00100000
@@ -2830,10 +2821,6 @@ struct tg3 {
 #define TG3_FLG2_USING_MSIX             0x00400000
 #define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
                                         TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_MII_SERDES             0x00800000
-#define TG3_FLG2_ANY_SERDES             (TG3_FLG2_PHY_SERDES |  \
-                                        TG3_FLG2_MII_SERDES)
-#define TG3_FLG2_PARALLEL_DETECT        0x01000000
 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
 #define TG3_FLG2_5780_CLASS             0x04000000
 #define TG3_FLG2_HW_TSO_2               0x08000000
@@ -2841,9 +2828,7 @@ struct tg3 {
                                          TG3_FLG2_HW_TSO_2 | \
                                          TG3_FLG2_HW_TSO_3)
 #define TG3_FLG2_1SHOT_MSI              0x10000000
-#define TG3_FLG2_PHY_JITTER_BUG         0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
-#define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
         u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 #define TG3_FLG3_ENABLE_APE             0x00000002
@@ -2851,15 +2836,12 @@ struct tg3 {
 #define TG3_FLG3_5701_DMA_BUG           0x00000008
 #define TG3_FLG3_USE_PHYLIB             0x00000010
 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
-#define TG3_FLG3_PHY_CONNECTED          0x00000080
 #define TG3_FLG3_RGMII_INBAND_DISABLE   0x00000100
 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
 #define TG3_FLG3_CLKREQ_BUG             0x00000800
-#define TG3_FLG3_PHY_ENABLE_APD         0x00001000
 #define TG3_FLG3_5755_PLUS              0x00002000
 #define TG3_FLG3_NO_NVRAM               0x00004000
-#define TG3_FLG3_PHY_IS_FET             0x00010000
 #define TG3_FLG3_ENABLE_RSS             0x00020000
 #define TG3_FLG3_ENABLE_TSS             0x00040000
 #define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
@@ -2966,6 +2948,24 @@ struct tg3 {
 
         u32                             phy_flags;
 #define TG3_PHYFLG_IS_LOW_POWER         0x00000001
+#define TG3_PHYFLG_IS_CONNECTED         0x00000002
+#define TG3_PHYFLG_USE_MI_INTERRUPT     0x00000004
+#define TG3_PHYFLG_PHY_SERDES           0x00000010
+#define TG3_PHYFLG_MII_SERDES           0x00000020
+#define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
+                                        TG3_PHYFLG_MII_SERDES)
+#define TG3_PHYFLG_IS_FET               0x00000040
+#define TG3_PHYFLG_10_100_ONLY          0x00000080
+#define TG3_PHYFLG_ENABLE_APD           0x00000100
+#define TG3_PHYFLG_CAPACITIVE_COUPLING  0x00000200
+#define TG3_PHYFLG_NO_ETH_WIRE_SPEED    0x00000400
+#define TG3_PHYFLG_JITTER_BUG           0x00000800
+#define TG3_PHYFLG_ADJUST_TRIM          0x00001000
+#define TG3_PHYFLG_ADC_BUG              0x00002000
+#define TG3_PHYFLG_5704_A0_BUG          0x00004000
+#define TG3_PHYFLG_BER_BUG              0x00008000
+#define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
+#define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
 
         u32                             led_ctrl;
         u32                             phy_otp;