diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-28 09:58:24 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-29 18:42:41 -0400 |
commit | 8f666b07ac53eeedd6c035adf6d4299f9ed0df2d (patch) | |
tree | a7c1b24da09573873097c33a25d25af2ea9206bc /drivers/net/tg3.h | |
parent | fdb72b38c94c0ead1f78ecc8db64b832feda22c3 (diff) |
tg3: Move the JUMBO_CAPABLE and SUPPORT_MSI flags
This patch moves where the jumbo capable and msi support flags are
located. This is prep work for the addition of msix support flags.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 1c9495df67ce..5efae2c51388 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2601,6 +2601,7 @@ struct tg3 { | |||
2601 | #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 | 2601 | #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 |
2602 | #define TG3_FLAG_NVRAM 0x00002000 | 2602 | #define TG3_FLAG_NVRAM 0x00002000 |
2603 | #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 | 2603 | #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 |
2604 | #define TG3_FLAG_SUPPORT_MSI 0x00008000 | ||
2604 | #define TG3_FLAG_PCIX_MODE 0x00020000 | 2605 | #define TG3_FLAG_PCIX_MODE 0x00020000 |
2605 | #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 | 2606 | #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 |
2606 | #define TG3_FLAG_PCI_32BIT 0x00080000 | 2607 | #define TG3_FLAG_PCI_32BIT 0x00080000 |
@@ -2613,7 +2614,7 @@ struct tg3 { | |||
2613 | #define TG3_FLAG_CPMU_PRESENT 0x04000000 | 2614 | #define TG3_FLAG_CPMU_PRESENT 0x04000000 |
2614 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 | 2615 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 |
2615 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 | 2616 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 |
2616 | #define TG3_FLAG_SUPPORT_MSI 0x20000000 | 2617 | #define TG3_FLAG_JUMBO_CAPABLE 0x20000000 |
2617 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 | 2618 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 |
2618 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 | 2619 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 |
2619 | u32 tg3_flags2; | 2620 | u32 tg3_flags2; |
@@ -2639,7 +2640,6 @@ struct tg3 { | |||
2639 | #define TG3_FLG2_5750_PLUS 0x00080000 | 2640 | #define TG3_FLG2_5750_PLUS 0x00080000 |
2640 | #define TG3_FLG2_PROTECTED_NVRAM 0x00100000 | 2641 | #define TG3_FLG2_PROTECTED_NVRAM 0x00100000 |
2641 | #define TG3_FLG2_USING_MSI 0x00200000 | 2642 | #define TG3_FLG2_USING_MSI 0x00200000 |
2642 | #define TG3_FLG2_JUMBO_CAPABLE 0x00400000 | ||
2643 | #define TG3_FLG2_MII_SERDES 0x00800000 | 2643 | #define TG3_FLG2_MII_SERDES 0x00800000 |
2644 | #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \ | 2644 | #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \ |
2645 | TG3_FLG2_MII_SERDES) | 2645 | TG3_FLG2_MII_SERDES) |