diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2010-12-06 03:28:53 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-12-06 14:03:48 -0500 |
commit | a386b9011a4687470e6168e2f2a08c468f25f72f (patch) | |
tree | 4f4c8d2dd7fe42d85e950302a71290d3db1fcc61 /drivers/net/tg3.h | |
parent | a6b68dab169e2a51e59f43504f1279cbc2afcde8 (diff) |
tg3: Relax EEE thresholds
The hardware defaults to fairly aggressive EEE thresholds. While there
appear to be no ill effects, this patch relaxes them, just as a
precaution.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 6e72c6bd2675..d62c8d937c82 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1094,13 +1094,19 @@ | |||
1094 | /* 0x3664 --> 0x36b0 unused */ | 1094 | /* 0x3664 --> 0x36b0 unused */ |
1095 | 1095 | ||
1096 | #define TG3_CPMU_EEE_MODE 0x000036b0 | 1096 | #define TG3_CPMU_EEE_MODE 0x000036b0 |
1097 | #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 | 1097 | #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 |
1098 | #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 | 1098 | #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 |
1099 | #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 | 1099 | #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 |
1100 | #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 | 1100 | #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 |
1101 | #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 | 1101 | #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 |
1102 | /* 0x36b4 --> 0x36b8 unused */ | 1102 | #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 |
1103 | 1103 | #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 | |
1104 | #define TG3_CPMU_EEE_DBTMR1 0x000036b4 | ||
1105 | #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 | ||
1106 | #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000070ff | ||
1107 | #define TG3_CPMU_EEE_DBTMR2 0x000036b8 | ||
1108 | #define TG3_CPMU_DBTMR1_APE_TX_2047US 0x07ff0000 | ||
1109 | #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000070ff | ||
1104 | #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc | 1110 | #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc |
1105 | #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 | 1111 | #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 |
1106 | #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 | 1112 | #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 |