diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2011-05-19 08:12:46 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-05-19 18:00:00 -0400 |
commit | 1ff30a59f6d0c754e99442501a5145bdbbcfa6ea (patch) | |
tree | 28c1fb69dea98daba406fc07c6df0edd04cbbba5 /drivers/net/tg3.h | |
parent | 432aa7ed75b3adaef6040d2cbe745fdd1c899415 (diff) |
tg3: Fix 57765 B0 data corruption
The PCIe max FTS limit is too aggressive on these chips. This patch
loosens the limit a little to eliminate data corruption issues.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index ce010cd33895..330959b9cfbc 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -180,6 +180,7 @@ | |||
180 | #define CHIPREV_5750_BX 0x41 | 180 | #define CHIPREV_5750_BX 0x41 |
181 | #define CHIPREV_5784_AX 0x57840 | 181 | #define CHIPREV_5784_AX 0x57840 |
182 | #define CHIPREV_5761_AX 0x57610 | 182 | #define CHIPREV_5761_AX 0x57610 |
183 | #define CHIPREV_57765_AX 0x577650 | ||
183 | #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) | 184 | #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) |
184 | #define METAL_REV_A0 0x00 | 185 | #define METAL_REV_A0 0x00 |
185 | #define METAL_REV_A1 0x01 | 186 | #define METAL_REV_A1 0x01 |
@@ -1951,6 +1952,9 @@ | |||
1951 | 1952 | ||
1952 | /* Alternate PCIE definitions */ | 1953 | /* Alternate PCIE definitions */ |
1953 | #define TG3_PCIE_TLDLPL_PORT 0x00007c00 | 1954 | #define TG3_PCIE_TLDLPL_PORT 0x00007c00 |
1955 | #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c | ||
1956 | #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff | ||
1957 | #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c | ||
1954 | #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 | 1958 | #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 |
1955 | #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 | 1959 | #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 |
1956 | #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 | 1960 | #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 |