[TG3]: Add basic 5906 support.

Add support for the new 5709 device.  This is a new 10/100 Mbps chip.
The mailbox access and firmware interface are quite different from
all other tg3 chips.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 24 insertions, 4 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index feed13dc8719..2f5e00c96016 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -24,6 +24,8 @@
 
 #define RX_COPY_THRESHOLD               256
 
+#define TG3_RX_INTERNAL_RING_SZ_5906    32
+
 #define RX_STD_MAX_SIZE                 1536
 #define RX_STD_MAX_SIZE_5705            512
 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
@@ -129,6 +131,7 @@
 #define  CHIPREV_ID_5752_A0_HW           0x5000
 #define  CHIPREV_ID_5752_A0              0x6000
 #define  CHIPREV_ID_5752_A1              0x6001
+#define  CHIPREV_ID_5906_A1              0xc001
 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                  0x07
 #define   ASIC_REV_5701                  0x00
@@ -141,6 +144,7 @@
 #define   ASIC_REV_5714                  0x09
 #define   ASIC_REV_5755                  0x0a
 #define   ASIC_REV_5787                  0x0b
+#define   ASIC_REV_5906                  0x0c
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -646,7 +650,8 @@
 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
 #define SNDDATAI_STATSENAB              0x00000c0c
 #define SNDDATAI_STATSINCMASK           0x00000c10
-/* 0xc14 --> 0xc80 unused */
+#define ISO_PKT_TX                      0x00000c20
+/* 0xc24 --> 0xc80 unused */
 #define SNDDATAI_COS_CNT_0              0x00000c80
 #define SNDDATAI_COS_CNT_1              0x00000c84
 #define SNDDATAI_COS_CNT_2              0x00000c88
@@ -997,11 +1002,13 @@
 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
+#define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
 #define BUFMGR_MB_HIGH_WATER            0x00004418
 #define  DEFAULT_MB_HIGH_WATER           0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
+#define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
@@ -1138,7 +1145,12 @@
 #define TX_CPU_STATE                    0x00005404
 #define TX_CPU_PGMCTR                   0x0000541c
 
+#define VCPU_STATUS                     0x00005100
+#define  VCPU_STATUS_INIT_DONE           0x04000000
+#define  VCPU_STATUS_DRV_RESET           0x08000000
+
 /* Mailboxes */
+#define GRCMBOX_BASE                    0x00005600
 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
@@ -1398,7 +1410,10 @@
 #define GRC_EEPROM_CTRL                 0x00006840
 #define GRC_MDI_CTRL                    0x00006844
 #define GRC_SEEPROM_DELAY               0x00006848
-/* 0x684c --> 0x6c00 unused */
+/* 0x684c --> 0x6890 unused */
+#define GRC_VCPU_EXT_CTRL               0x00006890
+#define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
+#define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
 
 /* 0x6c00 --> 0x7000 unused */
@@ -1485,7 +1500,11 @@
 #define NVRAM_WRITE1                    0x00007028
 /* 0x702c --> 0x7400 unused */
 
-/* 0x7400 --> 0x8000 unused */
+/* 0x7400 --> 0x7c00 unused */
+#define PCIE_TRANSACTION_CFG            0x00007c04
+#define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
+#define PCIE_TRANS_CFG_LOM               0x00000020
+
 
 #define TG3_EEPROM_MAGIC                0x669955aa
 
@@ -2283,6 +2302,7 @@ struct tg3 {
 #define PHY_ID_BCM5755                  0xbc050cc0
 #define PHY_ID_BCM5787                  0xbc050ce0
 #define PHY_ID_BCM5756                  0xbc050ed0
+#define PHY_ID_BCM5906                  0xdc00ac40
 #define PHY_ID_BCM8002                  0x60010140
 #define PHY_ID_INVALID                  0xffffffff
 #define PHY_ID_REV_MASK                 0x0000000f
@@ -2310,7 +2330,7 @@ struct tg3 {
          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
-         (X) == PHY_ID_BCM8002)
+         (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
 
         struct tg3_hw_stats             *hw_stats;
         dma_addr_t                      stats_mapping;