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authorMatt Carlson <mcarlson@broadcom.com>2009-08-25 06:09:36 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-26 18:47:58 -0400
commit535ef6e1124d445efbcc13b7126561dc544b0b64 (patch)
treea961c86394eca3c40f660743ac79585dc2c0613c /drivers/net/tg3.h
parentbb85fbb6a98d8edab81599913559c7ff0a963984 (diff)
tg3: Create MII_TG3_FET namespace
Broadcom's phys come in two distinctly different register layouts. For the lack of an official term to distinguish between the two formats, we can loosely categorize them by their fast ethernet or gigabit ethernet transceiver description. This patch creates the (driver-internal) Fast Ethernet Transceiver (FET) namespace and converts the 5906 EPHY definitions over. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h21
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d096e10ad634..b8339c9ae0e3 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1909,7 +1909,6 @@
1909 1909
1910#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 1910#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1911 1911
1912#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
1913#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 1912#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1914 1913
1915#define MII_TG3_DSP_TAP1 0x0001 1914#define MII_TG3_DSP_TAP1 0x0001
@@ -1976,17 +1975,23 @@
1976#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 1975#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
1977#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 1976#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
1978 1977
1979
1980#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1981#define MII_TG3_EPHY_SHADOW_EN 0x80
1982
1983#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
1984#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
1985
1986#define MII_TG3_TEST1 0x1e 1978#define MII_TG3_TEST1 0x1e
1987#define MII_TG3_TEST1_TRIM_EN 0x0010 1979#define MII_TG3_TEST1_TRIM_EN 0x0010
1988#define MII_TG3_TEST1_CRC_EN 0x8000 1980#define MII_TG3_TEST1_CRC_EN 0x8000
1989 1981
1982
1983/* Fast Ethernet Tranceiver definitions */
1984#define MII_TG3_FET_PTEST 0x17
1985#define MII_TG3_FET_TEST 0x1f
1986#define MII_TG3_FET_SHADOW_EN 0x0080
1987
1988#define MII_TG3_FET_SHDW_MISCCTRL 0x10
1989#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
1990
1991#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
1992#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
1993
1994
1990/* APE registers. Accessible through BAR1 */ 1995/* APE registers. Accessible through BAR1 */
1991#define TG3_APE_EVENT 0x000c 1996#define TG3_APE_EVENT 0x000c
1992#define APE_EVENT_1 0x00000001 1997#define APE_EVENT_1 0x00000001