diff options
author | Michael Chan <mchan@broadcom.com> | 2006-06-29 23:15:54 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2006-06-30 17:11:57 -0400 |
commit | 52c0fd834ea0e7c6ef8616ce0a1f85bac4233ed7 (patch) | |
tree | 92897bedf97906699f654fd94985fbada0497daa /drivers/net/tg3.h | |
parent | 1661394e78b3b2cc868cd0e89c1066974302aaca (diff) |
[TG3]: Add TSO workaround using GSO
Use GSO to workaround a rare TSO bug on some chips. This hardware
bug may be triggered when the TSO header size is greater than 80
bytes. When this condition is detected in a TSO packet, the driver
will use GSO to segment the packet to workaround the hardware bug.
Thanks to Juergen Kreileder <jk@blackdown.de> for reporting the
problem and collecting traces to help debug the problem.
And thanks to Herbert Xu <herbert@gondor.apana.org.au> for providing
the GSO mechanism that happens to be the perfect workaround for this
problem.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 97a860433b50..ba2c98711c88 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -125,6 +125,7 @@ | |||
125 | #define CHIPREV_ID_5750_A0 0x4000 | 125 | #define CHIPREV_ID_5750_A0 0x4000 |
126 | #define CHIPREV_ID_5750_A1 0x4001 | 126 | #define CHIPREV_ID_5750_A1 0x4001 |
127 | #define CHIPREV_ID_5750_A3 0x4003 | 127 | #define CHIPREV_ID_5750_A3 0x4003 |
128 | #define CHIPREV_ID_5750_C2 0x4202 | ||
128 | #define CHIPREV_ID_5752_A0_HW 0x5000 | 129 | #define CHIPREV_ID_5752_A0_HW 0x5000 |
129 | #define CHIPREV_ID_5752_A0 0x6000 | 130 | #define CHIPREV_ID_5752_A0 0x6000 |
130 | #define CHIPREV_ID_5752_A1 0x6001 | 131 | #define CHIPREV_ID_5752_A1 0x6001 |
@@ -2193,7 +2194,7 @@ struct tg3 { | |||
2193 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 | 2194 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 |
2194 | u32 tg3_flags2; | 2195 | u32 tg3_flags2; |
2195 | #define TG3_FLG2_RESTART_TIMER 0x00000001 | 2196 | #define TG3_FLG2_RESTART_TIMER 0x00000001 |
2196 | /* 0x00000002 available */ | 2197 | #define TG3_FLG2_HW_TSO_1_BUG 0x00000002 |
2197 | #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 | 2198 | #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 |
2198 | #define TG3_FLG2_IS_5788 0x00000008 | 2199 | #define TG3_FLG2_IS_5788 0x00000008 |
2199 | #define TG3_FLG2_MAX_RXPEND_64 0x00000010 | 2200 | #define TG3_FLG2_MAX_RXPEND_64 0x00000010 |