aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.h
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2007-11-13 00:08:03 -0500
committerDavid S. Miller <davem@davemloft.net>2007-11-13 00:08:03 -0500
commitce057f01956bfcb3cb8588091000ae546be78e00 (patch)
tree6438c33bcdde387ab191912e970b2fb65696b0a0 /drivers/net/tg3.h
parentc88864df27590b80fca4a991e0c257d1757cec41 (diff)
[TG3]: 5784 / 5764 GPHY power down fix
5784 and 5764 devices fail to link / pass traffic after one load / unload cycle. This happens because of a hardware bug in the new CPMU. During normal operation, the MAC depends on the PHY clock being available. When the PHY is powered down, the clock the MAC depends on is disabled. The fix is to switch the MAC clock to an alternate source before powering down the PHY, and to restore the MAC clock to the PHY source upon device resume. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 1d5b2a3dd29d..4659697beb4b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -109,6 +109,7 @@
109#define CHIPREV_ID_5714_A2 0x9002 109#define CHIPREV_ID_5714_A2 0x9002
110#define CHIPREV_ID_5906_A1 0xc001 110#define CHIPREV_ID_5906_A1 0xc001
111#define CHIPREV_ID_5784_A0 0x5784000 111#define CHIPREV_ID_5784_A0 0x5784000
112#define CHIPREV_ID_5761_A0 0x5761000
112#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 113#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
113#define ASIC_REV_5700 0x07 114#define ASIC_REV_5700 0x07
114#define ASIC_REV_5701 0x00 115#define ASIC_REV_5701 0x00
@@ -856,7 +857,13 @@
856#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 857#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
857#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 858#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
858#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 859#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
859/* 0x3604 --> 0x365c unused */ 860/* 0x3604 --> 0x360c unused */
861
862#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
863#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
864#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
865#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
866/* 0x3610 --> 0x365c unused */
860 867
861#define TG3_CPMU_MUTEX_REQ 0x0000365c 868#define TG3_CPMU_MUTEX_REQ 0x0000365c
862#define CPMU_MUTEX_REQ_DRIVER 0x00001000 869#define CPMU_MUTEX_REQ_DRIVER 0x00001000