aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.h
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2008-11-21 20:22:19 -0500
committerDavid S. Miller <davem@davemloft.net>2008-11-21 20:22:19 -0500
commit321d32a052d6b5f71111ebad4fbebea5577f8974 (patch)
tree76dae255ad9ae62ea8e3bf1e147a3bf0b1d0bfac /drivers/net/tg3.h
parent22435849a6dcde2ce10d1870aba461a54e347fe3 (diff)
tg3: Add 57780 support
This patch adds support for the 57780 ASIC revision. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 42f60ef4fa39..61556764a505 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -40,6 +40,10 @@
40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
41#define TG3PCI_DEVICE_TIGON3_5761S 0x1688 41#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
42#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 42#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
43#define TG3PCI_DEVICE_TIGON3_57780 0x1692
44#define TG3PCI_DEVICE_TIGON3_57760 0x1690
45#define TG3PCI_DEVICE_TIGON3_57790 0x1694
46#define TG3PCI_DEVICE_TIGON3_57720 0x168c
43#define TG3PCI_COMMAND 0x00000004 47#define TG3PCI_COMMAND 0x00000004
44#define TG3PCI_STATUS 0x00000006 48#define TG3PCI_STATUS 0x00000006
45#define TG3PCI_CCREVID 0x00000008 49#define TG3PCI_CCREVID 0x00000008
@@ -131,6 +135,7 @@
131#define ASIC_REV_5784 0x5784 135#define ASIC_REV_5784 0x5784
132#define ASIC_REV_5761 0x5761 136#define ASIC_REV_5761 0x5761
133#define ASIC_REV_5785 0x5785 137#define ASIC_REV_5785 0x5785
138#define ASIC_REV_57780 0x57780
134#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 139#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
135#define CHIPREV_5700_AX 0x70 140#define CHIPREV_5700_AX 0x70
136#define CHIPREV_5700_BX 0x71 141#define CHIPREV_5700_BX 0x71
@@ -1648,6 +1653,12 @@
1648#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1653#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1649#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1654#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1650#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1655#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1656#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1657#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1658#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1659#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1660#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1661#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1651#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1662#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1652#define FLASH_5752PAGE_SIZE_256 0x00000000 1663#define FLASH_5752PAGE_SIZE_256 0x00000000
1653#define FLASH_5752PAGE_SIZE_512 0x10000000 1664#define FLASH_5752PAGE_SIZE_512 0x10000000
@@ -1655,6 +1666,7 @@
1655#define FLASH_5752PAGE_SIZE_2K 0x30000000 1666#define FLASH_5752PAGE_SIZE_2K 0x30000000
1656#define FLASH_5752PAGE_SIZE_4K 0x40000000 1667#define FLASH_5752PAGE_SIZE_4K 0x40000000
1657#define FLASH_5752PAGE_SIZE_264 0x50000000 1668#define FLASH_5752PAGE_SIZE_264 0x50000000
1669#define FLASH_5752PAGE_SIZE_528 0x60000000
1658#define NVRAM_CFG2 0x00007018 1670#define NVRAM_CFG2 0x00007018
1659#define NVRAM_CFG3 0x0000701c 1671#define NVRAM_CFG3 0x0000701c
1660#define NVRAM_SWARB 0x00007020 1672#define NVRAM_SWARB 0x00007020
@@ -2632,6 +2644,7 @@ struct tg3 {
2632#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 2644#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
2633#define TG3_FLG3_CLKREQ_BUG 0x00000800 2645#define TG3_FLG3_CLKREQ_BUG 0x00000800
2634#define TG3_FLG3_PHY_ENABLE_APD 0x00001000 2646#define TG3_FLG3_PHY_ENABLE_APD 0x00001000
2647#define TG3_FLG3_5755_PLUS 0x00002000
2635 2648
2636 struct timer_list timer; 2649 struct timer_list timer;
2637 u16 timer_counter; 2650 u16 timer_counter;
@@ -2709,6 +2722,7 @@ struct tg3 {
2709#define TG3_PHY_ID_BCMAC131 0x143bc70 2722#define TG3_PHY_ID_BCMAC131 0x143bc70
2710#define TG3_PHY_ID_RTL8211C 0x001cc910 2723#define TG3_PHY_ID_RTL8211C 0x001cc910
2711#define TG3_PHY_ID_RTL8201E 0x00008200 2724#define TG3_PHY_ID_RTL8201E 0x00008200
2725#define TG3_PHY_ID_BCM57780 0x03625d90
2712#define TG3_PHY_OUI_MASK 0xfffffc00 2726#define TG3_PHY_OUI_MASK 0xfffffc00
2713#define TG3_PHY_OUI_1 0x00206000 2727#define TG3_PHY_OUI_1 0x00206000
2714#define TG3_PHY_OUI_2 0x0143bc00 2728#define TG3_PHY_OUI_2 0x0143bc00