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authorMichael Chan <mchan@broadcom.com>2006-05-26 20:48:07 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-18 00:26:26 -0400
commitdf3e6548186f0baa727cd6d3a492891854bd31f2 (patch)
tree525617b51451b730b0723d57258c6a8bf7f53d09 /drivers/net/tg3.h
parent30b6c28d2aca4669f2e609ad5d77ea2a6cf0dd3a (diff)
[TG3]: Add recovery logic when MMIOs are re-ordered
Add recovery logic when we suspect that the system is re-ordering MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx completions and hit BUG_ON() in the tx completion path. tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs that must be strictly ordered (such as the send mailbox). Determining when to enable the flush is currently a manual process of adding known chipsets to a list. The new code replaces the BUG_ON() in the tx completion path with the call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER flag and reset the chip later in the workqueue to recover and start flushing MMIOs to the mailbox. A message to report the problem will be printed. We will then decide whether or not to add the host bridge to the list of chipsets that do re-ordering. We may add some additional code later to print the host bridge's ID so that the user can report it more easily. The assumption that re-ordering can only happen on x86 systems is also removed. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h5
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index ff0faab94bd5..35669e18065c 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2155,11 +2155,7 @@ struct tg3 {
2155#define TG3_FLAG_ENABLE_ASF 0x00000020 2155#define TG3_FLAG_ENABLE_ASF 0x00000020
2156#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 2156#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
2157#define TG3_FLAG_POLL_SERDES 0x00000080 2157#define TG3_FLAG_POLL_SERDES 0x00000080
2158#if defined(CONFIG_X86)
2159#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 2158#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2160#else
2161#define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
2162#endif
2163#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 2159#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2164#define TG3_FLAG_WOL_SPEED_100MB 0x00000400 2160#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2165#define TG3_FLAG_WOL_ENABLE 0x00000800 2161#define TG3_FLAG_WOL_ENABLE 0x00000800
@@ -2172,6 +2168,7 @@ struct tg3 {
2172#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2168#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2173#define TG3_FLAG_PCI_32BIT 0x00080000 2169#define TG3_FLAG_PCI_32BIT 0x00080000
2174#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 2170#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2171#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2175#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2172#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2176#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 2173#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2177#define TG3_FLAG_10_100_ONLY 0x01000000 2174#define TG3_FLAG_10_100_ONLY 0x01000000