diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2007-07-11 22:48:29 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2007-07-11 22:48:29 -0400 |
commit | 9ef8ca99749784644602535691f8cf201ee2a225 (patch) | |
tree | 7836b055d04f88203b8cf563272696d6fe972e95 /drivers/net/tg3.h | |
parent | e8f3f6cad7e423253090887bc4afe7bc844162da (diff) |
[TG3]: Enable auto MDI.
This patch adds automatic MDI crossover support when autonegotiation is
turned off. Automatic MDI crossover allows link to be established
without the use of a crossover cable.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index bd9f4f428e5b..e1b9381d3b41 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1642,6 +1642,11 @@ | |||
1642 | 1642 | ||
1643 | #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ | 1643 | #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ |
1644 | 1644 | ||
1645 | #define MII_TG3_AUXCTL_MISC_WREN 0x8000 | ||
1646 | #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 | ||
1647 | #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000 | ||
1648 | #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 | ||
1649 | |||
1645 | #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ | 1650 | #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ |
1646 | #define MII_TG3_AUX_STAT_LPASS 0x0004 | 1651 | #define MII_TG3_AUX_STAT_LPASS 0x0004 |
1647 | #define MII_TG3_AUX_STAT_SPDMASK 0x0700 | 1652 | #define MII_TG3_AUX_STAT_SPDMASK 0x0700 |
@@ -1667,6 +1672,9 @@ | |||
1667 | #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ | 1672 | #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ |
1668 | #define MII_TG3_EPHY_SHADOW_EN 0x80 | 1673 | #define MII_TG3_EPHY_SHADOW_EN 0x80 |
1669 | 1674 | ||
1675 | #define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */ | ||
1676 | #define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000 | ||
1677 | |||
1670 | #define MII_TG3_TEST1 0x1e | 1678 | #define MII_TG3_TEST1 0x1e |
1671 | #define MII_TG3_TEST1_TRIM_EN 0x0010 | 1679 | #define MII_TG3_TEST1_TRIM_EN 0x0010 |
1672 | #define MII_TG3_TEST1_CRC_EN 0x8000 | 1680 | #define MII_TG3_TEST1_CRC_EN 0x8000 |