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authorMatt Carlson <mcarlson@broadcom.com>2008-05-02 19:49:29 -0400
committerDavid S. Miller <davem@davemloft.net>2008-05-02 19:49:29 -0400
commit7c5026aa9b81dd45df8d3f4e0be73e485976a8b6 (patch)
tree09b0e14566d630f1b8d3225b6fda0c2a862519e9 /drivers/net/tg3.h
parent109115e1991824b88306b374b763d6857b292aeb (diff)
tg3: Add link state reporting to UMP firmware
All variants of the 5714, 5715, and 5780 offer a feature called the "Universal Management Port". This feature is implemented in firmware and is largely transparent to the driver, except... It turns out that the UMP firmware needs to know the current status of the link. Because the firmware cannot touch the PHY registers while the driver is in control of the device, it needs the driver to report link status changes through an additional handshaking mechanism. Without this handshake, it has been observed in the field that the UMP firmware will not operate correctly. This patch implements the new handshake with the UMP firmware. Since the handshake uses the same mechanism ASF heartbeats use, code was added to detect and wait for completion of a pending previous event. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index bf387ff9bc15..0404f93baa29 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1429,6 +1429,7 @@
1429#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1429#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1430#define GRC_TIMER 0x0000680c 1430#define GRC_TIMER 0x0000680c
1431#define GRC_RX_CPU_EVENT 0x00006810 1431#define GRC_RX_CPU_EVENT 0x00006810
1432#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1432#define GRC_RX_TIMER_REF 0x00006814 1433#define GRC_RX_TIMER_REF 0x00006814
1433#define GRC_RX_CPU_SEM 0x00006818 1434#define GRC_RX_CPU_SEM 0x00006818
1434#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1435#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
@@ -1676,6 +1677,7 @@
1676#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 1677#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1677#define FWCMD_NICDRV_FIX_DMAR 0x00000005 1678#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1678#define FWCMD_NICDRV_FIX_DMAW 0x00000006 1679#define FWCMD_NICDRV_FIX_DMAW 0x00000006
1680#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
1679#define FWCMD_NICDRV_ALIVE2 0x0000000d 1681#define FWCMD_NICDRV_ALIVE2 0x0000000d
1680#define FWCMD_NICDRV_ALIVE3 0x0000000e 1682#define FWCMD_NICDRV_ALIVE3 0x0000000e
1681#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 1683#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c