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authorDavid S. Miller <davem@sunset.davemloft.net>2006-06-09 14:58:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-09 15:03:51 -0400
commitf49639e643e69ff233b14966b8d48541d2e17517 (patch)
tree8faeabd3bfc855f0a0a5a5a37d9fdbeed27a3f20 /drivers/net/tg3.h
parent5224e6cc3ab5ae03895bbb67f4a26ce72e62ce58 (diff)
[TG3]: Handle Sun onboard tg3 chips more correctly.
Get rid of all the SUN_570X logic and instead: 1) Make sure MEMARB_ENABLE is set when we probe the SRAM for config information. If that is off we will get timeouts. 2) Always try to sync with the firmware, if there is no firmware running do not treat it as an error and instead just report it the first time we notice this condition. 3) If there is no valid SRAM signature, assume the device is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT. Update driver version and release date. With help from Michael Chan and Fabio Massimo Di Nitto. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 0e29b885d449..ff0faab94bd5 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2184,7 +2184,7 @@ struct tg3 {
2184#define TG3_FLAG_INIT_COMPLETE 0x80000000 2184#define TG3_FLAG_INIT_COMPLETE 0x80000000
2185 u32 tg3_flags2; 2185 u32 tg3_flags2;
2186#define TG3_FLG2_RESTART_TIMER 0x00000001 2186#define TG3_FLG2_RESTART_TIMER 0x00000001
2187#define TG3_FLG2_SUN_570X 0x00000002 2187/* 0x00000002 available */
2188#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 2188#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2189#define TG3_FLG2_IS_5788 0x00000008 2189#define TG3_FLG2_IS_5788 0x00000008
2190#define TG3_FLG2_MAX_RXPEND_64 0x00000010 2190#define TG3_FLG2_MAX_RXPEND_64 0x00000010
@@ -2216,6 +2216,7 @@ struct tg3 {
2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) 2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2217#define TG3_FLG2_1SHOT_MSI 0x10000000 2217#define TG3_FLG2_1SHOT_MSI 0x10000000
2218#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2218#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2219#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2219 2220
2220 u32 split_mode_max_reqs; 2221 u32 split_mode_max_reqs;
2221#define SPLIT_MODE_5704_MAX_REQ 3 2222#define SPLIT_MODE_5704_MAX_REQ 3